[clang] [llvm] [RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (PR #117169)

[Sudharsan Veeravalli via llvm-commits]

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@@ -329,6 +329,9 @@ The primary goal of experimental support is to assist in the process of ratifica
 ``experimental-smctr``, ``experimental-ssctr``
   LLVM implements the `1.0-rc3 specification <https://github.com/riscv/riscv-control-transfer-records/releases/tag/v1.0_rc3>`__.
 
+``experimental-xqcicsr``
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svs-quic wrote:

Thanks. I've moved it to the Vendor Extensions section.

https://github.com/llvm/llvm-project/pull/117169