[llvm] [hexagon] Add support for llvm.debugtrap (PR #117049)
Brian Cain via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 20 12:59:28 PST 2024
https://github.com/androm3da created https://github.com/llvm/llvm-project/pull/117049
Also: set `hasSideEffects` on `Y2_break` instruction.
>From 9dbcb9632f55f32fd51153a97ca113d221377c83 Mon Sep 17 00:00:00 2001
From: Brian Cain <bcain at quicinc.com>
Date: Wed, 20 Nov 2024 12:34:33 -0800
Subject: [PATCH] [hexagon] Add support for llvm.debugtrap
Also: set `hasSideEffects` on `Y2_break` instruction.
---
.../lib/Target/Hexagon/HexagonDepInstrInfo.td | 1 +
.../Target/Hexagon/HexagonISelLowering.cpp | 3 ++-
llvm/lib/Target/Hexagon/HexagonPatterns.td | 1 +
llvm/test/CodeGen/Hexagon/trap-crash.ll | 19 ++++++++++++-------
4 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
index 0351217f441df2..7935c4b86af535 100644
--- a/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
+++ b/llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td
@@ -40411,6 +40411,7 @@ def Y2_break : HInst<
tc_55255f2b, TypeCR>, Enc_e3b0c4 {
let Inst{13-0} = 0b00000000000000;
let Inst{31-16} = 0b0110110000100000;
+let hasSideEffects = 1;
let isSolo = 1;
}
def Y2_ciad : HInst<
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 08a9c95ee7359f..77d8494921773b 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1498,7 +1498,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
// All operations default to "legal", except:
// - indexed loads and stores (pre-/post-incremented),
// - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
- // ConstantFP, DEBUGTRAP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
+ // ConstantFP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
// FLOG, FLOG2, FLOG10, FMAXNUM, FMINNUM, FNEARBYINT, FRINT, FROUND, TRAP,
// FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
// which default to "expand" for at least one type.
@@ -1507,6 +1507,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
setOperationAction(ISD::TRAP, MVT::Other, Legal);
+ setOperationAction(ISD::DEBUGTRAP, MVT::Other, Legal);
setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
setOperationAction(ISD::JumpTable, MVT::i32, Custom);
setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index baa552fcd220d8..fa6d4c6058f217 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -3384,6 +3384,7 @@ def HexagonBARRIER: SDNode<"HexagonISD::BARRIER", SDTNone, [SDNPHasChain]>;
def: Pat<(HexagonBARRIER), (Y2_barrier)>;
def: Pat<(trap), (PS_crash)>;
+def: Pat<(debugtrap), (Y2_break)>;
// Read cycle counter.
def SDTInt64Leaf: SDTypeProfile<1, 0, [SDTCisVT<0, i64>]>;
diff --git a/llvm/test/CodeGen/Hexagon/trap-crash.ll b/llvm/test/CodeGen/Hexagon/trap-crash.ll
index e940d98b620c57..a0afe5fdd30414 100644
--- a/llvm/test/CodeGen/Hexagon/trap-crash.ll
+++ b/llvm/test/CodeGen/Hexagon/trap-crash.ll
@@ -1,20 +1,25 @@
-; RUN: llc -march=hexagon < %s | FileCheck %s
+; RUN: llc -march=hexagon --verify-machineinstrs < %s | FileCheck %s
; Generate code that is guaranteed to crash. At the moment, it's a
; misaligned load.
+; CHECK-LABEL: f0
; CHECK: memd(##3134984174)
target triple = "hexagon"
-; Function Attrs: noreturn nounwind
-define i32 @f0() #0 {
+define i32 @f0() noreturn nounwind {
entry:
tail call void @llvm.trap()
unreachable
}
-; Function Attrs: cold noreturn nounwind
-declare void @llvm.trap() #1
+; CHECK-LABEL: f1
+; CHECK: brkpt
+define i32 @f1() noreturn nounwind {
+entry:
+ tail call void @llvm.debugtrap()
+ unreachable
+}
-attributes #0 = { noreturn nounwind "target-cpu"="hexagonv60" }
-attributes #1 = { cold noreturn nounwind }
+declare void @llvm.trap() nounwind
+declare void @llvm.debugtrap() nounwind
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