[llvm] [X86] Add APX imulzu support. (PR #116806)

[Daniel Zabawa via llvm-commits]

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@@ -58919,6 +58919,12 @@ bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const {
     if (IsFoldableAtomicRMW(N0, Op) ||
         (Commute && IsFoldableAtomicRMW(N1, Op)))
       return false;
+    // When ZU is enabled, we prefer to not promote for MUL by a constant,
+    // since a 16b imulzu will not incur partial-write stalls, and may be
+    // able to fold away a zero-extend of the 16b result.
+    if (Subtarget.hasZU() && Op.getOpcode() == ISD::MUL &&
+        (isa<ConstantSDNode>(N0) || isa<ConstantSDNode>(N1)))
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daniel-zabawa wrote:

I am following the same rationale as, e.g. https://github.com/llvm/llvm-project/commit/20683de70e43fa73536ac1e8ce4082604048d040, and assuming the 16b form is preferable in the absence of partial-write stalls. 

I have no objection to removing this if that's not accurate.

https://github.com/llvm/llvm-project/pull/116806