[llvm] a9b3ec1 - [MachineLICM] Add test case showing load hoisted across memory barrier.
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 20 07:10:33 PST 2024
Author: Florian Hahn
Date: 2024-11-20T15:10:19Z
New Revision: a9b3ec154d7ab2d0896ac5c9f1e9a1266a37be80
URL: https://github.com/llvm/llvm-project/commit/a9b3ec154d7ab2d0896ac5c9f1e9a1266a37be80
DIFF: https://github.com/llvm/llvm-project/commit/a9b3ec154d7ab2d0896ac5c9f1e9a1266a37be80.diff
LOG: [MachineLICM] Add test case showing load hoisted across memory barrier.
Added:
Modified:
llvm/test/CodeGen/AArch64/machine-licm-hoist-load.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/machine-licm-hoist-load.ll b/llvm/test/CodeGen/AArch64/machine-licm-hoist-load.ll
index e8dafd5e8fbabe..932a5af264a000 100644
--- a/llvm/test/CodeGen/AArch64/machine-licm-hoist-load.ll
+++ b/llvm/test/CodeGen/AArch64/machine-licm-hoist-load.ll
@@ -497,6 +497,35 @@ for.exit: ; preds = %for.body
ret i64 %spec.select
}
+ at a = external local_unnamed_addr global i32, align 4
+
+; FIXME: Load hoisted out of the loop across memory barriers.
+define i32 @load_between_memory_barriers() {
+; CHECK-LABEL: load_between_memory_barriers:
+; CHECK: // %bb.0:
+; CHECK-NEXT: adrp x8, :got:a
+; CHECK-NEXT: ldr x8, [x8, :got_lo12:a]
+; CHECK-NEXT: ldr w0, [x8]
+; CHECK-NEXT: .LBB8_1: // %loop
+; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: //MEMBARRIER
+; CHECK-NEXT: //MEMBARRIER
+; CHECK-NEXT: cbz w0, .LBB8_1
+; CHECK-NEXT: // %bb.2: // %exit
+; CHECK-NEXT: ret
+ br label %loop
+
+loop:
+ fence syncscope("singlethread") acq_rel
+ %l = load i32, ptr @a, align 4
+ fence syncscope("singlethread") acq_rel
+ %c = icmp eq i32 %l, 0
+ br i1 %c, label %loop, label %exit
+
+exit:
+ ret i32 %l
+}
+
declare i32 @bcmp(ptr, ptr, i64)
declare i32 @memcmp(ptr, ptr, i64)
declare void @func()
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