[llvm] 71b87d1 - [LLVM][SVE] Ensure all fixed length mask bits are defined. (#116819)
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Wed Nov 20 05:54:53 PST 2024
Author: Paul Walker
Date: 2024-11-20T13:54:50Z
New Revision: 71b87d12678cbdb900c3a8fb673dcaf14d0433be
URL: https://github.com/llvm/llvm-project/commit/71b87d12678cbdb900c3a8fb673dcaf14d0433be
DIFF: https://github.com/llvm/llvm-project/commit/71b87d12678cbdb900c3a8fb673dcaf14d0433be.diff
LOG: [LLVM][SVE] Ensure all fixed length mask bits are defined. (#116819)
convertFixedMaskToScalableVector expects the mask input to honour the
BoolContents scheme employed by the target. For AArch64 this means a
mask should be zero or all ones, and thus when promoting a mask we must
use a sign extend.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 961a90e51571d1..7ab3fc06715ec8 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -28163,7 +28163,7 @@ SDValue AArch64TargetLowering::LowerFixedLengthVectorMLoadToSVE(
if (VT.getScalarSizeInBits() > Mask.getValueType().getScalarSizeInBits()) {
assert(Load->getExtensionType() != ISD::NON_EXTLOAD &&
"Incorrect mask type");
- Mask = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Mask);
+ Mask = DAG.getNode(ISD::SIGN_EXTEND, DL, VT, Mask);
}
Mask = convertFixedMaskToScalableVector(Mask, DAG);
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
index 9055b2efba3282..48a642c908bfe6 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
@@ -2677,7 +2677,7 @@ define <3 x i32> @masked_load_zext_v3i32(ptr %load_ptr, <3 x i1> %pm) {
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: lsl z0.h, z0.h, #15
; CHECK-NEXT: asr z0.h, z0.h, #15
-; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: sunpklo z0.s, z0.h
; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #0
; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
@@ -2750,7 +2750,7 @@ define <3 x i32> @masked_load_sext_v3i32(ptr %load_ptr, <3 x i1> %pm) {
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: lsl z0.h, z0.h, #15
; CHECK-NEXT: asr z0.h, z0.h, #15
-; CHECK-NEXT: uunpklo z0.s, z0.h
+; CHECK-NEXT: sunpklo z0.s, z0.h
; CHECK-NEXT: cmpne p0.s, p0/z, z0.s, #0
; CHECK-NEXT: ld1sh { z0.s }, p0/z, [x0]
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
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