[llvm] [AArch64][Codegen] Improve small shufflevector/concat lowering for SME (PR #116662)

[Benjamin Maxwell via llvm-commits]

================
@@ -26161,6 +26238,8 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
 
     break;
   }
+  case AArch64ISD::ZIP1:
+    return performZIP1Combine(N, DAG);
----------------
MacDue wrote:

Improved this by attempting widening the shuffle before falling back to the SVE TBL :+1:. 

I've removed the ZIP1 fold now (which does mean a few extra ZIPs are generated in some cases, but it's probably not significant enough to justify the large folder).

https://github.com/llvm/llvm-project/pull/116662