[llvm] 2bf6751 - [RISCV] Add IsRV32 some patterns in RISCVInstrInfoXTHead.td.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-11-19T21:41:14-08:00
New Revision: 2bf6751522e8683d719d5651a4555147dd7d6acd

URL: https://github.com/llvm/llvm-project/commit/2bf6751522e8683d719d5651a4555147dd7d6acd
DIFF: https://github.com/llvm/llvm-project/commit/2bf6751522e8683d719d5651a4555147dd7d6acd.diff

LOG: [RISCV] Add IsRV32 some patterns in RISCVInstrInfoXTHead.td.

This restores the code to its original state before I experimented
with making i32 a legal type.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
index 90747a6b745cfc..99186ec7360e74 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
@@ -769,7 +769,9 @@ defm : LdIdxPat<zextloadi16, TH_LRHU>;
 
 defm : StIdxPat<truncstorei8, TH_SRB, GPR>;
 defm : StIdxPat<truncstorei16, TH_SRH, GPR>;
+}
 
+let Predicates = [HasVendorXTHeadMemIdx, IsRV32] in {
 defm : LdIdxPat<load, TH_LRW, i32>;
 defm : StIdxPat<store, TH_SRW, GPR, i32>;
 }