[llvm] [AArch64] Fix SDNode type mismatches between *.td files and ISel (PR #116523)

[Sergei Barannikov via llvm-commits]

s-barannikov wrote:

There is one more issue that I haven't dug deeply into -- `REVD_MERGE_PASSTHRU` is sometimes created with an extra operand, too. Here is the relevant piece of backtrace:
```
  t11: nxv2i1 = AArch64ISD::PTRUE TargetConstant:i32<4>
  t16: nxv2i64 = insert_subvector undef:nxv2i64, t5, Constant:i64<0>
t17: nxv2i64 = AArch64ISD::REVD_MERGE_PASSTHRU t11, t16, undef:nxv2i64, undef:nxv2i64

#17 0x000079e0721911f3 llvm::AArch64TargetLowering::LowerToPredicatedOp(llvm::SDValue, llvm::SelectionDAG&, unsigned int) const /home/sergei/Projects/llvm-nmc/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:28179:28
#18 0x000079e0721fb259 llvm::AArch64TargetLowering::LowerFixedLengthVECTOR_SHUFFLEToSVE(llvm::SDValue, llvm::SelectionDAG&) const /home/sergei/Projects/llvm-nmc/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:28856:14
#19 0x000079e0721c4959 llvm::AArch64TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const /home/sergei/Projects/llvm-nmc/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:13329:12
```

`LowerToPredicatedOp` starts with filling `Operands` vector with `Pg`, then adds two operands from `ISD::VECTOR_SHUFFLE`, and finally adds an `Undef` operand because `isMergePassthruOpcode` returns true for this node. This results in four operands, although there should be only three.


https://github.com/llvm/llvm-project/pull/116523