[llvm] [feature][riscv] handle target address calculation in llvm-objdump disassembly for riscv (PR #109914)

via llvm-commits llvm-commits at lists.llvm.org
Tue Nov 19 14:41:25 PST 2024


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<details>
<summary>
You can test this locally with the following command:
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``````````bash
git-clang-format --diff c2717a89b8437d041d532c7b2c535ca4f4b35872 3fc4e31d140067a5fe1cdd7340494403d912edaa --extensions h,cpp -- llvm/include/llvm/MC/MCInstrAnalysis.h llvm/lib/MC/MCInstrAnalysis.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp llvm/tools/llvm-objdump/llvm-objdump.cpp
``````````

</details>

<details>
<summary>
View the diff from clang-format here.
</summary>

``````````diff
diff --git a/llvm/include/llvm/MC/MCInstrAnalysis.h b/llvm/include/llvm/MC/MCInstrAnalysis.h
index 1c32d4177e..4274a29adc 100644
--- a/llvm/include/llvm/MC/MCInstrAnalysis.h
+++ b/llvm/include/llvm/MC/MCInstrAnalysis.h
@@ -183,9 +183,9 @@ public:
 
   /// Given an instruction that accesses a menory address, try to compute
   /// the target address. Return true success, and the address in Target.
-  virtual bool
-  evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
-                      uint64_t &Target, int ArchRegWidth) const;
+  virtual bool evaluateInstruction(const MCInst &Inst, uint64_t Addr,
+                                   uint64_t Size, uint64_t &Target,
+                                   int ArchRegWidth) const;
 
   /// Given an instruction tries to get the address of a memory operand. Returns
   /// the address on success.
diff --git a/llvm/lib/MC/MCInstrAnalysis.cpp b/llvm/lib/MC/MCInstrAnalysis.cpp
index 41a5563752..2a7f3655a6 100644
--- a/llvm/lib/MC/MCInstrAnalysis.cpp
+++ b/llvm/lib/MC/MCInstrAnalysis.cpp
@@ -30,9 +30,9 @@ bool MCInstrAnalysis::evaluateBranch(const MCInst & /*Inst*/, uint64_t /*Addr*/,
   return false;
 }
 
-bool MCInstrAnalysis::evaluateInstruction(const MCInst &Inst,
-                                          uint64_t Addr, uint64_t Size,
-                                          uint64_t &Target, int ArchRegWidth) const {
+bool MCInstrAnalysis::evaluateInstruction(const MCInst &Inst, uint64_t Addr,
+                                          uint64_t Size, uint64_t &Target,
+                                          int ArchRegWidth) const {
   return false;
 }
 
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 664f95ddd8..42e493d2ef 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -180,35 +180,34 @@ public:
     }
 
     switch (Inst.getOpcode()) {
-      case RISCV::LUI: {
-        setGPRState(Inst.getOperand(0).getReg(), 
-                    SignExtend64<32>(Inst.getOperand(1).getImm() << 12));
-        break;
-      }
-      case RISCV::C_LUI: {
-        MCRegister Reg = Inst.getOperand(0).getReg();
-        if (Reg == RISCV::X2)
-          break;
-        setGPRState(Reg, SignExtend64<18>(Inst.getOperand(1).getImm() << 12));
-        break;
-
-      }
-      case RISCV::AUIPC: {
-        setGPRState(Inst.getOperand(0).getReg(), 
-                    Addr + SignExtend64<32>(Inst.getOperand(1).getImm() << 12));
-        break;
-      }
-      default: {
-        // Clear the state of all defined registers for instructions that we don't
-        // explicitly support.
-        auto NumDefs = Info->get(Inst.getOpcode()).getNumDefs();
-        for (unsigned I = 0; I < NumDefs; ++I) {
-          auto DefReg = Inst.getOperand(I).getReg();
-          if (isGPR(DefReg))
-            setGPRState(DefReg, std::nullopt);
-        }
+    case RISCV::LUI: {
+      setGPRState(Inst.getOperand(0).getReg(),
+                  SignExtend64<32>(Inst.getOperand(1).getImm() << 12));
+      break;
+    }
+    case RISCV::C_LUI: {
+      MCRegister Reg = Inst.getOperand(0).getReg();
+      if (Reg == RISCV::X2)
         break;
+      setGPRState(Reg, SignExtend64<18>(Inst.getOperand(1).getImm() << 12));
+      break;
+    }
+    case RISCV::AUIPC: {
+      setGPRState(Inst.getOperand(0).getReg(),
+                  Addr + SignExtend64<32>(Inst.getOperand(1).getImm() << 12));
+      break;
+    }
+    default: {
+      // Clear the state of all defined registers for instructions that we don't
+      // explicitly support.
+      auto NumDefs = Info->get(Inst.getOpcode()).getNumDefs();
+      for (unsigned I = 0; I < NumDefs; ++I) {
+        auto DefReg = Inst.getOperand(I).getReg();
+        if (isGPR(DefReg))
+          setGPRState(DefReg, std::nullopt);
       }
+      break;
+    }
     }
   }
 
@@ -248,89 +247,91 @@ public:
 
   bool evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
                            uint64_t &Target, int ArchRegWidth) const override {
-    switch(Inst.getOpcode()) {
-      default:
-        return false;
-      case RISCV::ADDI: {
-        if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
-          uint64_t Mask = ~((uint64_t)0) >> (64 - ArchRegWidth);
-          Target = *TargetRegState + SignExtend64<12>(Inst.getOperand(2).getImm());
-          Target &= Mask;
-          return true;
-        }
-        break;
+    switch (Inst.getOpcode()) {
+    default:
+      return false;
+    case RISCV::ADDI: {
+      if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
+        uint64_t Mask = ~((uint64_t)0) >> (64 - ArchRegWidth);
+        Target =
+            *TargetRegState + SignExtend64<12>(Inst.getOperand(2).getImm());
+        Target &= Mask;
+        return true;
       }
-      case RISCV::ADDIW: {
-        if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
-          uint64_t Mask = ~((uint64_t)0) >> 32;
-          Target  = *TargetRegState + SignExtend64<12>(Inst.getOperand(2).getImm());
-          Target &= Mask;
-          Target = SignExtend64<32>(Target);
-          return true;
-        }
-        break;
+      break;
+    }
+    case RISCV::ADDIW: {
+      if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
+        uint64_t Mask = ~((uint64_t)0) >> 32;
+        Target =
+            *TargetRegState + SignExtend64<12>(Inst.getOperand(2).getImm());
+        Target &= Mask;
+        Target = SignExtend64<32>(Target);
+        return true;
       }
-      case RISCV::C_ADDI: {
-        int64_t Offset = Inst.getOperand(2).getImm();
-        if (Offset == 0)
-          break;
-        if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
-          Target = *TargetRegState + SignExtend64<6>(Offset);
-          return true;
-        }
+      break;
+    }
+    case RISCV::C_ADDI: {
+      int64_t Offset = Inst.getOperand(2).getImm();
+      if (Offset == 0)
         break;
+      if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
+        Target = *TargetRegState + SignExtend64<6>(Offset);
+        return true;
       }
-      case RISCV::C_ADDIW: {
-        int64_t Offset = Inst.getOperand(2).getImm(); 
-        if (Offset == 0)
-          break;
-        if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
-          uint64_t Mask = ~((uint64_t)0) >> 32;
-          Target &= Mask;
-          Target = *TargetRegState + SignExtend64<6>(Offset);
-          Target = SignExtend64<32>(Target);
-          return true;
-        }
+      break;
+    }
+    case RISCV::C_ADDIW: {
+      int64_t Offset = Inst.getOperand(2).getImm();
+      if (Offset == 0)
         break;
-      }
-      case RISCV::LB:
-      case RISCV::LH:
-      case RISCV::LD:
-      case RISCV::LW:
-      case RISCV::LBU:
-      case RISCV::LHU:
-      case RISCV::LWU:
-      case RISCV::SB:
-      case RISCV::SH:
-      case RISCV::SW:
-      case RISCV::SD:
-      case RISCV::FLH:
-      case RISCV::FLW:
-      case RISCV::FLD:
-      case RISCV::FSH:
-      case RISCV::FSW:
-      case RISCV::FSD: {
-        int64_t Offset = SignExtend64<12>(Inst.getOperand(2).getImm());
-        if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg()))
-          Target = *TargetRegState + Offset;
-        else
-          Target = Offset;
+      if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
+        uint64_t Mask = ~((uint64_t)0) >> 32;
+        Target &= Mask;
+        Target = *TargetRegState + SignExtend64<6>(Offset);
+        Target = SignExtend64<32>(Target);
         return true;
       }
-      case RISCV::C_LD:
-      case RISCV::C_SD:
-      case RISCV::C_FLD:
-      case RISCV::C_FSD:
-      case RISCV::C_SW:
-      case RISCV::C_LW:
-      case RISCV::C_FSW:
-      case RISCV::C_FLW: {
-        if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
-          Target = *TargetRegState + Inst.getOperand(2).getImm();
-          return true;
-        }
-        break;
+      break;
+    }
+    case RISCV::LB:
+    case RISCV::LH:
+    case RISCV::LD:
+    case RISCV::LW:
+    case RISCV::LBU:
+    case RISCV::LHU:
+    case RISCV::LWU:
+    case RISCV::SB:
+    case RISCV::SH:
+    case RISCV::SW:
+    case RISCV::SD:
+    case RISCV::FLH:
+    case RISCV::FLW:
+    case RISCV::FLD:
+    case RISCV::FSH:
+    case RISCV::FSW:
+    case RISCV::FSD: {
+      int64_t Offset = SignExtend64<12>(Inst.getOperand(2).getImm());
+      if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg()))
+        Target = *TargetRegState + Offset;
+      else
+        Target = Offset;
+      return true;
+    }
+    case RISCV::C_LD:
+    case RISCV::C_SD:
+    case RISCV::C_FLD:
+    case RISCV::C_FSD:
+    case RISCV::C_SW:
+    case RISCV::C_LW:
+    case RISCV::C_FSW:
+    case RISCV::C_FLW: {
+      if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
+        Target = *TargetRegState + Inst.getOperand(2).getImm();
+        return true;
       }
+      break;
+    }
     }
     return false;
   }
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index b45eb70312..7657109673 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -2323,9 +2323,13 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
           if (Disassembled && DT->InstrAnalysis) {
             llvm::raw_ostream *TargetOS = &FOS;
             uint64_t Target;
-            int TargetArchBitWidth = DT->SubtargetInfo->getTargetTriple().getArchPointerBitWidth();
-            bool PrintTarget = DT->InstrAnalysis->evaluateBranch(Inst, SectionAddr + Index, Size, Target) || 
-                               DT->InstrAnalysis->evaluateInstruction(Inst, SectionAddr + Index, Size, Target, TargetArchBitWidth);
+            int TargetArchBitWidth =
+                DT->SubtargetInfo->getTargetTriple().getArchPointerBitWidth();
+            bool PrintTarget = DT->InstrAnalysis->evaluateBranch(
+                                   Inst, SectionAddr + Index, Size, Target) ||
+                               DT->InstrAnalysis->evaluateInstruction(
+                                   Inst, SectionAddr + Index, Size, Target,
+                                   TargetArchBitWidth);
             if (!PrintTarget) {
               if (std::optional<uint64_t> MaybeTarget =
                       DT->InstrAnalysis->evaluateMemoryOperandAddress(
@@ -2361,9 +2365,11 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
                     [=](const std::pair<uint64_t, SectionRef> &O) {
                       return O.first <= Target;
                     });
-                uint64_t TargetSecAddr = It == SectionAddresses.end() ? It->first : 0;
+                uint64_t TargetSecAddr =
+                    It == SectionAddresses.end() ? It->first : 0;
                 bool FoundSymbols = false;
-                // missing case where begin == end as in this case, we are to return 0
+                // missing case where begin == end as in this case, we are to
+                // return 0
                 while (It != SectionAddresses.begin()) {
                   --It;
                   if (It->first != TargetSecAddr) {
@@ -2382,7 +2388,8 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
                 TargetSectionSymbols.push_back(&Symbols);
               }
               if (AbsoluteFirst)
-                TargetSectionSymbols.insert(TargetSectionSymbols.begin(), &AbsoluteSymbols);
+                TargetSectionSymbols.insert(TargetSectionSymbols.begin(),
+                                            &AbsoluteSymbols);
               else
                 TargetSectionSymbols.push_back(&AbsoluteSymbols);
 
@@ -2410,8 +2417,9 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
                   break;
               }
 
-              // Branch and instruction targets are printed just after the instructions.
-              // Print the labels corresponding to the target if there's any.
+              // Branch and instruction targets are printed just after the
+              // instructions. Print the labels corresponding to the target if
+              // there's any.
               bool BBAddrMapLabelAvailable = BBAddrMapLabels.count(Target);
               bool LabelAvailable = AllLabels.count(Target);
 
@@ -2491,7 +2499,7 @@ disassembleObject(ObjectFile &Obj, const ObjectFile &DbgObj,
                           << ">";
               } else if (LabelAvailable) {
                 *TargetOS << " <" << AllLabels[Target] << ">";
-              } 
+              }
               // By convention, each record in the comment stream should be
               // terminated.
               if (TargetOS == &CommentStream)

``````````

</details>


https://github.com/llvm/llvm-project/pull/109914


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