[llvm] [feature][riscv] handle target address calculation in llvm-objdump disassembly for riscv (PR #109914)

[Arjun Patel via llvm-commits]

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@@ -230,6 +246,97 @@ class RISCVMCInstrAnalysis : public MCInstrAnalysis {
     return false;
   }
 
+  bool evaluateInstruction(const MCInst &Inst, uint64_t Addr, uint64_t Size,
+                           uint64_t &Target) const override {
+    switch(Inst.getOpcode()) {
+      default:
+        return false;
+      case RISCV::ADDI: {
+        if (auto TargetRegState = getGPRState(Inst.getOperand(1).getReg())) {
+          // TODO: Figure out ways to find the actual value of XLEN during analysis
+          int XLEN = 32;
+          uint64_t Mask = ~((uint64_t)0) >> (64 - XLEN);
+          Target = *TargetRegState + SignExtend64<12>(Inst.getOperand(2).getImm());
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arjunUpatel wrote:

I think so. I was going off of suggestions provided in a previous [review](https://github.com/llvm/llvm-project/pull/109914#discussion_r1775677211) where we concluded that the immediates of LUI and AUIPC should be sign extended and extrapolated that decision to the rest of the instructions. Any holes in my understanding as to why those should be sign extended but not the immediates of ADDI in this case (and other instructions)?

I ended up digging through the RISCV spec and noticed it specifically states that 
> ADDI adds the sign-extended 12-bit immediate ...

this was true for other instructions as well, but not AUIPC and LUI. Following this distinction, I am assuming that the immediate values for AUIPC and LUI are not stored in sign extended form (while others are) leading to the sign extension being needed for these instructions and not others. Any insights appreciated :)

https://github.com/llvm/llvm-project/pull/109914