[llvm] [SDAG] Generalize FSINCOS type legalization (NFC) (PR #116848)
Benjamin Maxwell via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 19 09:51:25 PST 2024
https://github.com/MacDue updated https://github.com/llvm/llvm-project/pull/116848
>From 3346889838e445cdba0fd667a38cda8451294efc Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: Tue, 19 Nov 2024 17:33:14 +0000
Subject: [PATCH 1/2] [SDAG] Generalize FSINCOS type legalization (NFC)
There's nothing that specific to FSINCOS about these; they could be used
for similar nodes in the future.
---
.../SelectionDAG/LegalizeFloatTypes.cpp | 40 +++++++++++--------
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 5 ++-
2 files changed, 26 insertions(+), 19 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 5abd7cb97bda57..572e7e9b64fc49 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -791,28 +791,29 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FFREXP(SDNode *N) {
return ReturnVal;
}
-SDValue DAGTypeLegalizer::SoftenFloatRes_FSINCOS(SDNode *N) {
- assert(!N->isStrictFPOpcode() && "strictfp not implemented for fsincos");
+SDValue
+DAGTypeLegalizer::SoftenFloatRes_UnaryWithTwoFPResults(SDNode *N,
+ RTLIB::Libcall LC) {
+ assert(!N->isStrictFPOpcode() && "strictfp not implemented");
EVT VT = N->getValueType(0);
- RTLIB::Libcall LC = RTLIB::getFSINCOS(VT);
if (!TLI.getLibcallName(LC))
return SDValue();
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
- SDValue StackSlotSin = DAG.CreateStackTemporary(NVT);
- SDValue StackSlotCos = DAG.CreateStackTemporary(NVT);
+ SDValue FirstResultSlot = DAG.CreateStackTemporary(NVT);
+ SDValue SecondResultSlot = DAG.CreateStackTemporary(NVT);
SDLoc DL(N);
TargetLowering::MakeLibCallOptions CallOptions;
- std::array Ops{GetSoftenedFloat(N->getOperand(0)), StackSlotSin,
- StackSlotCos};
- std::array OpsVT{VT, StackSlotSin.getValueType(),
- StackSlotCos.getValueType()};
+ std::array Ops{GetSoftenedFloat(N->getOperand(0)), FirstResultSlot,
+ SecondResultSlot};
+ std::array OpsVT{VT, FirstResultSlot.getValueType(),
+ SecondResultSlot.getValueType()};
// TODO: setTypeListBeforeSoften can't properly express multiple return types,
- // but since both returns have the same type for sincos it should be okay.
+ // but since both returns have the same type it should be okay.
CallOptions.setTypeListBeforeSoften({OpsVT}, VT, true);
auto [ReturnVal, Chain] = TLI.makeLibCall(DAG, LC, NVT, Ops, CallOptions, DL,
@@ -824,12 +825,17 @@ SDValue DAGTypeLegalizer::SoftenFloatRes_FSINCOS(SDNode *N) {
MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
return DAG.getLoad(NVT, DL, Chain, StackSlot, PtrInfo);
};
- SetSoftenedFloat(SDValue(N, 0), CreateStackLoad(StackSlotSin));
- SetSoftenedFloat(SDValue(N, 1), CreateStackLoad(StackSlotCos));
+ SetSoftenedFloat(SDValue(N, 0), CreateStackLoad(FirstResultSlot));
+ SetSoftenedFloat(SDValue(N, 1), CreateStackLoad(SecondResultSlot));
return SDValue();
}
+SDValue DAGTypeLegalizer::SoftenFloatRes_FSINCOS(SDNode *N) {
+ return SoftenFloatRes_UnaryWithTwoFPResults(
+ N, RTLIB::getFSINCOS(N->getValueType(0)));
+}
+
SDValue DAGTypeLegalizer::SoftenFloatRes_FREM(SDNode *N) {
return SoftenFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
RTLIB::REM_F32,
@@ -2761,8 +2767,8 @@ void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) {
case ISD::FFREXP: R = PromoteFloatRes_FFREXP(N); break;
case ISD::FSINCOS:
- R = PromoteFloatRes_FSINCOS(N);
- break;
+ R = PromoteFloatRes_UnaryWithTwoFPResults(N);
+ break;
case ISD::FP_ROUND: R = PromoteFloatRes_FP_ROUND(N); break;
case ISD::STRICT_FP_ROUND:
@@ -2959,7 +2965,7 @@ SDValue DAGTypeLegalizer::PromoteFloatRes_FFREXP(SDNode *N) {
return Res;
}
-SDValue DAGTypeLegalizer::PromoteFloatRes_FSINCOS(SDNode *N) {
+SDValue DAGTypeLegalizer::PromoteFloatRes_UnaryWithTwoFPResults(SDNode *N) {
EVT VT = N->getValueType(0);
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
SDValue Op = GetPromotedFloat(N->getOperand(0));
@@ -3223,7 +3229,7 @@ void DAGTypeLegalizer::SoftPromoteHalfResult(SDNode *N, unsigned ResNo) {
case ISD::FFREXP: R = SoftPromoteHalfRes_FFREXP(N); break;
case ISD::FSINCOS:
- R = SoftPromoteHalfRes_FSINCOS(N);
+ R = SoftPromoteHalfRes_UnaryWithTwoFPResults(N);
break;
case ISD::LOAD: R = SoftPromoteHalfRes_LOAD(N); break;
@@ -3382,7 +3388,7 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfRes_FFREXP(SDNode *N) {
return DAG.getNode(GetPromotionOpcode(NVT, OVT), dl, MVT::i16, Res);
}
-SDValue DAGTypeLegalizer::SoftPromoteHalfRes_FSINCOS(SDNode *N) {
+SDValue DAGTypeLegalizer::SoftPromoteHalfRes_UnaryWithTwoFPResults(SDNode *N) {
EVT OVT = N->getValueType(0);
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), OVT);
SDValue Op = GetSoftPromotedHalf(N->getOperand(0));
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 6eb7628675e641..1703149aca7463 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -557,6 +557,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
// Convert Float Results to Integer.
void SoftenFloatResult(SDNode *N, unsigned ResNo);
SDValue SoftenFloatRes_Unary(SDNode *N, RTLIB::Libcall LC);
+ SDValue SoftenFloatRes_UnaryWithTwoFPResults(SDNode *N, RTLIB::Libcall LC);
SDValue SoftenFloatRes_Binary(SDNode *N, RTLIB::Libcall LC);
SDValue SoftenFloatRes_MERGE_VALUES(SDNode *N, unsigned ResNo);
SDValue SoftenFloatRes_ARITH_FENCE(SDNode *N);
@@ -743,13 +744,13 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
void PromoteFloatResult(SDNode *N, unsigned ResNo);
SDValue PromoteFloatRes_BITCAST(SDNode *N);
SDValue PromoteFloatRes_BinOp(SDNode *N);
+ SDValue PromoteFloatRes_UnaryWithTwoFPResults(SDNode *N);
SDValue PromoteFloatRes_ConstantFP(SDNode *N);
SDValue PromoteFloatRes_EXTRACT_VECTOR_ELT(SDNode *N);
SDValue PromoteFloatRes_FCOPYSIGN(SDNode *N);
SDValue PromoteFloatRes_FMAD(SDNode *N);
SDValue PromoteFloatRes_ExpOp(SDNode *N);
SDValue PromoteFloatRes_FFREXP(SDNode *N);
- SDValue PromoteFloatRes_FSINCOS(SDNode *N);
SDValue PromoteFloatRes_FP_ROUND(SDNode *N);
SDValue PromoteFloatRes_STRICT_FP_ROUND(SDNode *N);
SDValue PromoteFloatRes_LOAD(SDNode *N);
@@ -791,6 +792,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
void SoftPromoteHalfResult(SDNode *N, unsigned ResNo);
SDValue SoftPromoteHalfRes_ARITH_FENCE(SDNode *N);
SDValue SoftPromoteHalfRes_BinOp(SDNode *N);
+ SDValue SoftPromoteHalfRes_UnaryWithTwoFPResults(SDNode *N);
SDValue SoftPromoteHalfRes_BITCAST(SDNode *N);
SDValue SoftPromoteHalfRes_ConstantFP(SDNode *N);
SDValue SoftPromoteHalfRes_EXTRACT_VECTOR_ELT(SDNode *N);
@@ -798,7 +800,6 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
SDValue SoftPromoteHalfRes_FMAD(SDNode *N);
SDValue SoftPromoteHalfRes_ExpOp(SDNode *N);
SDValue SoftPromoteHalfRes_FFREXP(SDNode *N);
- SDValue SoftPromoteHalfRes_FSINCOS(SDNode *N);
SDValue SoftPromoteHalfRes_FP_ROUND(SDNode *N);
SDValue SoftPromoteHalfRes_LOAD(SDNode *N);
SDValue SoftPromoteHalfRes_ATOMIC_LOAD(SDNode *N);
>From d62bd99b68bb6a0fa9e7f87750b2e138b037d2c2 Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: Tue, 19 Nov 2024 17:51:11 +0000
Subject: [PATCH 2/2] Fix format
---
llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 572e7e9b64fc49..3f8d117400efdc 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -2767,8 +2767,8 @@ void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) {
case ISD::FFREXP: R = PromoteFloatRes_FFREXP(N); break;
case ISD::FSINCOS:
- R = PromoteFloatRes_UnaryWithTwoFPResults(N);
- break;
+ R = PromoteFloatRes_UnaryWithTwoFPResults(N);
+ break;
case ISD::FP_ROUND: R = PromoteFloatRes_FP_ROUND(N); break;
case ISD::STRICT_FP_ROUND:
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