[llvm] [Thumb2][ARMAsmParser] Fix processing of `t2STR_{PRE,POST}_imm` when changing to its concrete form (PR #116757)
Kai Luo via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 19 07:50:33 PST 2024
https://github.com/bzEq updated https://github.com/llvm/llvm-project/pull/116757
>From c2da86815d8f0e8722144a2e8d2eea724ed25176 Mon Sep 17 00:00:00 2001
From: Kai Luo <luokai at vivo.com>
Date: Tue, 19 Nov 2024 14:51:07 +0800
Subject: [PATCH 1/4] Fix #97020
---
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 0dc637fc08aca37..99b813473bb9d54 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -9061,11 +9061,9 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
return true;
}
// Aliases for imm syntax of STR instructions.
- case ARM::t2STR_PRE_imm:
- case ARM::t2STR_POST_imm: {
+ case ARM::t2STR_PRE_imm: {
MCInst TmpInst;
- TmpInst.setOpcode(Inst.getOpcode() == ARM::t2STR_PRE_imm ? ARM::t2STR_PRE
- : ARM::t2STR_POST);
+ TmpInst.setOpcode(ARM::t2STR_PRE);
TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
TmpInst.addOperand(Inst.getOperand(0)); // Rt
TmpInst.addOperand(Inst.getOperand(1)); // Rn
@@ -9074,6 +9072,18 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
Inst = TmpInst;
return true;
}
+ case ARM::t2STR_POST_imm: {
+ MCInst TmpInst;
+ TmpInst.setOpcode(ARM::t2STR_POST);
+ TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb
+ TmpInst.addOperand(Inst.getOperand(0)); // Rt
+ TmpInst.addOperand(Inst.getOperand(1)); // Rn
+ TmpInst.addOperand(Inst.getOperand(2)); // imm
+ TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+ TmpInst.addOperand(Inst.getOperand(4));
+ Inst = TmpInst;
+ return true;
+ }
// Aliases for imm syntax of LDRB instructions.
case ARM::t2LDRB_OFFSET_imm: {
MCInst TmpInst;
>From 5d865d4938a0d12c4ed2cf4b1ecdc26855ccf078 Mon Sep 17 00:00:00 2001
From: Kai Luo <luokai at vivo.com>
Date: Tue, 19 Nov 2024 15:13:09 +0800
Subject: [PATCH 2/4] Add test
---
llvm/test/tools/llvm-mca/ARM/m4-strw.s | 35 ++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
create mode 100644 llvm/test/tools/llvm-mca/ARM/m4-strw.s
diff --git a/llvm/test/tools/llvm-mca/ARM/m4-strw.s b/llvm/test/tools/llvm-mca/ARM/m4-strw.s
new file mode 100644
index 000000000000000..11d3fcf9a75778b
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/ARM/m4-strw.s
@@ -0,0 +1,35 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple thumbv7m-none-eabi -mcpu=cortex-m4 < %s | FileCheck %s
+str.w r1, [r0], #16
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 100
+# CHECK-NEXT: Total Cycles: 101
+# CHECK-NEXT: Total uOps: 100
+
+# CHECK: Dispatch Width: 1
+# CHECK-NEXT: uOps Per Cycle: 0.99
+# CHECK-NEXT: IPC: 0.99
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 * str r1, [r0], #16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - M4Unit
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0]
+# CHECK-NEXT: 1.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] Instructions:
+# CHECK-NEXT: 1.00 str r1, [r0], #16
>From 283f4e4557dc8d62745559693b3b2c3503fb83a0 Mon Sep 17 00:00:00 2001
From: Kai Luo <luokai at vivo.com>
Date: Tue, 19 Nov 2024 18:09:12 +0800
Subject: [PATCH 3/4] Fix pre-inc form
---
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 15 +++------------
llvm/test/tools/llvm-mca/ARM/m4-strw.s | 17 ++++++++++-------
2 files changed, 13 insertions(+), 19 deletions(-)
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 99b813473bb9d54..5126d46b88088cc 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -9061,20 +9061,11 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
return true;
}
// Aliases for imm syntax of STR instructions.
- case ARM::t2STR_PRE_imm: {
- MCInst TmpInst;
- TmpInst.setOpcode(ARM::t2STR_PRE);
- TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
- TmpInst.addOperand(Inst.getOperand(0)); // Rt
- TmpInst.addOperand(Inst.getOperand(1)); // Rn
- TmpInst.addOperand(Inst.getOperand(2)); // imm
- TmpInst.addOperand(Inst.getOperand(3)); // CondCode
- Inst = TmpInst;
- return true;
- }
+ case ARM::t2STR_PRE_imm:
case ARM::t2STR_POST_imm: {
MCInst TmpInst;
- TmpInst.setOpcode(ARM::t2STR_POST);
+ TmpInst.setOpcode(Inst.getOpcode() == ARM::t2STR_PRE_imm ? ARM::t2STR_PRE
+ : ARM::t2STR_POST);
TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(0)); // Rt
TmpInst.addOperand(Inst.getOperand(1)); // Rn
diff --git a/llvm/test/tools/llvm-mca/ARM/m4-strw.s b/llvm/test/tools/llvm-mca/ARM/m4-strw.s
index 11d3fcf9a75778b..0bf78aee31ffaee 100644
--- a/llvm/test/tools/llvm-mca/ARM/m4-strw.s
+++ b/llvm/test/tools/llvm-mca/ARM/m4-strw.s
@@ -1,16 +1,17 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple thumbv7m-none-eabi -mcpu=cortex-m4 < %s | FileCheck %s
str.w r1, [r0], #16
+str.w r1, [r0, 16]!
# CHECK: Iterations: 100
-# CHECK-NEXT: Instructions: 100
-# CHECK-NEXT: Total Cycles: 101
-# CHECK-NEXT: Total uOps: 100
+# CHECK-NEXT: Instructions: 200
+# CHECK-NEXT: Total Cycles: 201
+# CHECK-NEXT: Total uOps: 200
# CHECK: Dispatch Width: 1
-# CHECK-NEXT: uOps Per Cycle: 0.99
-# CHECK-NEXT: IPC: 0.99
-# CHECK-NEXT: Block RThroughput: 1.0
+# CHECK-NEXT: uOps Per Cycle: 1.00
+# CHECK-NEXT: IPC: 1.00
+# CHECK-NEXT: Block RThroughput: 2.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -22,14 +23,16 @@ str.w r1, [r0], #16
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 1 1.00 * str r1, [r0], #16
+# CHECK-NEXT: 1 1 1.00 * str r1, [r0, #16]!
# CHECK: Resources:
# CHECK-NEXT: [0] - M4Unit
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0]
-# CHECK-NEXT: 1.00
+# CHECK-NEXT: 2.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] Instructions:
# CHECK-NEXT: 1.00 str r1, [r0], #16
+# CHECK-NEXT: 1.00 str r1, [r0, #16]!
>From f303f2dbde52153493a192d152faf9c5714da814 Mon Sep 17 00:00:00 2001
From: Kai Luo <gluokai at gmail.com>
Date: Tue, 19 Nov 2024 23:49:59 +0800
Subject: [PATCH 4/4] Fix more
---
.../lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 21 +++--
llvm/test/tools/llvm-mca/ARM/m4-ldr-str-w.s | 80 +++++++++++++++++++
llvm/test/tools/llvm-mca/ARM/m4-strw.s | 38 ---------
3 files changed, 94 insertions(+), 45 deletions(-)
create mode 100644 llvm/test/tools/llvm-mca/ARM/m4-ldr-str-w.s
delete mode 100644 llvm/test/tools/llvm-mca/ARM/m4-strw.s
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 5126d46b88088cc..bf62849fba0c3d1 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -9053,10 +9053,11 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
TmpInst.setOpcode(Inst.getOpcode() == ARM::t2LDR_PRE_imm ? ARM::t2LDR_PRE
: ARM::t2LDR_POST);
TmpInst.addOperand(Inst.getOperand(0)); // Rt
- TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
+ TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // imm
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+ TmpInst.addOperand(Inst.getOperand(4));
Inst = TmpInst;
return true;
}
@@ -9093,10 +9094,11 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
? ARM::t2LDRB_PRE
: ARM::t2LDRB_POST);
TmpInst.addOperand(Inst.getOperand(0)); // Rt
- TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
+ TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // imm
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+ TmpInst.addOperand(Inst.getOperand(4));
Inst = TmpInst;
return true;
}
@@ -9117,11 +9119,12 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
TmpInst.setOpcode(Inst.getOpcode() == ARM::t2STRB_PRE_imm
? ARM::t2STRB_PRE
: ARM::t2STRB_POST);
- TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
+ TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(0)); // Rt
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // imm
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+ TmpInst.addOperand(Inst.getOperand(4));
Inst = TmpInst;
return true;
}
@@ -9143,10 +9146,11 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
? ARM::t2LDRH_PRE
: ARM::t2LDRH_POST);
TmpInst.addOperand(Inst.getOperand(0)); // Rt
- TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
+ TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // imm
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+ TmpInst.addOperand(Inst.getOperand(4));
Inst = TmpInst;
return true;
}
@@ -9167,11 +9171,12 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
TmpInst.setOpcode(Inst.getOpcode() == ARM::t2STRH_PRE_imm
? ARM::t2STRH_PRE
: ARM::t2STRH_POST);
- TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
+ TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(0)); // Rt
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // imm
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+ TmpInst.addOperand(Inst.getOperand(4));
Inst = TmpInst;
return true;
}
@@ -9193,10 +9198,11 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
? ARM::t2LDRSB_PRE
: ARM::t2LDRSB_POST);
TmpInst.addOperand(Inst.getOperand(0)); // Rt
- TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
+ TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // imm
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+ TmpInst.addOperand(Inst.getOperand(4));
Inst = TmpInst;
return true;
}
@@ -9218,10 +9224,11 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
? ARM::t2LDRSH_PRE
: ARM::t2LDRSH_POST);
TmpInst.addOperand(Inst.getOperand(0)); // Rt
- TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
+ TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb
TmpInst.addOperand(Inst.getOperand(1)); // Rn
TmpInst.addOperand(Inst.getOperand(2)); // imm
TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+ TmpInst.addOperand(Inst.getOperand(4));
Inst = TmpInst;
return true;
}
diff --git a/llvm/test/tools/llvm-mca/ARM/m4-ldr-str-w.s b/llvm/test/tools/llvm-mca/ARM/m4-ldr-str-w.s
new file mode 100644
index 000000000000000..cb4eeaff4b2a834
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/ARM/m4-ldr-str-w.s
@@ -0,0 +1,80 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple thumbv7m-none-eabi -mcpu=cortex-m4 < %s | FileCheck %s
+str.w r1, [r0], #16
+str.w r1, [r0, 16]!
+strb.w r1, [r0], #16
+strb.w r1, [r0, 16]!
+strh.w r1, [r0], #16
+strh.w r1, [r0, 16]!
+ldr.w r1, [r0], #16
+ldr.w r1, [r0, 16]!
+ldrb.w r1, [r0], #16
+ldrb.w r1, [r0, 16]!
+ldrh.w r1, [r0], #16
+ldrh.w r1, [r0, 16]!
+ldrsb.w r1, [r0], #16
+ldrsb.w r1, [r0, 16]!
+ldrsh.w r1, [r0], #16
+ldrsh.w r1, [r0, 16]!
+
+# CHECK: Iterations: 100
+# CHECK-NEXT: Instructions: 1600
+# CHECK-NEXT: Total Cycles: 2601
+# CHECK-NEXT: Total uOps: 1600
+
+# CHECK: Dispatch Width: 1
+# CHECK-NEXT: uOps Per Cycle: 0.62
+# CHECK-NEXT: IPC: 0.62
+# CHECK-NEXT: Block RThroughput: 16.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 1.00 * str r1, [r0], #16
+# CHECK-NEXT: 1 1 1.00 * str r1, [r0, #16]!
+# CHECK-NEXT: 1 1 1.00 * strb r1, [r0], #16
+# CHECK-NEXT: 1 1 1.00 * strb r1, [r0, #16]!
+# CHECK-NEXT: 1 1 1.00 * strh r1, [r0], #16
+# CHECK-NEXT: 1 1 1.00 * strh r1, [r0, #16]!
+# CHECK-NEXT: 1 2 1.00 * ldr r1, [r0], #16
+# CHECK-NEXT: 1 2 1.00 * ldr r1, [r0, #16]!
+# CHECK-NEXT: 1 2 1.00 * ldrb r1, [r0], #16
+# CHECK-NEXT: 1 2 1.00 * ldrb r1, [r0, #16]!
+# CHECK-NEXT: 1 2 1.00 * ldrh r1, [r0], #16
+# CHECK-NEXT: 1 2 1.00 * ldrh r1, [r0, #16]!
+# CHECK-NEXT: 1 2 1.00 * ldrsb r1, [r0], #16
+# CHECK-NEXT: 1 2 1.00 * ldrsb r1, [r0, #16]!
+# CHECK-NEXT: 1 2 1.00 * ldrsh r1, [r0], #16
+# CHECK-NEXT: 1 2 1.00 * ldrsh r1, [r0, #16]!
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - M4Unit
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0]
+# CHECK-NEXT: 16.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] Instructions:
+# CHECK-NEXT: 1.00 str r1, [r0], #16
+# CHECK-NEXT: 1.00 str r1, [r0, #16]!
+# CHECK-NEXT: 1.00 strb r1, [r0], #16
+# CHECK-NEXT: 1.00 strb r1, [r0, #16]!
+# CHECK-NEXT: 1.00 strh r1, [r0], #16
+# CHECK-NEXT: 1.00 strh r1, [r0, #16]!
+# CHECK-NEXT: 1.00 ldr r1, [r0], #16
+# CHECK-NEXT: 1.00 ldr r1, [r0, #16]!
+# CHECK-NEXT: 1.00 ldrb r1, [r0], #16
+# CHECK-NEXT: 1.00 ldrb r1, [r0, #16]!
+# CHECK-NEXT: 1.00 ldrh r1, [r0], #16
+# CHECK-NEXT: 1.00 ldrh r1, [r0, #16]!
+# CHECK-NEXT: 1.00 ldrsb r1, [r0], #16
+# CHECK-NEXT: 1.00 ldrsb r1, [r0, #16]!
+# CHECK-NEXT: 1.00 ldrsh r1, [r0], #16
+# CHECK-NEXT: 1.00 ldrsh r1, [r0, #16]!
diff --git a/llvm/test/tools/llvm-mca/ARM/m4-strw.s b/llvm/test/tools/llvm-mca/ARM/m4-strw.s
deleted file mode 100644
index 0bf78aee31ffaee..000000000000000
--- a/llvm/test/tools/llvm-mca/ARM/m4-strw.s
+++ /dev/null
@@ -1,38 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple thumbv7m-none-eabi -mcpu=cortex-m4 < %s | FileCheck %s
-str.w r1, [r0], #16
-str.w r1, [r0, 16]!
-
-# CHECK: Iterations: 100
-# CHECK-NEXT: Instructions: 200
-# CHECK-NEXT: Total Cycles: 201
-# CHECK-NEXT: Total uOps: 200
-
-# CHECK: Dispatch Width: 1
-# CHECK-NEXT: uOps Per Cycle: 1.00
-# CHECK-NEXT: IPC: 1.00
-# CHECK-NEXT: Block RThroughput: 2.0
-
-# CHECK: Instruction Info:
-# CHECK-NEXT: [1]: #uOps
-# CHECK-NEXT: [2]: Latency
-# CHECK-NEXT: [3]: RThroughput
-# CHECK-NEXT: [4]: MayLoad
-# CHECK-NEXT: [5]: MayStore
-# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 1.00 * str r1, [r0], #16
-# CHECK-NEXT: 1 1 1.00 * str r1, [r0, #16]!
-
-# CHECK: Resources:
-# CHECK-NEXT: [0] - M4Unit
-
-# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0]
-# CHECK-NEXT: 2.00
-
-# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0] Instructions:
-# CHECK-NEXT: 1.00 str r1, [r0], #16
-# CHECK-NEXT: 1.00 str r1, [r0, #16]!
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