[llvm] abac5be - [InstCombine] Fix APInt ctor assertion
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 19 06:18:08 PST 2024
Author: Nikita Popov
Date: 2024-11-19T15:17:59+01:00
New Revision: abac5be673a2053cceab8ce25009722e45021b9f
URL: https://github.com/llvm/llvm-project/commit/abac5be673a2053cceab8ce25009722e45021b9f
DIFF: https://github.com/llvm/llvm-project/commit/abac5be673a2053cceab8ce25009722e45021b9f.diff
LOG: [InstCombine] Fix APInt ctor assertion
The (extended) bit width might not fit into the (non-extended)
type, resulting in an incorrect truncation of the compared value.
Fix this by using m_SpecificInt(), which is both simpler and
handles this correctly.
Fixes the assertion failure reported in:
https://github.com/llvm/llvm-project/pull/114539#issuecomment-2485799395
Added:
Modified:
llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
llvm/test/Transforms/InstCombine/conditional-variable-length-signext-after-high-bit-extract.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
index a6d6ea573d802d..46ce011c5f7880 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
@@ -1357,14 +1357,10 @@ Instruction *InstCombinerImpl::
// low bits to skip = shift bitwidth - high bits to extract
// The shift amount itself may be extended, and we need to look past zero-ext
// when matching NBits, that will matter for matching later.
- Constant *C;
Value *NBits;
- if (!match(
- LowBitsToSkip,
- m_ZExtOrSelf(m_Sub(m_Constant(C), m_ZExtOrSelf(m_Value(NBits))))) ||
- !match(C, m_SpecificInt_ICMP(ICmpInst::Predicate::ICMP_EQ,
- APInt(C->getType()->getScalarSizeInBits(),
- X->getType()->getScalarSizeInBits()))))
+ if (!match(LowBitsToSkip,
+ m_ZExtOrSelf(m_Sub(m_SpecificInt(XTy->getScalarSizeInBits()),
+ m_ZExtOrSelf(m_Value(NBits))))))
return nullptr;
// Sign-extending value can be zero-extended if we `sub`tract it,
diff --git a/llvm/test/Transforms/InstCombine/conditional-variable-length-signext-after-high-bit-extract.ll b/llvm/test/Transforms/InstCombine/conditional-variable-length-signext-after-high-bit-extract.ll
index 5569af452de4fc..b00b3a289de477 100644
--- a/llvm/test/Transforms/InstCombine/conditional-variable-length-signext-after-high-bit-extract.ll
+++ b/llvm/test/Transforms/InstCombine/conditional-variable-length-signext-after-high-bit-extract.ll
@@ -1137,3 +1137,18 @@ define i32 @n290_or_with_wrong_magic(i32 %data, i32 %nbits) {
%signextended = or i32 %high_bits_extracted, %magic
ret i32 %signextended
}
+
+define i32 @bitwidth_does_not_fit(i3 %arg) {
+; CHECK-LABEL: @bitwidth_does_not_fit(
+; CHECK-NEXT: [[NEG:%.*]] = sub i3 0, [[ARG:%.*]]
+; CHECK-NEXT: [[NEG_EXT:%.*]] = zext i3 [[NEG]] to i32
+; CHECK-NEXT: [[SHR:%.*]] = lshr i32 1, [[NEG_EXT]]
+; CHECK-NEXT: [[INC:%.*]] = add nuw nsw i32 [[SHR]], 1
+; CHECK-NEXT: ret i32 [[INC]]
+;
+ %neg = sub i3 0, %arg
+ %neg.ext = zext i3 %neg to i32
+ %shr = lshr i32 1, %neg.ext
+ %inc = add i32 %shr, 1
+ ret i32 %inc
+}
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