[llvm] [ARM] Stop gluing 1-bit shifts (PR #116547)

[Simon Tatham via llvm-commits]

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@@ -325,7 +325,7 @@ def M7Ex1ReadNoFastBypass : SchedReadAdvance<-1, [WriteLd, M7LoadLatency1]>;
 def : InstRW<[WriteALUsi, M7Ex1ReadNoFastBypass, M7Read_ISS],
              (instregex "t2(ADC|ADDS|ADD|BIC|EOR|ORN|ORR|RSBS|RSB|SBC|SUBS)rs$",
                         "t2(SUB|CMP|CMNz|TEQ|TST)rs$",
-                        "t2MOVsr(a|l)")>;
+                        "t2(A|L)SRs1")>;
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statham-arm wrote:

Tiny nit: should this regex end in `$`, to match the two above it? I don't think you're intentionally matching other opcodes that start with `t2ASRs1` or `t2LSRs1`. (Whereas the previous code _was_ matching things that had extra stuff after `t2MOVsra`/`t2MOVsrl`.

https://github.com/llvm/llvm-project/pull/116547