[llvm] [Thumb2][ARMAsmParser] Fix processing of `t2STR_POST_imm` when changing to its concrete form (PR #116757)

[Kai Luo via llvm-commits]

https://github.com/bzEq created https://github.com/llvm/llvm-project/pull/116757

`t2STR_POST_imm` is pseudo instruction and is expected to be `t2STR_POST`. During building the new MCInst of `t2STR_POST`, the order looks incorrect.

Fixes https://github.com/llvm/llvm-project/issues/97020.

>From fe87ebf34524cc40d8cd59d3da4cd7c862be37a0 Mon Sep 17 00:00:00 2001
From: Kai Luo <luokai at vivo.com>
Date: Tue, 19 Nov 2024 14:51:07 +0800
Subject: [PATCH 1/2] Fix #97020

---
 llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 0dc637fc08aca3..99b813473bb9d5 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -9061,11 +9061,9 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
     return true;
   }
   // Aliases for imm syntax of STR instructions.
-  case ARM::t2STR_PRE_imm:
-  case ARM::t2STR_POST_imm: {
+  case ARM::t2STR_PRE_imm: {
     MCInst TmpInst;
-    TmpInst.setOpcode(Inst.getOpcode() == ARM::t2STR_PRE_imm ? ARM::t2STR_PRE
-                                                             : ARM::t2STR_POST);
+    TmpInst.setOpcode(ARM::t2STR_PRE);
     TmpInst.addOperand(Inst.getOperand(4)); // Rt_wb
     TmpInst.addOperand(Inst.getOperand(0)); // Rt
     TmpInst.addOperand(Inst.getOperand(1)); // Rn
@@ -9074,6 +9072,18 @@ bool ARMAsmParser::processInstruction(MCInst &Inst,
     Inst = TmpInst;
     return true;
   }
+  case ARM::t2STR_POST_imm: {
+    MCInst TmpInst;
+    TmpInst.setOpcode(ARM::t2STR_POST);
+    TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb
+    TmpInst.addOperand(Inst.getOperand(0)); // Rt
+    TmpInst.addOperand(Inst.getOperand(1)); // Rn
+    TmpInst.addOperand(Inst.getOperand(2)); // imm
+    TmpInst.addOperand(Inst.getOperand(3)); // CondCode
+    TmpInst.addOperand(Inst.getOperand(4));
+    Inst = TmpInst;
+    return true;
+  }
   // Aliases for imm syntax of LDRB instructions.
   case ARM::t2LDRB_OFFSET_imm: {
     MCInst TmpInst;

>From 0eb5e201a5e3193817c466bfb86ae5ad8613247f Mon Sep 17 00:00:00 2001
From: Kai Luo <luokai at vivo.com>
Date: Tue, 19 Nov 2024 15:13:09 +0800
Subject: [PATCH 2/2] Add test

---
 llvm/test/tools/llvm-mca/ARM/m4-strw.s | 35 ++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 llvm/test/tools/llvm-mca/ARM/m4-strw.s

diff --git a/llvm/test/tools/llvm-mca/ARM/m4-strw.s b/llvm/test/tools/llvm-mca/ARM/m4-strw.s
new file mode 100644
index 00000000000000..11d3fcf9a75778
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/ARM/m4-strw.s
@@ -0,0 +1,35 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple thumbv7m-none-eabi -mcpu=cortex-m4 < %s | FileCheck %s
+str.w r1, [r0], #16
+
+# CHECK:      Iterations:        100
+# CHECK-NEXT: Instructions:      100
+# CHECK-NEXT: Total Cycles:      101
+# CHECK-NEXT: Total uOps:        100
+
+# CHECK:      Dispatch Width:    1
+# CHECK-NEXT: uOps Per Cycle:    0.99
+# CHECK-NEXT: IPC:               0.99
+# CHECK-NEXT: Block RThroughput: 1.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      1     1.00           *            str	r1, [r0], #16
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - M4Unit
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]
+# CHECK-NEXT: 1.00
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    Instructions:
+# CHECK-NEXT: 1.00   str	r1, [r0], #16