[llvm] 36d47f8 - [AArch64][GlobalISel] Legalize ptr vector freeze and implicit defs.
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 18 14:36:03 PST 2024
Author: David Green
Date: 2024-11-18T22:35:58Z
New Revision: 36d47f88786d29d381545a5f88a7964b47d9a595
URL: https://github.com/llvm/llvm-project/commit/36d47f88786d29d381545a5f88a7964b47d9a595
DIFF: https://github.com/llvm/llvm-project/commit/36d47f88786d29d381545a5f88a7964b47d9a595.diff
LOG: [AArch64][GlobalISel] Legalize ptr vector freeze and implicit defs.
They can be treated the same as other s64 operations.
Added:
Modified:
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
llvm/test/CodeGen/AArch64/freeze.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index baa42302756a56..c8f01068f72189 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -103,7 +103,8 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.clampNumElements(0, v8s8, v16s8)
.clampNumElements(0, v4s16, v8s16)
.clampNumElements(0, v2s32, v4s32)
- .clampNumElements(0, v2s64, v2s64);
+ .clampMaxNumElements(0, s64, 2)
+ .clampMaxNumElements(0, p0, 2);
getActionDefinitionsBuilder(G_PHI)
.legalFor({p0, s16, s32, s64})
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
index 29bd1f8feb5c4d..b0b0e6b322a01e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
@@ -400,10 +400,9 @@ body: |
; CHECK-LABEL: name: test_eve_v4p0
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %vec:_(<4 x p0>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x p0>) = G_IMPLICIT_DEF
; CHECK-NEXT: %idx:_(s64) = G_CONSTANT i64 1
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x p0>), [[UV1:%[0-9]+]]:_(<2 x p0>) = G_UNMERGE_VALUES %vec(<4 x p0>)
- ; CHECK-NEXT: %eve:_(p0) = G_EXTRACT_VECTOR_ELT [[UV]](<2 x p0>), %idx(s64)
+ ; CHECK-NEXT: %eve:_(p0) = G_EXTRACT_VECTOR_ELT [[DEF]](<2 x p0>), %idx(s64)
; CHECK-NEXT: $x0 = COPY %eve(p0)
; CHECK-NEXT: RET_ReallyLR
%vec:_(<4 x p0>) = G_IMPLICIT_DEF
@@ -490,15 +489,14 @@ body: |
; CHECK-LABEL: name: test_eve_v4p0_unknown_idx
; CHECK: liveins: $x0
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: %vec:_(<4 x p0>) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x p0>) = G_IMPLICIT_DEF
; CHECK-NEXT: %idx:_(s64) = COPY $x0
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
- ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x p0>), [[UV1:%[0-9]+]]:_(<2 x p0>) = G_UNMERGE_VALUES %vec(<4 x p0>)
- ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[UV]](<2 x p0>)
+ ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[DEF]](<2 x p0>)
; CHECK-NEXT: G_STORE [[BITCAST]](<2 x s64>), [[FRAME_INDEX]](p0) :: (store (<2 x s64>) into %stack.0, align 32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[FRAME_INDEX]], [[C]](s64)
- ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[UV1]](<2 x p0>)
+ ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[DEF]](<2 x p0>)
; CHECK-NEXT: G_STORE [[BITCAST1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into %stack.0 + 16, basealign 32)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 3
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND %idx, [[C1]]
diff --git a/llvm/test/CodeGen/AArch64/freeze.ll b/llvm/test/CodeGen/AArch64/freeze.ll
index d200b244280639..6efd9f40f00688 100644
--- a/llvm/test/CodeGen/AArch64/freeze.ll
+++ b/llvm/test/CodeGen/AArch64/freeze.ll
@@ -3,8 +3,6 @@
; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel -global-isel-abort=2 2>&1 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
; CHECK-GI: warning: Instruction selection used fallback path for freeze_v2i8
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for freeze_v3p0
-; CHECK-GI-NEXT: warning: Instruction selection used fallback path for freeze_v4p0
%struct.T = type { i32, i32 }
@@ -294,29 +292,47 @@ define <2 x ptr> @freeze_v2p0() {
}
define <3 x ptr> @freeze_v3p0() {
-; CHECK-LABEL: freeze_v3p0:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #4 // =0x4
-; CHECK-NEXT: dup v2.2d, x8
-; CHECK-NEXT: add v0.2d, v0.2d, v2.2d
-; CHECK-NEXT: add d2, d0, d2
-; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: freeze_v3p0:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #4 // =0x4
+; CHECK-SD-NEXT: dup v2.2d, x8
+; CHECK-SD-NEXT: add v0.2d, v0.2d, v2.2d
+; CHECK-SD-NEXT: add d2, d0, d2
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: freeze_v3p0:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI22_0
+; CHECK-GI-NEXT: ldr q0, [x8, :lo12:.LCPI22_0]
+; CHECK-GI-NEXT: add x8, x8, #4
+; CHECK-GI-NEXT: fmov d2, x8
+; CHECK-GI-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: ret
%y1 = freeze <3 x ptr> undef
%t1 = getelementptr i32, <3 x ptr> %y1, i32 1
ret <3 x ptr> %t1
}
define <4 x ptr> @freeze_v4p0() {
-; CHECK-LABEL: freeze_v4p0:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #4 // =0x4
-; CHECK-NEXT: dup v0.2d, x8
-; CHECK-NEXT: add v0.2d, v0.2d, v0.2d
-; CHECK-NEXT: mov v1.16b, v0.16b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: freeze_v4p0:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #4 // =0x4
+; CHECK-SD-NEXT: dup v0.2d, x8
+; CHECK-SD-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-SD-NEXT: mov v1.16b, v0.16b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: freeze_v4p0:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI23_0
+; CHECK-GI-NEXT: ldr q0, [x8, :lo12:.LCPI23_0]
+; CHECK-GI-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-GI-NEXT: mov v1.16b, v0.16b
+; CHECK-GI-NEXT: ret
%y1 = freeze <4 x ptr> undef
%t1 = getelementptr i32, <4 x ptr> %y1, i32 1
ret <4 x ptr> %t1
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