[llvm] 50209e9 - [AArch64][GlobalISel] Move and update freeze.ll test. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 18 14:31:18 PST 2024
Author: David Green
Date: 2024-11-18T22:31:13Z
New Revision: 50209e994200c98236a27b54e87e8c598d160402
URL: https://github.com/llvm/llvm-project/commit/50209e994200c98236a27b54e87e8c598d160402
DIFF: https://github.com/llvm/llvm-project/commit/50209e994200c98236a27b54e87e8c598d160402.diff
LOG: [AArch64][GlobalISel] Move and update freeze.ll test. NFC
This adds a number of extra vector cases, notably the ptr vectors.
Added:
llvm/test/CodeGen/AArch64/freeze.ll
Modified:
llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
Removed:
llvm/test/CodeGen/AArch64/GlobalISel/freeze.ll
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/freeze.ll b/llvm/test/CodeGen/AArch64/GlobalISel/freeze.ll
deleted file mode 100644
index a793ecbf03f656..00000000000000
--- a/llvm/test/CodeGen/AArch64/GlobalISel/freeze.ll
+++ /dev/null
@@ -1,149 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s 2>&1 | FileCheck %s
-; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel -global-isel-abort=1 < %s 2>&1 | FileCheck %s --check-prefix=GISEL
-
-%struct.T = type { i32, i32 }
-
-define i32 @freeze_int() {
-; CHECK-LABEL: freeze_int:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mul w0, w8, w8
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: freeze_int:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mul w0, w8, w8
-; GISEL-NEXT: ret
- %y1 = freeze i32 undef
- %t1 = mul i32 %y1, %y1
- ret i32 %t1
-}
-
-define i5 @freeze_int2() {
-; CHECK-LABEL: freeze_int2:
-; CHECK: // %bb.0:
-; CHECK-NEXT: mul w0, w8, w8
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: freeze_int2:
-; GISEL: // %bb.0:
-; GISEL-NEXT: mul w0, w8, w8
-; GISEL-NEXT: ret
- %y1 = freeze i5 undef
- %t1 = mul i5 %y1, %y1
- ret i5 %t1
-}
-
-define float @freeze_float() {
-; CHECK-LABEL: freeze_float:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fadd s0, s0, s0
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: freeze_float:
-; GISEL: // %bb.0:
-; GISEL-NEXT: fadd s0, s0, s0
-; GISEL-NEXT: ret
- %y1 = freeze float undef
- %t1 = fadd float %y1, %y1
- ret float %t1
-}
-
-define <2 x i32> @freeze_ivec() {
-; CHECK-LABEL: freeze_ivec:
-; CHECK: // %bb.0:
-; CHECK-NEXT: add v0.2s, v0.2s, v0.2s
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: freeze_ivec:
-; GISEL: // %bb.0:
-; GISEL-NEXT: add v0.2s, v0.2s, v0.2s
-; GISEL-NEXT: ret
- %y1 = freeze <2 x i32> undef
- %t1 = add <2 x i32> %y1, %y1
- ret <2 x i32> %t1
-}
-
-define ptr @freeze_ptr() {
-; CHECK-LABEL: freeze_ptr:
-; CHECK: // %bb.0:
-; CHECK-NEXT: add x0, x8, #4
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: freeze_ptr:
-; GISEL: // %bb.0:
-; GISEL-NEXT: add x0, x8, #4
-; GISEL-NEXT: ret
- %y1 = freeze ptr undef
- %t1 = getelementptr i8, ptr %y1, i64 4
- ret ptr %t1
-}
-
-define i32 @freeze_struct() {
-; CHECK-LABEL: freeze_struct:
-; CHECK: // %bb.0:
-; CHECK-NEXT: add w0, w8, w8
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: freeze_struct:
-; GISEL: // %bb.0:
-; GISEL-NEXT: add w0, w8, w8
-; GISEL-NEXT: ret
- %y1 = freeze %struct.T undef
- %v1 = extractvalue %struct.T %y1, 0
- %v2 = extractvalue %struct.T %y1, 1
- %t1 = add i32 %v1, %v2
- ret i32 %t1
-}
-
-define i32 @freeze_anonstruct() {
-; CHECK-LABEL: freeze_anonstruct:
-; CHECK: // %bb.0:
-; CHECK-NEXT: add w0, w8, w8
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: freeze_anonstruct:
-; GISEL: // %bb.0:
-; GISEL-NEXT: add w0, w8, w8
-; GISEL-NEXT: ret
- %y1 = freeze {i32, i32} undef
- %v1 = extractvalue {i32, i32} %y1, 0
- %v2 = extractvalue {i32, i32} %y1, 1
- %t1 = add i32 %v1, %v2
- ret i32 %t1
-}
-
-define i32 @freeze_anonstruct2() {
-; CHECK-LABEL: freeze_anonstruct2:
-; CHECK: // %bb.0:
-; CHECK-NEXT: add w0, w8, w8, uxth
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: freeze_anonstruct2:
-; GISEL: // %bb.0:
-; GISEL-NEXT: add w0, w8, w8, uxth
-; GISEL-NEXT: ret
- %y1 = freeze {i32, i16} undef
- %v1 = extractvalue {i32, i16} %y1, 0
- %v2 = extractvalue {i32, i16} %y1, 1
- %z2 = zext i16 %v2 to i32
- %t1 = add i32 %v1, %z2
- ret i32 %t1
-}
-
-define i64 @freeze_array() {
-; CHECK-LABEL: freeze_array:
-; CHECK: // %bb.0:
-; CHECK-NEXT: add x0, x8, x8
-; CHECK-NEXT: ret
-;
-; GISEL-LABEL: freeze_array:
-; GISEL: // %bb.0:
-; GISEL-NEXT: add x0, x8, x8
-; GISEL-NEXT: ret
- %y1 = freeze [2 x i64] undef
- %v1 = extractvalue [2 x i64] %y1, 0
- %v2 = extractvalue [2 x i64] %y1, 1
- %t1 = add i64 %v1, %v2
- ret i64 %t1
-}
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
index 323a3993473fcb..29bd1f8feb5c4d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
@@ -7,7 +7,9 @@ body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: test_eve_1
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; CHECK: liveins: $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[C]](s64)
; CHECK-NEXT: $x0 = COPY [[EVEC]](s64)
@@ -24,7 +26,9 @@ body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: test_eve_v2s1
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; CHECK: liveins: $q0, $q1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(eq), [[COPY]](<2 x s64>), [[COPY1]]
@@ -46,7 +50,9 @@ body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: test_eve_v4s1
- ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+ ; CHECK: liveins: $q0, $q1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY]](<4 x s32>), [[COPY1]]
@@ -69,7 +75,9 @@ body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: test_eve_v8s1
- ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+ ; CHECK: liveins: $q0, $q1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(eq), [[COPY]](<8 x s16>), [[COPY1]]
@@ -92,7 +100,9 @@ body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: test_eve_v16s1
- ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+ ; CHECK: liveins: $q0, $q1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]]
@@ -115,7 +125,9 @@ body: |
bb.0:
liveins: $q0, $q1
; CHECK-LABEL: name: test_eve_v2p0
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $q0
+ ; CHECK: liveins: $q0, $q1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(p0) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x p0>), [[C]](s64)
; CHECK-NEXT: $x0 = COPY [[EVEC]](p0)
@@ -132,7 +144,9 @@ body: |
bb.0:
liveins: $q0, $q1, $x0
; CHECK-LABEL: name: test_eve_v4s64
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; CHECK: liveins: $q0, $q1, $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s64) = G_EXTRACT_VECTOR_ELT [[COPY]](<2 x s64>), [[C]](s64)
; CHECK-NEXT: $x0 = COPY [[EVEC]](s64)
@@ -152,7 +166,9 @@ body: |
bb.0:
liveins: $q0, $q1, $x0
; CHECK-LABEL: name: test_eve_v2s1_unknown_idx
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; CHECK: liveins: $q0, $q1, $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(eq), [[COPY]](<2 x s64>), [[COPY1]]
@@ -181,7 +197,9 @@ body: |
bb.0:
liveins: $q0, $q1, $x0
; CHECK-LABEL: name: test_eve_v4s1_unknown_idx
- ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+ ; CHECK: liveins: $q0, $q1, $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY]](<4 x s32>), [[COPY1]]
@@ -211,7 +229,9 @@ body: |
bb.0:
liveins: $q0, $q1, $x0
; CHECK-LABEL: name: test_eve_v8s1_unknown_idx
- ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+ ; CHECK: liveins: $q0, $q1, $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(eq), [[COPY]](<8 x s16>), [[COPY1]]
@@ -241,7 +261,9 @@ body: |
bb.0:
liveins: $q0, $q1, $x0
; CHECK-LABEL: name: test_eve_v16s1_unknown_idx
- ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+ ; CHECK: liveins: $q0, $q1, $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]]
@@ -271,7 +293,9 @@ body: |
bb.0:
liveins: $q0, $q1, $x0
; CHECK-LABEL: name: test_eve_v2p0_unknown_idx
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $q0
+ ; CHECK: liveins: $q0, $q1, $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<2 x s64>) = G_BITCAST [[COPY]](<2 x p0>)
@@ -296,7 +320,9 @@ body: |
bb.0:
liveins: $q0, $q1, $x0
; CHECK-LABEL: name: test_eve_v4s64_unknown_idx
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; CHECK: liveins: $q0, $q1, $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
; CHECK-NEXT: %idx:_(s64) = COPY $x0
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
@@ -326,7 +352,9 @@ body: |
bb.0:
liveins: $q0, $q1, $x0
; CHECK-LABEL: name: test_eve_v8s32
- ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+ ; CHECK: liveins: $q0, $q1, $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[COPY]](<4 x s32>), [[C]](s64)
; CHECK-NEXT: $w0 = COPY [[EVEC]](s32)
@@ -346,7 +374,9 @@ body: |
bb.0:
liveins: $q0, $q1, $x0
; CHECK-LABEL: name: test_eve_v16s16
- ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q1
+ ; CHECK: liveins: $q0, $q1, $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s16) = G_EXTRACT_VECTOR_ELT [[COPY]](<8 x s16>), [[C]](s64)
; CHECK-NEXT: %ext:_(s32) = G_ANYEXT [[EVEC]](s16)
@@ -368,7 +398,9 @@ body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: test_eve_v4p0
- ; CHECK: %vec:_(<4 x p0>) = G_IMPLICIT_DEF
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %vec:_(<4 x p0>) = G_IMPLICIT_DEF
; CHECK-NEXT: %idx:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x p0>), [[UV1:%[0-9]+]]:_(<2 x p0>) = G_UNMERGE_VALUES %vec(<4 x p0>)
; CHECK-NEXT: %eve:_(p0) = G_EXTRACT_VECTOR_ELT [[UV]](<2 x p0>), %idx(s64)
@@ -386,7 +418,9 @@ body: |
bb.0:
liveins: $q0, $q1, $w0
; CHECK-LABEL: name: test_eve_v8s32_unknown_idx
- ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+ ; CHECK: liveins: $q0, $q1, $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
; CHECK-NEXT: %idx:_(s32) = COPY $w0
; CHECK-NEXT: %idxprom:_(s64) = G_SEXT %idx(s32)
@@ -418,7 +452,9 @@ body: |
bb.0:
liveins: $q0, $q1, $w0
; CHECK-LABEL: name: test_eve_v16s16_unknown_idx
- ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+ ; CHECK: liveins: $q0, $q1, $w0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
; CHECK-NEXT: %idx:_(s32) = COPY $w0
; CHECK-NEXT: %idxprom:_(s64) = G_SEXT %idx(s32)
@@ -452,7 +488,9 @@ body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: test_eve_v4p0_unknown_idx
- ; CHECK: %vec:_(<4 x p0>) = G_IMPLICIT_DEF
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %vec:_(<4 x p0>) = G_IMPLICIT_DEF
; CHECK-NEXT: %idx:_(s64) = COPY $x0
; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %stack.0
; CHECK-NEXT: [[UV:%[0-9]+]]:_(<2 x p0>), [[UV1:%[0-9]+]]:_(<2 x p0>) = G_UNMERGE_VALUES %vec(<4 x p0>)
@@ -477,15 +515,17 @@ body: |
RET_ReallyLR
...
---
+# Make sure that the pointer legalization rules don't apply when we have
+#
diff erent address spaces.
name: cant_legalize_
diff erent_address_spaces
body: |
bb.0:
liveins: $x0
- ; Make sure that the pointer legalization rules don't apply when we have
- ;
diff erent address spaces.
; CHECK-LABEL: name: cant_legalize_
diff erent_address_spaces
- ; CHECK: %vec:_(<4 x p1>) = G_IMPLICIT_DEF
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: %vec:_(<4 x p1>) = G_IMPLICIT_DEF
; CHECK-NEXT: %idx:_(s64) = G_CONSTANT i64 1
; CHECK-NEXT: %eve:_(p0) = G_EXTRACT_VECTOR_ELT %vec(<4 x p1>), %idx(s64)
; CHECK-NEXT: $x0 = COPY %eve(p0)
diff --git a/llvm/test/CodeGen/AArch64/freeze.ll b/llvm/test/CodeGen/AArch64/freeze.ll
new file mode 100644
index 00000000000000..d200b244280639
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/freeze.ll
@@ -0,0 +1,382 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=aarch64-unknown-linux-gnu -global-isel -global-isel-abort=2 2>&1 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI: warning: Instruction selection used fallback path for freeze_v2i8
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for freeze_v3p0
+; CHECK-GI-NEXT: warning: Instruction selection used fallback path for freeze_v4p0
+
+%struct.T = type { i32, i32 }
+
+define i32 @freeze_int() {
+; CHECK-LABEL: freeze_int:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w0, w8, w8
+; CHECK-NEXT: ret
+ %y1 = freeze i32 undef
+ %t1 = mul i32 %y1, %y1
+ ret i32 %t1
+}
+
+define i5 @freeze_int2() {
+; CHECK-LABEL: freeze_int2:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mul w0, w8, w8
+; CHECK-NEXT: ret
+ %y1 = freeze i5 undef
+ %t1 = mul i5 %y1, %y1
+ ret i5 %t1
+}
+
+define float @freeze_float() {
+; CHECK-LABEL: freeze_float:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fadd s0, s0, s0
+; CHECK-NEXT: ret
+ %y1 = freeze float undef
+ %t1 = fadd float %y1, %y1
+ ret float %t1
+}
+
+define <2 x i8> @freeze_v2i8() {
+; CHECK-LABEL: freeze_v2i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: add v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: ret
+ %y1 = freeze <2 x i8> undef
+ %t1 = add <2 x i8> %y1, %y1
+ ret <2 x i8> %t1
+}
+
+define <3 x i8> @freeze_v3i8() {
+; CHECK-SD-LABEL: freeze_v3i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: umov w0, v0.h[0]
+; CHECK-SD-NEXT: umov w1, v0.h[1]
+; CHECK-SD-NEXT: umov w2, v0.h[2]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: freeze_v3i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov b0, v0.b[1]
+; CHECK-GI-NEXT: mov b1, v0.b[2]
+; CHECK-GI-NEXT: fmov w8, s0
+; CHECK-GI-NEXT: mov v0.h[1], w8
+; CHECK-GI-NEXT: fmov w8, s1
+; CHECK-GI-NEXT: mov v0.h[2], w8
+; CHECK-GI-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-GI-NEXT: umov w0, v0.h[0]
+; CHECK-GI-NEXT: umov w1, v0.h[1]
+; CHECK-GI-NEXT: umov w2, v0.h[2]
+; CHECK-GI-NEXT: ret
+ %y1 = freeze <3 x i8> undef
+ %t1 = add <3 x i8> %y1, %y1
+ ret <3 x i8> %t1
+}
+
+define <4 x i8> @freeze_v4i8() {
+; CHECK-SD-LABEL: freeze_v4i8:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: freeze_v4i8:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov b0, v0.b[1]
+; CHECK-GI-NEXT: fmov w8, s0
+; CHECK-GI-NEXT: mov b1, v0.b[2]
+; CHECK-GI-NEXT: mov v0.h[1], w8
+; CHECK-GI-NEXT: fmov w8, s1
+; CHECK-GI-NEXT: mov b2, v0.b[3]
+; CHECK-GI-NEXT: mov v0.h[2], w8
+; CHECK-GI-NEXT: fmov w8, s2
+; CHECK-GI-NEXT: mov v0.h[3], w8
+; CHECK-GI-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-GI-NEXT: ret
+ %y1 = freeze <4 x i8> undef
+ %t1 = add <4 x i8> %y1, %y1
+ ret <4 x i8> %t1
+}
+
+define <8 x i8> @freeze_v8i8() {
+; CHECK-LABEL: freeze_v8i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: add v0.8b, v0.8b, v0.8b
+; CHECK-NEXT: ret
+ %y1 = freeze <8 x i8> undef
+ %t1 = add <8 x i8> %y1, %y1
+ ret <8 x i8> %t1
+}
+
+define <16 x i8> @freeze_v16i8() {
+; CHECK-LABEL: freeze_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: add v0.16b, v0.16b, v0.16b
+; CHECK-NEXT: ret
+ %y1 = freeze <16 x i8> undef
+ %t1 = add <16 x i8> %y1, %y1
+ ret <16 x i8> %t1
+}
+
+define <32 x i8> @freeze_v32i8() {
+; CHECK-LABEL: freeze_v32i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: add v0.16b, v0.16b, v0.16b
+; CHECK-NEXT: mov v1.16b, v0.16b
+; CHECK-NEXT: ret
+ %y1 = freeze <32 x i8> undef
+ %t1 = add <32 x i8> %y1, %y1
+ ret <32 x i8> %t1
+}
+
+define <2 x i16> @freeze_v2i16() {
+; CHECK-SD-LABEL: freeze_v2i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: add v0.2s, v0.2s, v0.2s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: freeze_v2i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: mov h0, v0.h[1]
+; CHECK-GI-NEXT: mov v1.s[0], w8
+; CHECK-GI-NEXT: fmov w8, s0
+; CHECK-GI-NEXT: mov v1.s[1], w8
+; CHECK-GI-NEXT: add v0.2s, v1.2s, v1.2s
+; CHECK-GI-NEXT: ret
+ %y1 = freeze <2 x i16> undef
+ %t1 = add <2 x i16> %y1, %y1
+ ret <2 x i16> %t1
+}
+
+define <3 x i16> @freeze_v3i16() {
+; CHECK-LABEL: freeze_v3i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: ret
+ %y1 = freeze <3 x i16> undef
+ %t1 = add <3 x i16> %y1, %y1
+ ret <3 x i16> %t1
+}
+
+define <4 x i16> @freeze_v4i16() {
+; CHECK-LABEL: freeze_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: add v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: ret
+ %y1 = freeze <4 x i16> undef
+ %t1 = add <4 x i16> %y1, %y1
+ ret <4 x i16> %t1
+}
+
+define <8 x i16> @freeze_v8i16() {
+; CHECK-LABEL: freeze_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: add v0.8h, v0.8h, v0.8h
+; CHECK-NEXT: ret
+ %y1 = freeze <8 x i16> undef
+ %t1 = add <8 x i16> %y1, %y1
+ ret <8 x i16> %t1
+}
+
+define <16 x i16> @freeze_v16i16() {
+; CHECK-LABEL: freeze_v16i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: add v0.8h, v0.8h, v0.8h
+; CHECK-NEXT: mov v1.16b, v0.16b
+; CHECK-NEXT: ret
+ %y1 = freeze <16 x i16> undef
+ %t1 = add <16 x i16> %y1, %y1
+ ret <16 x i16> %t1
+}
+
+define <2 x i32> @freeze_v2i32() {
+; CHECK-LABEL: freeze_v2i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: add v0.2s, v0.2s, v0.2s
+; CHECK-NEXT: ret
+ %y1 = freeze <2 x i32> undef
+ %t1 = add <2 x i32> %y1, %y1
+ ret <2 x i32> %t1
+}
+
+define <3 x i32> @freeze_v3i32() {
+; CHECK-LABEL: freeze_v3i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: add v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: ret
+ %y1 = freeze <3 x i32> undef
+ %t1 = add <3 x i32> %y1, %y1
+ ret <3 x i32> %t1
+}
+
+define <4 x i32> @freeze_v4i32() {
+; CHECK-LABEL: freeze_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: add v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: ret
+ %y1 = freeze <4 x i32> undef
+ %t1 = add <4 x i32> %y1, %y1
+ ret <4 x i32> %t1
+}
+
+define <8 x i32> @freeze_v8i32() {
+; CHECK-LABEL: freeze_v8i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: add v0.4s, v0.4s, v0.4s
+; CHECK-NEXT: mov v1.16b, v0.16b
+; CHECK-NEXT: ret
+ %y1 = freeze <8 x i32> undef
+ %t1 = add <8 x i32> %y1, %y1
+ ret <8 x i32> %t1
+}
+
+define <2 x i64> @freeze_v2i64() {
+; CHECK-LABEL: freeze_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: ret
+ %y1 = freeze <2 x i64> undef
+ %t1 = add <2 x i64> %y1, %y1
+ ret <2 x i64> %t1
+}
+
+define <3 x i64> @freeze_v3i64() {
+; CHECK-SD-LABEL: freeze_v3i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-SD-NEXT: fmov d2, d0
+; CHECK-SD-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-SD-NEXT: // kill: def $d1 killed $d1 killed $q1
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: freeze_v3i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-GI-NEXT: add x8, x8, x8
+; CHECK-GI-NEXT: fmov d2, x8
+; CHECK-GI-NEXT: mov d1, v0.d[1]
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
+ %y1 = freeze <3 x i64> undef
+ %t1 = add <3 x i64> %y1, %y1
+ ret <3 x i64> %t1
+}
+
+define <4 x i64> @freeze_v4i64() {
+; CHECK-LABEL: freeze_v4i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: mov v1.16b, v0.16b
+; CHECK-NEXT: ret
+ %y1 = freeze <4 x i64> undef
+ %t1 = add <4 x i64> %y1, %y1
+ ret <4 x i64> %t1
+}
+
+define <2 x ptr> @freeze_v2p0() {
+; CHECK-SD-LABEL: freeze_v2p0:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: mov w8, #4 // =0x4
+; CHECK-SD-NEXT: dup v0.2d, x8
+; CHECK-SD-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: freeze_v2p0:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: adrp x8, .LCPI21_0
+; CHECK-GI-NEXT: ldr q0, [x8, :lo12:.LCPI21_0]
+; CHECK-GI-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-GI-NEXT: ret
+ %y1 = freeze <2 x ptr> undef
+ %t1 = getelementptr i32, <2 x ptr> %y1, i32 1
+ ret <2 x ptr> %t1
+}
+
+define <3 x ptr> @freeze_v3p0() {
+; CHECK-LABEL: freeze_v3p0:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #4 // =0x4
+; CHECK-NEXT: dup v2.2d, x8
+; CHECK-NEXT: add v0.2d, v0.2d, v2.2d
+; CHECK-NEXT: add d2, d0, d2
+; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-NEXT: // kill: def $d1 killed $d1 killed $q1
+; CHECK-NEXT: ret
+ %y1 = freeze <3 x ptr> undef
+ %t1 = getelementptr i32, <3 x ptr> %y1, i32 1
+ ret <3 x ptr> %t1
+}
+
+define <4 x ptr> @freeze_v4p0() {
+; CHECK-LABEL: freeze_v4p0:
+; CHECK: // %bb.0:
+; CHECK-NEXT: mov w8, #4 // =0x4
+; CHECK-NEXT: dup v0.2d, x8
+; CHECK-NEXT: add v0.2d, v0.2d, v0.2d
+; CHECK-NEXT: mov v1.16b, v0.16b
+; CHECK-NEXT: ret
+ %y1 = freeze <4 x ptr> undef
+ %t1 = getelementptr i32, <4 x ptr> %y1, i32 1
+ ret <4 x ptr> %t1
+}
+
+define ptr @freeze_ptr() {
+; CHECK-LABEL: freeze_ptr:
+; CHECK: // %bb.0:
+; CHECK-NEXT: add x0, x8, #4
+; CHECK-NEXT: ret
+ %y1 = freeze ptr undef
+ %t1 = getelementptr i8, ptr %y1, i64 4
+ ret ptr %t1
+}
+
+define i32 @freeze_struct() {
+; CHECK-LABEL: freeze_struct:
+; CHECK: // %bb.0:
+; CHECK-NEXT: add w0, w8, w8
+; CHECK-NEXT: ret
+ %y1 = freeze %struct.T undef
+ %v1 = extractvalue %struct.T %y1, 0
+ %v2 = extractvalue %struct.T %y1, 1
+ %t1 = add i32 %v1, %v2
+ ret i32 %t1
+}
+
+define i32 @freeze_anonstruct() {
+; CHECK-LABEL: freeze_anonstruct:
+; CHECK: // %bb.0:
+; CHECK-NEXT: add w0, w8, w8
+; CHECK-NEXT: ret
+ %y1 = freeze {i32, i32} undef
+ %v1 = extractvalue {i32, i32} %y1, 0
+ %v2 = extractvalue {i32, i32} %y1, 1
+ %t1 = add i32 %v1, %v2
+ ret i32 %t1
+}
+
+define i32 @freeze_anonstruct2() {
+; CHECK-LABEL: freeze_anonstruct2:
+; CHECK: // %bb.0:
+; CHECK-NEXT: add w0, w8, w8, uxth
+; CHECK-NEXT: ret
+ %y1 = freeze {i32, i16} undef
+ %v1 = extractvalue {i32, i16} %y1, 0
+ %v2 = extractvalue {i32, i16} %y1, 1
+ %z2 = zext i16 %v2 to i32
+ %t1 = add i32 %v1, %z2
+ ret i32 %t1
+}
+
+define i64 @freeze_array() {
+; CHECK-LABEL: freeze_array:
+; CHECK: // %bb.0:
+; CHECK-NEXT: add x0, x8, x8
+; CHECK-NEXT: ret
+ %y1 = freeze [2 x i64] undef
+ %v1 = extractvalue [2 x i64] %y1, 0
+ %v2 = extractvalue [2 x i64] %y1, 1
+ %t1 = add i64 %v1, %v2
+ ret i64 %t1
+}
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