[llvm] ac17b50 - [RISCV] Use getSignedTargetConstant. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 18 12:33:10 PST 2024
Author: Craig Topper
Date: 2024-11-18T12:20:44-08:00
New Revision: ac17b50f50bad5c1cc306e1813322ed2ae6e1ef0
URL: https://github.com/llvm/llvm-project/commit/ac17b50f50bad5c1cc306e1813322ed2ae6e1ef0
DIFF: https://github.com/llvm/llvm-project/commit/ac17b50f50bad5c1cc306e1813322ed2ae6e1ef0.diff
LOG: [RISCV] Use getSignedTargetConstant. NFC
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 034314c88f79f0..ca368a18c80d64 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -176,8 +176,7 @@ static SDValue selectImmSeq(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT,
RISCVMatInt::InstSeq &Seq) {
SDValue SrcReg = CurDAG->getRegister(RISCV::X0, VT);
for (const RISCVMatInt::Inst &Inst : Seq) {
- SDValue SDImm =
- CurDAG->getSignedConstant(Inst.getImm(), DL, VT, /*isTarget=*/true);
+ SDValue SDImm = CurDAG->getSignedTargetConstant(Inst.getImm(), DL, VT);
SDNode *Result = nullptr;
switch (Inst.getOpndKind()) {
case RISCVMatInt::Imm:
@@ -208,10 +207,10 @@ static SDValue selectImm(SelectionDAG *CurDAG, const SDLoc &DL, const MVT VT,
// Use a rematerializable pseudo instruction for short sequences if enabled.
if (Seq.size() == 2 && UsePseudoMovImm)
- return SDValue(CurDAG->getMachineNode(RISCV::PseudoMovImm, DL, VT,
- CurDAG->getSignedConstant(
- Imm, DL, VT, /*isTarget=*/true)),
- 0);
+ return SDValue(
+ CurDAG->getMachineNode(RISCV::PseudoMovImm, DL, VT,
+ CurDAG->getSignedTargetConstant(Imm, DL, VT)),
+ 0);
// See if we can create this constant as (ADD (SLLI X, C), X) where X is at
// worst an LUI+ADDIW. This will require an extra register, but avoids a
@@ -594,7 +593,7 @@ bool RISCVDAGToDAGISel::tryShrinkShlLogicImm(SDNode *Node) {
SDNode *BinOp = CurDAG->getMachineNode(
BinOpc, DL, VT, Shift.getOperand(0),
- CurDAG->getSignedConstant(ShiftedVal, DL, VT, /*isTarget=*/true));
+ CurDAG->getSignedTargetConstant(ShiftedVal, DL, VT));
SDNode *SLLI =
CurDAG->getMachineNode(ShOpc, DL, VT, SDValue(BinOp, 0),
CurDAG->getTargetConstant(ShAmt, DL, VT));
@@ -723,11 +722,10 @@ bool RISCVDAGToDAGISel::tryIndexedLoad(SDNode *Node) {
return false;
EVT Ty = Ld->getOffset().getValueType();
- SDValue Ops[] = {Ld->getBasePtr(),
- CurDAG->getSignedConstant(Offset >> Shift, SDLoc(Node), Ty,
- /*isTarget=*/true),
- CurDAG->getTargetConstant(Shift, SDLoc(Node), Ty),
- Ld->getChain()};
+ SDValue Ops[] = {
+ Ld->getBasePtr(),
+ CurDAG->getSignedTargetConstant(Offset >> Shift, SDLoc(Node), Ty),
+ CurDAG->getTargetConstant(Shift, SDLoc(Node), Ty), Ld->getChain()};
SDNode *New = CurDAG->getMachineNode(Opcode, SDLoc(Node), Ld->getValueType(0),
Ld->getValueType(1), MVT::Other, Ops);
@@ -2515,8 +2513,8 @@ bool RISCVDAGToDAGISel::SelectFrameAddrRegImm(SDValue Addr, SDValue &Base,
if (isInt<12>(CVal)) {
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(),
Subtarget->getXLenVT());
- Offset = CurDAG->getSignedConstant(
- CVal, SDLoc(Addr), Subtarget->getXLenVT(), /*isTarget=*/true);
+ Offset = CurDAG->getSignedTargetConstant(CVal, SDLoc(Addr),
+ Subtarget->getXLenVT());
return true;
}
}
@@ -2555,7 +2553,7 @@ static bool selectConstantAddr(SelectionDAG *CurDAG, const SDLoc &DL,
} else {
Base = CurDAG->getRegister(RISCV::X0, VT);
}
- Offset = CurDAG->getSignedConstant(Lo12, DL, VT, /*isTarget=*/true);
+ Offset = CurDAG->getSignedTargetConstant(Lo12, DL, VT);
return true;
}
@@ -2577,7 +2575,7 @@ static bool selectConstantAddr(SelectionDAG *CurDAG, const SDLoc &DL,
assert(!Seq.empty() && "Expected more instructions in sequence");
Base = selectImmSeq(CurDAG, DL, VT, Seq);
- Offset = CurDAG->getSignedConstant(Lo12, DL, VT, /*isTarget=*/true);
+ Offset = CurDAG->getSignedTargetConstant(Lo12, DL, VT);
return true;
}
@@ -2727,7 +2725,7 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
if (auto *FIN = dyn_cast<FrameIndexSDNode>(Base))
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), VT);
- Offset = CurDAG->getSignedConstant(CVal, DL, VT, /*isTarget=*/true);
+ Offset = CurDAG->getSignedTargetConstant(CVal, DL, VT);
return true;
}
}
@@ -2744,11 +2742,10 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
if (CVal >= -4096 && CVal <= (4094 - RV32ZdinxRange)) {
int64_t Adj = CVal < 0 ? -2048 : 2047;
Base = SDValue(
- CurDAG->getMachineNode(
- RISCV::ADDI, DL, VT, Addr.getOperand(0),
- CurDAG->getSignedConstant(Adj, DL, VT, /*isTarget=*/true)),
+ CurDAG->getMachineNode(RISCV::ADDI, DL, VT, Addr.getOperand(0),
+ CurDAG->getSignedTargetConstant(Adj, DL, VT)),
0);
- Offset = CurDAG->getSignedConstant(CVal - Adj, DL, VT, /*isTarget=*/true);
+ Offset = CurDAG->getSignedTargetConstant(CVal - Adj, DL, VT);
return true;
}
@@ -2802,7 +2799,7 @@ bool RISCVDAGToDAGISel::SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base,
if (auto *FIN = dyn_cast<FrameIndexSDNode>(Base))
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), VT);
- Offset = CurDAG->getSignedConstant(CVal, DL, VT, /*isTarget=*/true);
+ Offset = CurDAG->getSignedTargetConstant(CVal, DL, VT);
return true;
}
}
@@ -2818,12 +2815,12 @@ bool RISCVDAGToDAGISel::SelectAddrRegImmLsb00000(SDValue Addr, SDValue &Base,
if ((-2049 >= CVal && CVal >= -4096) || (4065 >= CVal && CVal >= 2017)) {
int64_t Adj = CVal < 0 ? -2048 : 2016;
int64_t AdjustedOffset = CVal - Adj;
- Base = SDValue(CurDAG->getMachineNode(
- RISCV::ADDI, DL, VT, Addr.getOperand(0),
- CurDAG->getSignedConstant(AdjustedOffset, DL, VT,
- /*isTarget=*/true)),
- 0);
- Offset = CurDAG->getSignedConstant(Adj, DL, VT, /*isTarget=*/true);
+ Base =
+ SDValue(CurDAG->getMachineNode(
+ RISCV::ADDI, DL, VT, Addr.getOperand(0),
+ CurDAG->getSignedTargetConstant(AdjustedOffset, DL, VT)),
+ 0);
+ Offset = CurDAG->getSignedTargetConstant(Adj, DL, VT);
return true;
}
@@ -2969,21 +2966,21 @@ bool RISCVDAGToDAGISel::selectSETCC(SDValue N, ISD::CondCode ExpectedCCVal,
// If the RHS is -2048, we can use xori to produce 0 if the LHS is -2048 and
// non-zero otherwise.
if (CVal == -2048) {
- Val = SDValue(CurDAG->getMachineNode(
- RISCV::XORI, DL, N->getValueType(0), LHS,
- CurDAG->getSignedConstant(CVal, DL, N->getValueType(0),
- /*isTarget=*/true)),
- 0);
+ Val = SDValue(
+ CurDAG->getMachineNode(
+ RISCV::XORI, DL, N->getValueType(0), LHS,
+ CurDAG->getSignedTargetConstant(CVal, DL, N->getValueType(0))),
+ 0);
return true;
}
// If the RHS is [-2047,2048], we can use addi with -RHS to produce 0 if the
// LHS is equal to the RHS and non-zero otherwise.
if (isInt<12>(CVal) || CVal == 2048) {
- Val = SDValue(CurDAG->getMachineNode(
- RISCV::ADDI, DL, N->getValueType(0), LHS,
- CurDAG->getSignedConstant(-CVal, DL, N->getValueType(0),
- /*isTarget=*/true)),
- 0);
+ Val = SDValue(
+ CurDAG->getMachineNode(
+ RISCV::ADDI, DL, N->getValueType(0), LHS,
+ CurDAG->getSignedTargetConstant(-CVal, DL, N->getValueType(0))),
+ 0);
return true;
}
if (isPowerOf2_64(CVal) && Subtarget->hasStdExtZbs()) {
@@ -3424,8 +3421,7 @@ bool RISCVDAGToDAGISel::selectSimm5Shl2(SDValue N, SDValue &Simm5,
return false;
EVT Ty = N->getValueType(0);
- Simm5 = CurDAG->getSignedConstant(Offset >> Shift, SDLoc(N), Ty,
- /*isTarget=*/true);
+ Simm5 = CurDAG->getSignedTargetConstant(Offset >> Shift, SDLoc(N), Ty);
Shl2 = CurDAG->getTargetConstant(Shift, SDLoc(N), Ty);
return true;
}
@@ -3442,16 +3438,16 @@ bool RISCVDAGToDAGISel::selectVLOp(SDValue N, SDValue &VL) {
N->getValueType(0));
} else if (C && C->isAllOnes()) {
// Treat all ones as VLMax.
- VL = CurDAG->getSignedConstant(RISCV::VLMaxSentinel, SDLoc(N),
- N->getValueType(0), /*isTarget=*/true);
+ VL = CurDAG->getSignedTargetConstant(RISCV::VLMaxSentinel, SDLoc(N),
+ N->getValueType(0));
} else if (isa<RegisterSDNode>(N) &&
cast<RegisterSDNode>(N)->getReg() == RISCV::X0) {
// All our VL operands use an operand that allows GPRNoX0 or an immediate
// as the register class. Convert X0 to a special immediate to pass the
// MachineVerifier. This is recognized specially by the vsetvli insertion
// pass.
- VL = CurDAG->getSignedConstant(RISCV::VLMaxSentinel, SDLoc(N),
- N->getValueType(0), /*isTarget=*/true);
+ VL = CurDAG->getSignedTargetConstant(RISCV::VLMaxSentinel, SDLoc(N),
+ N->getValueType(0));
} else {
VL = N;
}
@@ -3509,8 +3505,8 @@ static bool selectVSplatImmHelper(SDValue N, SDValue &SplatVal,
if (!ValidateImm(SplatImm))
return false;
- SplatVal = DAG.getSignedConstant(SplatImm, SDLoc(N), Subtarget.getXLenVT(),
- /*isTarget=*/true);
+ SplatVal =
+ DAG.getSignedTargetConstant(SplatImm, SDLoc(N), Subtarget.getXLenVT());
return true;
}
@@ -3610,8 +3606,8 @@ bool RISCVDAGToDAGISel::selectRVVSimm5(SDValue N, unsigned Width,
if (!isInt<5>(ImmVal))
return false;
- Imm = CurDAG->getSignedConstant(ImmVal, SDLoc(N), Subtarget->getXLenVT(),
- /*isTarget=*/true);
+ Imm = CurDAG->getSignedTargetConstant(ImmVal, SDLoc(N),
+ Subtarget->getXLenVT());
return true;
}
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 35040734d71dfa..675809348b0e66 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -20784,8 +20784,8 @@ void RISCVTargetLowering::LowerAsmOperandForConstraint(
if (auto *C = dyn_cast<ConstantSDNode>(Op)) {
uint64_t CVal = C->getSExtValue();
if (isInt<12>(CVal))
- Ops.push_back(DAG.getSignedConstant(
- CVal, SDLoc(Op), Subtarget.getXLenVT(), /*isTarget=*/true));
+ Ops.push_back(DAG.getSignedTargetConstant(CVal, SDLoc(Op),
+ Subtarget.getXLenVT()));
}
return;
case 'J':
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 1908f5e5dede85..5747f05ffafd47 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -415,14 +415,14 @@ def AddrRegImm : ComplexPattern<iPTR, 2, "SelectAddrRegImm">;
// Return the negation of an immediate value.
def NegImm : SDNodeXForm<imm, [{
- return CurDAG->getSignedConstant(-N->getSExtValue(), SDLoc(N),
- N->getValueType(0), /*isTarget=*/true);
+ return CurDAG->getSignedTargetConstant(-N->getSExtValue(), SDLoc(N),
+ N->getValueType(0));
}]>;
// Return an immediate value minus 32.
def ImmSub32 : SDNodeXForm<imm, [{
- return CurDAG->getSignedConstant(N->getSExtValue() - 32, SDLoc(N),
- N->getValueType(0), /*isTarget=*/true);
+ return CurDAG->getSignedTargetConstant(N->getSExtValue() - 32, SDLoc(N),
+ N->getValueType(0));
}]>;
// Return an immediate subtracted from XLen.
@@ -454,16 +454,15 @@ def AddiPair : PatLeaf<(imm), [{
def AddiPairImmSmall : SDNodeXForm<imm, [{
int64_t Imm = N->getSExtValue();
int64_t Adj = N->getSExtValue() < 0 ? -2048 : 2047;
- return CurDAG->getSignedConstant(Imm - Adj, SDLoc(N),
- N->getValueType(0), /*isTarget=*/true);
+ return CurDAG->getSignedTargetConstant(Imm - Adj, SDLoc(N),
+ N->getValueType(0));
}]>;
// Return -2048 if immediate is negative or 2047 if positive. These are the
// largest simm12 values.
def AddiPairImmLarge : SDNodeXForm<imm, [{
int64_t Imm = N->getSExtValue() < 0 ? -2048 : 2047;
- return CurDAG->getSignedConstant(Imm, SDLoc(N),
- N->getValueType(0), /*isTarget=*/true);
+ return CurDAG->getSignedTargetConstant(Imm, SDLoc(N), N->getValueType(0));
}]>;
def TrailingZeros : SDNodeXForm<imm, [{
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 2654a54c95d1b2..6c4e41711440e6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -104,8 +104,8 @@ def vec_rm : RISCVOp {
def VLOp : ComplexPattern<XLenVT, 1, "selectVLOp">;
def DecImm : SDNodeXForm<imm, [{
- return CurDAG->getSignedConstant(N->getSExtValue() - 1, SDLoc(N),
- N->getValueType(0), /*isTarget=*/true);
+ return CurDAG->getSignedTargetConstant(N->getSExtValue() - 1, SDLoc(N),
+ N->getValueType(0));
}]>;
defvar TAIL_AGNOSTIC = 1;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index ccb851f9322d62..69e4b30dc4fc8f 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -145,8 +145,8 @@ def BCLRIANDIMask : PatLeaf<(imm), [{
}]>;
def BCLRIANDIMaskLow : SDNodeXForm<imm, [{
- return CurDAG->getSignedConstant((N->getZExtValue() & 0x7ff) | ~0x7ffull,
- SDLoc(N), N->getValueType(0), /*isTarget=*/true);
+ return CurDAG->getSignedTargetConstant((N->getZExtValue() & 0x7ff) | ~0x7ffull,
+ SDLoc(N), N->getValueType(0));
}]>;
def CSImm12MulBy4 : PatLeaf<(imm), [{
@@ -167,13 +167,13 @@ def CSImm12MulBy8 : PatLeaf<(imm), [{
}]>;
def SimmShiftRightBy2XForm : SDNodeXForm<imm, [{
- return CurDAG->getSignedConstant(N->getSExtValue() >> 2, SDLoc(N),
- N->getValueType(0), /*isTarget=*/true);
+ return CurDAG->getSignedTargetConstant(N->getSExtValue() >> 2, SDLoc(N),
+ N->getValueType(0));
}]>;
def SimmShiftRightBy3XForm : SDNodeXForm<imm, [{
- return CurDAG->getSignedConstant(N->getSExtValue() >> 3, SDLoc(N),
- N->getValueType(0), /*isTarget=*/true);
+ return CurDAG->getSignedTargetConstant(N->getSExtValue() >> 3, SDLoc(N),
+ N->getValueType(0));
}]>;
// Pattern to exclude simm12 immediates from matching, namely `non_imm12`.
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