[llvm] [RISCV] Fix FP64 DinX R Regclass (PR #116688)

[Sam Elliott via llvm-commits]

https://github.com/lenary created https://github.com/llvm/llvm-project/pull/116688

This was a typo in llvm/llvm-project#112983 that didn't cause build failures but is still wrong.

---

I have half a PR to merge the GPR and GPRF64 classes, but this should go in before that (rebasing that PR is how I noticed this problem)

>From e43900996b0c5bdd1cc1798c5f2a4ff8b53b2dd4 Mon Sep 17 00:00:00 2001
From: Sam Elliott <quic_aelliott at quicinc.com>
Date: Mon, 18 Nov 2024 12:05:36 -0800
Subject: [PATCH] [RISCV] Fix FP64 DinX R Regclass

This was a typo in llvm/llvm-project#112983 that didn't cause build
failures but is still wrong.
---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 35040734d71dfa..556b337da4d68f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -20531,7 +20531,7 @@ RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
       break;
     case 'R':
       if (VT == MVT::f64 && !Subtarget.is64Bit() && Subtarget.hasStdExtZdinx())
-        return std::make_pair(0U, &RISCV::GPRF64PairCRegClass);
+        return std::make_pair(0U, &RISCV::GPRF64PairNoX0RegClass);
       return std::make_pair(0U, &RISCV::GPRPairNoX0RegClass);
     default:
       break;