[llvm] [AArch64][FEAT_CMPBR] Codegen for Armv9.6-a compare-and-branch (PR #116465)

[David Tellenbach via llvm-commits]

dtellenbach wrote:

> I agree - I would suggest changing the instructions to work more like the psuedos you have added, where the condition is an operand. That looks like a nicer way of specifying the instruction for codegen. Unfortunate I don't know if it is possible to easily have an instruction where the mnemonic is based on one of the operands, so maybe this is OK.

Yeah, I've looked into doing that a while ago, and it was more painful than helpful. I think there is no out-of-the-box functionality to treat an operand as part of the mnemonic. I think CB is especially unthankful for that as the condition codes are not only different from the standard 4-bit ones but register and immediate instruction variants use different encodings for the same conditions. That means that, e.g. during Asm parsing, you can't decode the condition code operand before you handle the later immediate or register operands. It's doable but different from what we currently do. 

https://github.com/llvm/llvm-project/pull/116465