[llvm] [ARM] Stop gluing VFP comparisons to FMSTAT (PR #116676)
Sergei Barannikov via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 18 10:43:12 PST 2024
https://github.com/s-barannikov created https://github.com/llvm/llvm-project/pull/116676
Depends on https://github.com/llvm/llvm-project/pull/116547
>From c37a1c4957a3b98f9e335a1f9133d509e245745c Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Mon, 18 Nov 2024 21:41:30 +0300
Subject: [PATCH] [ARM] Stop gluing VFP comparisons to FMSTAT
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 26 +-
llvm/lib/Target/ARM/ARMInstrVFP.td | 56 +-
llvm/lib/Target/ARM/ARMRegisterInfo.td | 4 +-
llvm/test/CodeGen/ARM/fcmp-xo.ll | 10 +-
llvm/test/CodeGen/ARM/fp16-instructions.ll | 58 +-
llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll | 32 +-
llvm/test/CodeGen/ARM/fptosi-sat-scalar.ll | 729 +--
llvm/test/CodeGen/ARM/fptoui-sat-scalar.ll | 420 +-
.../CodeGen/ARM/minnum-maxnum-intrinsics.ll | 94 +-
llvm/test/CodeGen/ARM/select.ll | 20 +-
llvm/test/CodeGen/Thumb2/mve-fmas.ll | 116 +-
.../CodeGen/Thumb2/mve-fptosi-sat-vector.ll | 3953 +++++++----------
.../CodeGen/Thumb2/mve-fptoui-sat-vector.ll | 1959 +++-----
llvm/test/CodeGen/Thumb2/mve-pred-ext.ll | 28 +-
llvm/test/CodeGen/Thumb2/mve-vcmpf.ll | 50 +-
llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll | 80 +-
llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll | 84 +-
17 files changed, 2901 insertions(+), 4818 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 7fce91f97f3618..60cc7ff0b995c7 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -4969,14 +4969,14 @@ SDValue ARMTargetLowering::getVFPCmp(SDValue LHS, SDValue RHS,
SelectionDAG &DAG, const SDLoc &dl,
bool Signaling) const {
assert(Subtarget->hasFP64() || RHS.getValueType() != MVT::f64);
- SDValue Cmp;
+ SDValue Flags;
if (!isFloatingPointZero(RHS))
- Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPE : ARMISD::CMPFP,
- dl, MVT::Glue, LHS, RHS);
+ Flags = DAG.getNode(Signaling ? ARMISD::CMPFPE : ARMISD::CMPFP, dl, FlagsVT,
+ LHS, RHS);
else
- Cmp = DAG.getNode(Signaling ? ARMISD::CMPFPEw0 : ARMISD::CMPFPw0,
- dl, MVT::Glue, LHS);
- return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
+ Flags = DAG.getNode(Signaling ? ARMISD::CMPFPEw0 : ARMISD::CMPFPw0, dl,
+ FlagsVT, LHS);
+ return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Flags);
}
/// duplicateCmp - Glue values can have only one use, so this function
@@ -4989,15 +4989,11 @@ ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
- Cmp = Cmp.getOperand(0);
- Opc = Cmp.getOpcode();
- if (Opc == ARMISD::CMPFP)
- Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
- else {
- assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
- Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
- }
- return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
+ SDValue Flags = Cmp.getOperand(0);
+ assert((Flags.getOpcode() == ARMISD::CMPFP ||
+ Flags.getOpcode() == ARMISD::CMPFPw0) &&
+ "unexpected operand of FMSTAT");
+ return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Flags);
}
// This function returns three things: the arithmetic computation itself
diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td
index 5b49f728ebb8d8..a29753909ea992 100644
--- a/llvm/lib/Target/ARM/ARMInstrVFP.td
+++ b/llvm/lib/Target/ARM/ARMInstrVFP.td
@@ -10,7 +10,17 @@
//
//===----------------------------------------------------------------------===//
-def SDT_CMPFP0 : SDTypeProfile<0, 1, [SDTCisFP<0>]>;
+def SDT_CMPFP : SDTypeProfile<1, 2, [
+ SDTCisVT<0, FlagsVT>, // out flags
+ SDTCisFP<1>, // lhs
+ SDTCisSameAs<2, 1> // rhs
+]>;
+
+def SDT_CMPFP0 : SDTypeProfile<1, 1, [
+ SDTCisVT<0, FlagsVT>, // out flags
+ SDTCisFP<1> // operand
+]>;
+
def SDT_VMOVDRR : SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,
SDTCisSameAs<1, 2>]>;
def SDT_VMOVRRD : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
@@ -18,11 +28,18 @@ def SDT_VMOVRRD : SDTypeProfile<2, 1, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
def SDT_VMOVSR : SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisVT<1, i32>]>;
-def arm_fmstat : SDNode<"ARMISD::FMSTAT", SDTNone, [SDNPInGlue, SDNPOutGlue]>;
-def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_ARMCmp, [SDNPOutGlue]>;
-def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0, [SDNPOutGlue]>;
-def arm_cmpfpe : SDNode<"ARMISD::CMPFPE", SDT_ARMCmp, [SDNPOutGlue]>;
-def arm_cmpfpe0: SDNode<"ARMISD::CMPFPEw0",SDT_CMPFP0, [SDNPOutGlue]>;
+def arm_cmpfp : SDNode<"ARMISD::CMPFP", SDT_CMPFP>;
+def arm_cmpfp0 : SDNode<"ARMISD::CMPFPw0", SDT_CMPFP0>;
+def arm_cmpfpe : SDNode<"ARMISD::CMPFPE", SDT_CMPFP>;
+def arm_cmpfpe0 : SDNode<"ARMISD::CMPFPEw0", SDT_CMPFP0>;
+
+def arm_fmstat : SDNode<"ARMISD::FMSTAT",
+ SDTypeProfile<0, 1, [
+ SDTCisVT<0, FlagsVT> // in flags
+ ]>,
+ [SDNPOutGlue] // TODO: Change Glue to a normal result.
+>;
+
def arm_fmdrr : SDNode<"ARMISD::VMOVDRR", SDT_VMOVDRR>;
def arm_fmrrd : SDNode<"ARMISD::VMOVRRD", SDT_VMOVRRD>;
def arm_vmovsr : SDNode<"ARMISD::VMOVSR", SDT_VMOVSR>;
@@ -606,12 +623,12 @@ let Defs = [FPSCR_NZCV] in {
def VCMPED : ADuI<0b11101, 0b11, 0b0100, 0b11, 0,
(outs), (ins DPR:$Dd, DPR:$Dm),
IIC_fpCMP64, "vcmpe", ".f64\t$Dd, $Dm", "",
- [(arm_cmpfpe DPR:$Dd, (f64 DPR:$Dm))]>;
+ [(set FPSCR_NZCV, (arm_cmpfpe DPR:$Dd, (f64 DPR:$Dm)))]>;
def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
(outs), (ins SPR:$Sd, SPR:$Sm),
IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm", "",
- [(arm_cmpfpe SPR:$Sd, SPR:$Sm)]> {
+ [(set FPSCR_NZCV, (arm_cmpfpe SPR:$Sd, SPR:$Sm))]> {
// Some single precision VFP instructions may be executed on both NEON and
// VFP pipelines on A8.
let D = VFPNeonA8Domain;
@@ -620,17 +637,17 @@ def VCMPES : ASuI<0b11101, 0b11, 0b0100, 0b11, 0,
def VCMPEH : AHuI<0b11101, 0b11, 0b0100, 0b11, 0,
(outs), (ins HPR:$Sd, HPR:$Sm),
IIC_fpCMP16, "vcmpe", ".f16\t$Sd, $Sm",
- [(arm_cmpfpe (f16 HPR:$Sd), (f16 HPR:$Sm))]>;
+ [(set FPSCR_NZCV, (arm_cmpfpe (f16 HPR:$Sd), (f16 HPR:$Sm)))]>;
def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0,
(outs), (ins DPR:$Dd, DPR:$Dm),
IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm", "",
- [(arm_cmpfp DPR:$Dd, (f64 DPR:$Dm))]>;
+ [(set FPSCR_NZCV, (arm_cmpfp DPR:$Dd, (f64 DPR:$Dm)))]>;
def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
(outs), (ins SPR:$Sd, SPR:$Sm),
IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm", "",
- [(arm_cmpfp SPR:$Sd, SPR:$Sm)]> {
+ [(set FPSCR_NZCV, (arm_cmpfp SPR:$Sd, SPR:$Sm))]> {
// Some single precision VFP instructions may be executed on both NEON and
// VFP pipelines on A8.
let D = VFPNeonA8Domain;
@@ -639,7 +656,7 @@ def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0,
def VCMPH : AHuI<0b11101, 0b11, 0b0100, 0b01, 0,
(outs), (ins HPR:$Sd, HPR:$Sm),
IIC_fpCMP16, "vcmp", ".f16\t$Sd, $Sm",
- [(arm_cmpfp (f16 HPR:$Sd), (f16 HPR:$Sm))]>;
+ [(set FPSCR_NZCV, (arm_cmpfp (f16 HPR:$Sd), (f16 HPR:$Sm)))]>;
} // Defs = [FPSCR_NZCV]
//===----------------------------------------------------------------------===//
@@ -669,7 +686,7 @@ let Defs = [FPSCR_NZCV] in {
def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
(outs), (ins DPR:$Dd),
IIC_fpCMP64, "vcmpe", ".f64\t$Dd, #0", "",
- [(arm_cmpfpe0 (f64 DPR:$Dd))]> {
+ [(set FPSCR_NZCV, (arm_cmpfpe0 (f64 DPR:$Dd)))]> {
let Inst{3-0} = 0b0000;
let Inst{5} = 0;
}
@@ -677,7 +694,7 @@ def VCMPEZD : ADuI<0b11101, 0b11, 0b0101, 0b11, 0,
def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
(outs), (ins SPR:$Sd),
IIC_fpCMP32, "vcmpe", ".f32\t$Sd, #0", "",
- [(arm_cmpfpe0 SPR:$Sd)]> {
+ [(set FPSCR_NZCV, (arm_cmpfpe0 SPR:$Sd))]> {
let Inst{3-0} = 0b0000;
let Inst{5} = 0;
@@ -689,7 +706,7 @@ def VCMPEZS : ASuI<0b11101, 0b11, 0b0101, 0b11, 0,
def VCMPEZH : AHuI<0b11101, 0b11, 0b0101, 0b11, 0,
(outs), (ins HPR:$Sd),
IIC_fpCMP16, "vcmpe", ".f16\t$Sd, #0",
- [(arm_cmpfpe0 (f16 HPR:$Sd))]> {
+ [(set FPSCR_NZCV, (arm_cmpfpe0 (f16 HPR:$Sd)))]> {
let Inst{3-0} = 0b0000;
let Inst{5} = 0;
}
@@ -697,7 +714,7 @@ def VCMPEZH : AHuI<0b11101, 0b11, 0b0101, 0b11, 0,
def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
(outs), (ins DPR:$Dd),
IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0", "",
- [(arm_cmpfp0 (f64 DPR:$Dd))]> {
+ [(set FPSCR_NZCV, (arm_cmpfp0 (f64 DPR:$Dd)))]> {
let Inst{3-0} = 0b0000;
let Inst{5} = 0;
}
@@ -705,7 +722,7 @@ def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0,
def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
(outs), (ins SPR:$Sd),
IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0", "",
- [(arm_cmpfp0 SPR:$Sd)]> {
+ [(set FPSCR_NZCV, (arm_cmpfp0 SPR:$Sd))]> {
let Inst{3-0} = 0b0000;
let Inst{5} = 0;
@@ -717,7 +734,7 @@ def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0,
def VCMPZH : AHuI<0b11101, 0b11, 0b0101, 0b01, 0,
(outs), (ins HPR:$Sd),
IIC_fpCMP16, "vcmp", ".f16\t$Sd, #0",
- [(arm_cmpfp0 (f16 HPR:$Sd))]> {
+ [(set FPSCR_NZCV, (arm_cmpfp0 (f16 HPR:$Sd)))]> {
let Inst{3-0} = 0b0000;
let Inst{5} = 0;
}
@@ -2492,7 +2509,8 @@ let DecoderMethod = "DecodeForVMRSandVMSR" in {
let Defs = [CPSR], Uses = [FPSCR_NZCV], Predicates = [HasFPRegs],
Rt = 0b1111 /* apsr_nzcv */ in
def FMSTAT : MovFromVFP<0b0001 /* fpscr */, (outs), (ins),
- "vmrs", "\tAPSR_nzcv, fpscr", [(arm_fmstat)]>;
+ "vmrs", "\tAPSR_nzcv, fpscr",
+ [(arm_fmstat FPSCR_NZCV)]>;
// Application level FPSCR -> GPR
let hasSideEffects = 1, Uses = [FPSCR], Predicates = [HasFPRegs] in
diff --git a/llvm/lib/Target/ARM/ARMRegisterInfo.td b/llvm/lib/Target/ARM/ARMRegisterInfo.td
index f37d0fe542b4f7..f5a675e2976bb7 100644
--- a/llvm/lib/Target/ARM/ARMRegisterInfo.td
+++ b/llvm/lib/Target/ARM/ARMRegisterInfo.td
@@ -413,7 +413,9 @@ def VCCR : RegisterClass<"ARM", [i32, v16i1, v8i1, v4i1, v2i1], 32, (add VPR)> {
// FPSCR, when the flags at the top of it are used as the input or
// output to an instruction such as MVE VADC.
-def cl_FPSCR_NZCV : RegisterClass<"ARM", [i32], 32, (add FPSCR_NZCV)>;
+def cl_FPSCR_NZCV : RegisterClass<"ARM", [i32], 32, (add FPSCR_NZCV)> {
+ let CopyCost = -1;
+}
// Scalar single precision floating point register class..
// FIXME: Allocation order changed to s0, s2, ... or s0, s4, ... as a quick hack
diff --git a/llvm/test/CodeGen/ARM/fcmp-xo.ll b/llvm/test/CodeGen/ARM/fcmp-xo.ll
index 3d5972f065859f..908dbd7a11a6b6 100644
--- a/llvm/test/CodeGen/ARM/fcmp-xo.ll
+++ b/llvm/test/CodeGen/ARM/fcmp-xo.ll
@@ -54,12 +54,12 @@ define arm_aapcs_vfpcc float @float128(float %a0) local_unnamed_addr {
; NEON-LABEL: float128:
; NEON: @ %bb.0:
; NEON-NEXT: mov.w r0, #1124073472
-; NEON-NEXT: vmov.f32 s2, #5.000000e-01
-; NEON-NEXT: vmov d3, r0, r0
-; NEON-NEXT: vmov.f32 s4, #-5.000000e-01
-; NEON-NEXT: vcmp.f32 s6, s0
+; NEON-NEXT: vmov.f32 s4, #5.000000e-01
+; NEON-NEXT: vmov d1, r0, r0
+; NEON-NEXT: vmov.f32 s6, #-5.000000e-01
+; NEON-NEXT: vcmp.f32 s2, s0
; NEON-NEXT: vmrs APSR_nzcv, fpscr
-; NEON-NEXT: vselgt.f32 s0, s4, s2
+; NEON-NEXT: vselgt.f32 s0, s6, s4
; NEON-NEXT: bx lr
%1 = fcmp nsz olt float %a0, 128.000000e+00
%2 = select i1 %1, float -5.000000e-01, float 5.000000e-01
diff --git a/llvm/test/CodeGen/ARM/fp16-instructions.ll b/llvm/test/CodeGen/ARM/fp16-instructions.ll
index 1988cb1d2f9039..7a1d5ddfa301b6 100644
--- a/llvm/test/CodeGen/ARM/fp16-instructions.ll
+++ b/llvm/test/CodeGen/ARM/fp16-instructions.ll
@@ -700,9 +700,9 @@ define half @select_cc1(ptr %a0) {
; CHECK-LABEL: select_cc1:
-; CHECK-HARDFP-FULLFP16: vcmp.f16
-; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-HARDFP-FULLFP16-NEXT: vseleq.f16 s0,
+; CHECK-HARDFP-FULLFP16: vcmp.f16
+; CHECK-HARDFP-FULLFP16: vmrs APSR_nzcv, fpscr
+; CHECK-HARDFP-FULLFP16: vseleq.f16 s0,
; CHECK-SOFTFP-FP16-A32: vcmp.f32
; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
@@ -728,9 +728,9 @@ define half @select_cc_ge1(ptr %a0) {
; CHECK-LABEL: select_cc_ge1:
-; CHECK-HARDFP-FULLFP16: vcmp.f16
-; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-HARDFP-FULLFP16-NEXT: vselge.f16 s0,
+; CHECK-HARDFP-FULLFP16: vcmp.f16
+; CHECK-HARDFP-FULLFP16: vmrs APSR_nzcv, fpscr
+; CHECK-HARDFP-FULLFP16: vselge.f16 s0,
; CHECK-SOFTFP-FP16-A32: vcmp.f32
; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
@@ -751,9 +751,9 @@ define half @select_cc_ge2(ptr %a0) {
; CHECK-LABEL: select_cc_ge2:
-; CHECK-HARDFP-FULLFP16: vcmp.f16
-; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-HARDFP-FULLFP16-NEXT: vselge.f16 s0,
+; CHECK-HARDFP-FULLFP16: vcmp.f16
+; CHECK-HARDFP-FULLFP16: vmrs APSR_nzcv, fpscr
+; CHECK-HARDFP-FULLFP16: vselge.f16 s0,
; CHECK-SOFTFP-FP16-A32: vcmp.f32
; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
@@ -774,9 +774,9 @@ define half @select_cc_ge3(ptr %a0) {
; CHECK-LABEL: select_cc_ge3:
-; CHECK-HARDFP-FULLFP16: vcmp.f16
-; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-HARDFP-FULLFP16-NEXT: vselge.f16 s0,
+; CHECK-HARDFP-FULLFP16: vcmp.f16
+; CHECK-HARDFP-FULLFP16: vmrs APSR_nzcv, fpscr
+; CHECK-HARDFP-FULLFP16: vselge.f16 s0,
; CHECK-SOFTFP-FP16-A32: vcmp.f32
; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
@@ -797,9 +797,9 @@ define half @select_cc_ge4(ptr %a0) {
; CHECK-LABEL: select_cc_ge4:
-; CHECK-HARDFP-FULLFP16: vcmp.f16
-; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-HARDFP-FULLFP16-NEXT: vselge.f16 s0, s{{.}}, s{{.}}
+; CHECK-HARDFP-FULLFP16: vcmp.f16
+; CHECK-HARDFP-FULLFP16: vmrs APSR_nzcv, fpscr
+; CHECK-HARDFP-FULLFP16: vselge.f16 s0, s{{.}}, s{{.}}
; CHECK-SOFTFP-FP16-A32: vcmp.f32
; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
@@ -821,9 +821,9 @@ define half @select_cc_gt1(ptr %a0) {
; CHECK-LABEL: select_cc_gt1:
-; CHECK-HARDFP-FULLFP16: vcmp.f16
-; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-HARDFP-FULLFP16-NEXT: vselgt.f16 s0, s{{.}}, s{{.}}
+; CHECK-HARDFP-FULLFP16: vcmp.f16
+; CHECK-HARDFP-FULLFP16: vmrs APSR_nzcv, fpscr
+; CHECK-HARDFP-FULLFP16: vselgt.f16 s0, s{{.}}, s{{.}}
; CHECK-SOFTFP-FP16-A32: vcmp.f32
; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
@@ -844,9 +844,9 @@ define half @select_cc_gt2(ptr %a0) {
; CHECK-LABEL: select_cc_gt2:
-; CHECK-HARDFP-FULLFP16: vcmp.f16
-; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-HARDFP-FULLFP16-NEXT: vselgt.f16 s0, s{{.}}, s{{.}}
+; CHECK-HARDFP-FULLFP16: vcmp.f16
+; CHECK-HARDFP-FULLFP16: vmrs APSR_nzcv, fpscr
+; CHECK-HARDFP-FULLFP16: vselgt.f16 s0, s{{.}}, s{{.}}
; CHECK-SOFTFP-FP16-A32: vcmp.f32
; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
@@ -867,9 +867,9 @@ define half @select_cc_gt3(ptr %a0) {
; CHECK-LABEL: select_cc_gt3:
-; CHECK-HARDFP-FULLFP16: vcmp.f16
-; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-HARDFP-FULLFP16-NEXT: vselgt.f16 s0, s{{.}}, s{{.}}
+; CHECK-HARDFP-FULLFP16: vcmp.f16
+; CHECK-HARDFP-FULLFP16: vmrs APSR_nzcv, fpscr
+; CHECK-HARDFP-FULLFP16: vselgt.f16 s0, s{{.}}, s{{.}}
; CHECK-SOFTFP-FP16-A32: vcmp.f32
; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
@@ -890,9 +890,9 @@ define half @select_cc_gt4(ptr %a0) {
; CHECK-LABEL: select_cc_gt4:
-; CHECK-HARDFP-FULLFP16: vcmp.f16
-; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-HARDFP-FULLFP16-NEXT: vselgt.f16 s0, s{{.}}, s{{.}}
+; CHECK-HARDFP-FULLFP16: vcmp.f16
+; CHECK-HARDFP-FULLFP16: vmrs APSR_nzcv, fpscr
+; CHECK-HARDFP-FULLFP16: vselgt.f16 s0, s{{.}}, s{{.}}
; CHECK-SOFTFP-FP16-A32: vcmp.f32
; CHECK-SOFTFP-FP16-A32-NEXT: vmrs APSR_nzcv, fpscr
@@ -923,10 +923,10 @@ entry:
; CHECK-LABEL: select_cc4:
; CHECK-HARDFP-FULLFP16: vldr.16 [[S2:s[0-9]]], .LCPI{{.*}}
+; CHECK-HARDFP-FULLFP16: vcmp.f16 s0, [[S2]]
; CHECK-HARDFP-FULLFP16: vldr.16 [[S4:s[0-9]]], .LCPI{{.*}}
+; CHECK-HARDFP-FULLFP16: vmrs APSR_nzcv, fpscr
; CHECK-HARDFP-FULLFP16: vmov.f16 [[S6:s[0-9]]], #-2.000000e+00
-; CHECK-HARDFP-FULLFP16: vcmp.f16 s0, [[S2]]
-; CHECK-HARDFP-FULLFP16-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-HARDFP-FULLFP16-NEXT: vseleq.f16 [[S0:s[0-9]]], [[S6]], [[S4]]
; CHECK-HARDFP-FULLFP16-NEXT: vselvs.f16 s0, [[S6]], [[S0]]
diff --git a/llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll b/llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll
index 56e734c4404336..996b46c51ab361 100644
--- a/llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll
+++ b/llvm/test/CodeGen/ARM/fp16-vminmaxnm-safe.ll
@@ -5,11 +5,11 @@
define half @fp16_vminnm_o(half %a, half %b) {
; CHECK-LABEL: fp16_vminnm_o:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.f16 s0, r1
-; CHECK-NEXT: vmov.f16 s2, r0
-; CHECK-NEXT: vcmp.f16 s0, s2
+; CHECK-NEXT: vmov.f16 s0, r0
+; CHECK-NEXT: vmov.f16 s2, r1
+; CHECK-NEXT: vcmp.f16 s2, s0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vselgt.f16 s0, s2, s0
+; CHECK-NEXT: vselgt.f16 s0, s0, s2
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
entry:
@@ -37,11 +37,11 @@ entry:
define half @fp16_vminnm_u(half %a, half %b) {
; CHECK-LABEL: fp16_vminnm_u:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.f16 s0, r0
-; CHECK-NEXT: vmov.f16 s2, r1
-; CHECK-NEXT: vcmp.f16 s0, s2
+; CHECK-NEXT: vmov.f16 s0, r1
+; CHECK-NEXT: vmov.f16 s2, r0
+; CHECK-NEXT: vcmp.f16 s2, s0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vselge.f16 s0, s2, s0
+; CHECK-NEXT: vselge.f16 s0, s0, s2
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
entry:
@@ -53,11 +53,11 @@ entry:
define half @fp16_vminnm_ule(half %a, half %b) {
; CHECK-LABEL: fp16_vminnm_ule:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.f16 s0, r0
-; CHECK-NEXT: vmov.f16 s2, r1
-; CHECK-NEXT: vcmp.f16 s0, s2
+; CHECK-NEXT: vmov.f16 s0, r1
+; CHECK-NEXT: vmov.f16 s2, r0
+; CHECK-NEXT: vcmp.f16 s2, s0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vselgt.f16 s0, s2, s0
+; CHECK-NEXT: vselgt.f16 s0, s0, s2
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
entry:
@@ -69,11 +69,11 @@ entry:
define half @fp16_vminnm_u_rev(half %a, half %b) {
; CHECK-LABEL: fp16_vminnm_u_rev:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov.f16 s0, r1
-; CHECK-NEXT: vmov.f16 s2, r0
-; CHECK-NEXT: vcmp.f16 s0, s2
+; CHECK-NEXT: vmov.f16 s0, r0
+; CHECK-NEXT: vmov.f16 s2, r1
+; CHECK-NEXT: vcmp.f16 s2, s0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vselge.f16 s0, s2, s0
+; CHECK-NEXT: vselge.f16 s0, s0, s2
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bx lr
entry:
diff --git a/llvm/test/CodeGen/ARM/fptosi-sat-scalar.ll b/llvm/test/CodeGen/ARM/fptosi-sat-scalar.ll
index 4b27e804e6df9a..84f6ee276ba5f1 100644
--- a/llvm/test/CodeGen/ARM/fptosi-sat-scalar.ll
+++ b/llvm/test/CodeGen/ARM/fptosi-sat-scalar.ll
@@ -258,11 +258,11 @@ define i13 @test_signed_i13_f32(float %f) nounwind {
; VFP2: @ %bb.0:
; VFP2-NEXT: vmov s0, r0
; VFP2-NEXT: vldr s2, .LCPI2_0
+; VFP2-NEXT: vldr s6, .LCPI2_1
; VFP2-NEXT: vcvt.s32.f32 s4, s0
; VFP2-NEXT: vcmp.f32 s0, s2
-; VFP2-NEXT: vldr s2, .LCPI2_1
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s0, s2
+; VFP2-NEXT: vcmp.f32 s0, s6
; VFP2-NEXT: vmov r0, s4
; VFP2-NEXT: itt lt
; VFP2-NEXT: movwlt r0, #61440
@@ -358,11 +358,11 @@ define i16 @test_signed_i16_f32(float %f) nounwind {
; VFP2: @ %bb.0:
; VFP2-NEXT: vmov s0, r0
; VFP2-NEXT: vldr s2, .LCPI3_0
+; VFP2-NEXT: vldr s6, .LCPI3_1
; VFP2-NEXT: vcvt.s32.f32 s4, s0
; VFP2-NEXT: vcmp.f32 s0, s2
-; VFP2-NEXT: vldr s2, .LCPI3_1
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s0, s2
+; VFP2-NEXT: vcmp.f32 s0, s6
; VFP2-NEXT: vmov r0, s4
; VFP2-NEXT: itt lt
; VFP2-NEXT: movwlt r0, #32768
@@ -458,11 +458,11 @@ define i19 @test_signed_i19_f32(float %f) nounwind {
; VFP2: @ %bb.0:
; VFP2-NEXT: vmov s0, r0
; VFP2-NEXT: vldr s2, .LCPI4_0
+; VFP2-NEXT: vldr s6, .LCPI4_1
; VFP2-NEXT: vcvt.s32.f32 s4, s0
; VFP2-NEXT: vcmp.f32 s0, s2
-; VFP2-NEXT: vldr s2, .LCPI4_1
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s0, s2
+; VFP2-NEXT: vcmp.f32 s0, s6
; VFP2-NEXT: vmov r0, s4
; VFP2-NEXT: itt lt
; VFP2-NEXT: movlt r0, #0
@@ -639,39 +639,31 @@ define i50 @test_signed_i50_f32(float %f) nounwind {
;
; VFP-LABEL: test_signed_i50_f32:
; VFP: @ %bb.0:
-; VFP-NEXT: .save {r7, lr}
-; VFP-NEXT: push {r7, lr}
-; VFP-NEXT: .vsave {d8}
-; VFP-NEXT: vpush {d8}
-; VFP-NEXT: vmov s16, r0
+; VFP-NEXT: .save {r4, lr}
+; VFP-NEXT: push {r4, lr}
+; VFP-NEXT: mov r4, r0
; VFP-NEXT: bl __aeabi_f2lz
; VFP-NEXT: vldr s0, .LCPI6_0
-; VFP-NEXT: vldr s2, .LCPI6_1
-; VFP-NEXT: vcmp.f32 s16, s0
+; VFP-NEXT: vmov s2, r4
+; VFP-NEXT: vldr s4, .LCPI6_1
+; VFP-NEXT: vcmp.f32 s2, s0
; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s16, s2
-; VFP-NEXT: itt lt
+; VFP-NEXT: ittt lt
; VFP-NEXT: movlt r1, #0
; VFP-NEXT: movtlt r1, #65534
+; VFP-NEXT: movlt r0, #0
+; VFP-NEXT: vcmp.f32 s2, s4
; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s16, s0
-; VFP-NEXT: itt gt
+; VFP-NEXT: ittt gt
; VFP-NEXT: movwgt r1, #65535
; VFP-NEXT: movtgt r1, #1
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: it lt
-; VFP-NEXT: movlt r0, #0
-; VFP-NEXT: vcmp.f32 s16, s2
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: it gt
; VFP-NEXT: movgt.w r0, #-1
-; VFP-NEXT: vcmp.f32 s16, s16
+; VFP-NEXT: vcmp.f32 s2, s2
; VFP-NEXT: vmrs APSR_nzcv, fpscr
; VFP-NEXT: itt vs
; VFP-NEXT: movvs r0, #0
; VFP-NEXT: movvs r1, #0
-; VFP-NEXT: vpop {d8}
-; VFP-NEXT: pop {r7, pc}
+; VFP-NEXT: pop {r4, pc}
; VFP-NEXT: .p2align 2
; VFP-NEXT: @ %bb.1:
; VFP-NEXT: .LCPI6_0:
@@ -765,27 +757,18 @@ define i64 @test_signed_i64_f32(float %f) nounwind {
; VFP-NEXT: vldr s4, .LCPI7_1
; VFP-NEXT: vcmp.f32 s2, s0
; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s2, s4
-; VFP-NEXT: it lt
+; VFP-NEXT: itt lt
; VFP-NEXT: movlt r0, #0
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s2, s2
-; VFP-NEXT: it gt
-; VFP-NEXT: movgt.w r0, #-1
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s2, s0
-; VFP-NEXT: it vs
-; VFP-NEXT: movvs r0, #0
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: it lt
; VFP-NEXT: movlt.w r1, #-2147483648
; VFP-NEXT: vcmp.f32 s2, s4
; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: it gt
+; VFP-NEXT: itt gt
; VFP-NEXT: mvngt r1, #-2147483648
+; VFP-NEXT: movgt.w r0, #-1
; VFP-NEXT: vcmp.f32 s2, s2
; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: it vs
+; VFP-NEXT: itt vs
+; VFP-NEXT: movvs r0, #0
; VFP-NEXT: movvs r1, #0
; VFP-NEXT: pop {r4, pc}
; VFP-NEXT: .p2align 2
@@ -923,51 +906,24 @@ define i100 @test_signed_i100_f32(float %f) nounwind {
; VFP-NEXT: vldr s4, .LCPI8_1
; VFP-NEXT: vcmp.f32 s2, s0
; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s2, s4
-; VFP-NEXT: it lt
+; VFP-NEXT: itttt lt
; VFP-NEXT: movlt r0, #0
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s2, s2
-; VFP-NEXT: it gt
-; VFP-NEXT: movgt.w r0, #-1
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s2, s0
-; VFP-NEXT: it vs
-; VFP-NEXT: movvs r0, #0
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s2, s4
-; VFP-NEXT: it lt
; VFP-NEXT: movlt r1, #0
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s2, s2
-; VFP-NEXT: it gt
-; VFP-NEXT: movgt.w r1, #-1
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s2, s0
-; VFP-NEXT: it vs
-; VFP-NEXT: movvs r1, #0
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s2, s4
-; VFP-NEXT: it lt
; VFP-NEXT: movlt r2, #0
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s2, s2
-; VFP-NEXT: it gt
-; VFP-NEXT: movgt.w r2, #-1
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s2, s0
-; VFP-NEXT: it vs
-; VFP-NEXT: movvs r2, #0
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: it lt
; VFP-NEXT: mvnlt r3, #7
; VFP-NEXT: vcmp.f32 s2, s4
; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: it gt
+; VFP-NEXT: itttt gt
; VFP-NEXT: movgt r3, #7
+; VFP-NEXT: movgt.w r2, #-1
+; VFP-NEXT: movgt.w r1, #-1
+; VFP-NEXT: movgt.w r0, #-1
; VFP-NEXT: vcmp.f32 s2, s2
; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: it vs
+; VFP-NEXT: itttt vs
+; VFP-NEXT: movvs r0, #0
+; VFP-NEXT: movvs r1, #0
+; VFP-NEXT: movvs r2, #0
; VFP-NEXT: movvs r3, #0
; VFP-NEXT: pop {r4, pc}
; VFP-NEXT: .p2align 2
@@ -1108,51 +1064,24 @@ define i128 @test_signed_i128_f32(float %f) nounwind {
; VFP-NEXT: vldr s4, .LCPI9_1
; VFP-NEXT: vcmp.f32 s2, s0
; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s2, s4
-; VFP-NEXT: it lt
+; VFP-NEXT: itttt lt
; VFP-NEXT: movlt r0, #0
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s2, s2
-; VFP-NEXT: it gt
-; VFP-NEXT: movgt.w r0, #-1
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s2, s0
-; VFP-NEXT: it vs
-; VFP-NEXT: movvs r0, #0
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s2, s4
-; VFP-NEXT: it lt
; VFP-NEXT: movlt r1, #0
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s2, s2
-; VFP-NEXT: it gt
-; VFP-NEXT: movgt.w r1, #-1
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s2, s0
-; VFP-NEXT: it vs
-; VFP-NEXT: movvs r1, #0
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s2, s4
-; VFP-NEXT: it lt
; VFP-NEXT: movlt r2, #0
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s2, s2
-; VFP-NEXT: it gt
-; VFP-NEXT: movgt.w r2, #-1
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s2, s0
-; VFP-NEXT: it vs
-; VFP-NEXT: movvs r2, #0
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: it lt
; VFP-NEXT: movlt.w r3, #-2147483648
; VFP-NEXT: vcmp.f32 s2, s4
; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: it gt
+; VFP-NEXT: itttt gt
; VFP-NEXT: mvngt r3, #-2147483648
+; VFP-NEXT: movgt.w r2, #-1
+; VFP-NEXT: movgt.w r1, #-1
+; VFP-NEXT: movgt.w r0, #-1
; VFP-NEXT: vcmp.f32 s2, s2
; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: it vs
+; VFP-NEXT: itttt vs
+; VFP-NEXT: movvs r0, #0
+; VFP-NEXT: movvs r1, #0
+; VFP-NEXT: movvs r2, #0
; VFP-NEXT: movvs r3, #0
; VFP-NEXT: pop {r4, pc}
; VFP-NEXT: .p2align 2
@@ -1451,15 +1380,15 @@ define i13 @test_signed_i13_f64(double %f) nounwind {
; VFP2: @ %bb.0:
; VFP2-NEXT: vmov d16, r0, r1
; VFP2-NEXT: vldr d17, .LCPI12_0
+; VFP2-NEXT: vldr d18, .LCPI12_1
; VFP2-NEXT: vcvt.s32.f64 s0, d16
; VFP2-NEXT: vcmp.f64 d16, d17
-; VFP2-NEXT: vldr d17, .LCPI12_1
-; VFP2-NEXT: vmov r0, s0
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
+; VFP2-NEXT: vmov r0, s0
+; VFP2-NEXT: vcmp.f64 d16, d18
; VFP2-NEXT: itt lt
; VFP2-NEXT: movwlt r0, #61440
; VFP2-NEXT: movtlt r0, #65535
-; VFP2-NEXT: vcmp.f64 d16, d17
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
; VFP2-NEXT: it gt
; VFP2-NEXT: movwgt r0, #4095
@@ -1568,15 +1497,15 @@ define i16 @test_signed_i16_f64(double %f) nounwind {
; VFP2: @ %bb.0:
; VFP2-NEXT: vmov d16, r0, r1
; VFP2-NEXT: vldr d17, .LCPI13_0
+; VFP2-NEXT: vldr d18, .LCPI13_1
; VFP2-NEXT: vcvt.s32.f64 s0, d16
; VFP2-NEXT: vcmp.f64 d16, d17
-; VFP2-NEXT: vldr d17, .LCPI13_1
-; VFP2-NEXT: vmov r0, s0
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
+; VFP2-NEXT: vmov r0, s0
+; VFP2-NEXT: vcmp.f64 d16, d18
; VFP2-NEXT: itt lt
; VFP2-NEXT: movwlt r0, #32768
; VFP2-NEXT: movtlt r0, #65535
-; VFP2-NEXT: vcmp.f64 d16, d17
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
; VFP2-NEXT: it gt
; VFP2-NEXT: movwgt r0, #32767
@@ -1685,15 +1614,15 @@ define i19 @test_signed_i19_f64(double %f) nounwind {
; VFP2: @ %bb.0:
; VFP2-NEXT: vmov d16, r0, r1
; VFP2-NEXT: vldr d17, .LCPI14_0
+; VFP2-NEXT: vldr d18, .LCPI14_1
; VFP2-NEXT: vcvt.s32.f64 s0, d16
; VFP2-NEXT: vcmp.f64 d16, d17
-; VFP2-NEXT: vldr d17, .LCPI14_1
-; VFP2-NEXT: vmov r0, s0
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
+; VFP2-NEXT: vmov r0, s0
+; VFP2-NEXT: vcmp.f64 d16, d18
; VFP2-NEXT: itt lt
; VFP2-NEXT: movlt r0, #0
; VFP2-NEXT: movtlt r0, #65532
-; VFP2-NEXT: vcmp.f64 d16, d17
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
; VFP2-NEXT: itt gt
; VFP2-NEXT: movwgt r0, #65535
@@ -1905,42 +1834,32 @@ define i50 @test_signed_i50_f64(double %f) nounwind {
;
; VFP2-LABEL: test_signed_i50_f64:
; VFP2: @ %bb.0:
-; VFP2-NEXT: .save {r7, lr}
-; VFP2-NEXT: push {r7, lr}
-; VFP2-NEXT: .vsave {d8}
-; VFP2-NEXT: vpush {d8}
-; VFP2-NEXT: vmov d8, r0, r1
+; VFP2-NEXT: .save {r4, r5, r7, lr}
+; VFP2-NEXT: push {r4, r5, r7, lr}
+; VFP2-NEXT: mov r4, r1
+; VFP2-NEXT: mov r5, r0
; VFP2-NEXT: bl __aeabi_d2lz
; VFP2-NEXT: vldr d16, .LCPI16_0
-; VFP2-NEXT: vldr d17, .LCPI16_1
-; VFP2-NEXT: vcmp.f64 d8, d16
+; VFP2-NEXT: vmov d17, r5, r4
+; VFP2-NEXT: vldr d18, .LCPI16_1
+; VFP2-NEXT: vcmp.f64 d17, d16
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: itt lt
+; VFP2-NEXT: ittt lt
; VFP2-NEXT: movlt r1, #0
; VFP2-NEXT: movtlt r1, #65534
-; VFP2-NEXT: vcmp.f64 d8, d17
+; VFP2-NEXT: movlt r0, #0
+; VFP2-NEXT: vcmp.f64 d17, d18
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: itt gt
+; VFP2-NEXT: ittt gt
; VFP2-NEXT: movwgt r1, #65535
; VFP2-NEXT: movtgt r1, #1
-; VFP2-NEXT: vcmp.f64 d8, d8
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it vs
-; VFP2-NEXT: movvs r1, #0
-; VFP2-NEXT: vcmp.f64 d8, d16
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
-; VFP2-NEXT: movlt r0, #0
-; VFP2-NEXT: vcmp.f64 d8, d17
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
; VFP2-NEXT: movgt.w r0, #-1
-; VFP2-NEXT: vcmp.f64 d8, d8
+; VFP2-NEXT: vcmp.f64 d17, d17
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it vs
+; VFP2-NEXT: itt vs
; VFP2-NEXT: movvs r0, #0
-; VFP2-NEXT: vpop {d8}
-; VFP2-NEXT: pop {r7, pc}
+; VFP2-NEXT: movvs r1, #0
+; VFP2-NEXT: pop {r4, r5, r7, pc}
; VFP2-NEXT: .p2align 3
; VFP2-NEXT: @ %bb.1:
; VFP2-NEXT: .LCPI16_0:
@@ -2074,27 +1993,18 @@ define i64 @test_signed_i64_f64(double %f) nounwind {
; VFP2-NEXT: vldr d18, .LCPI17_1
; VFP2-NEXT: vcmp.f64 d17, d16
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
+; VFP2-NEXT: itt lt
; VFP2-NEXT: movlt r0, #0
-; VFP2-NEXT: vcmp.f64 d17, d18
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
-; VFP2-NEXT: movgt.w r0, #-1
-; VFP2-NEXT: vcmp.f64 d17, d17
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it vs
-; VFP2-NEXT: movvs r0, #0
-; VFP2-NEXT: vcmp.f64 d17, d16
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
; VFP2-NEXT: movlt.w r1, #-2147483648
; VFP2-NEXT: vcmp.f64 d17, d18
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
+; VFP2-NEXT: itt gt
; VFP2-NEXT: mvngt r1, #-2147483648
+; VFP2-NEXT: movgt.w r0, #-1
; VFP2-NEXT: vcmp.f64 d17, d17
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it vs
+; VFP2-NEXT: itt vs
+; VFP2-NEXT: movvs r0, #0
; VFP2-NEXT: movvs r1, #0
; VFP2-NEXT: pop {r4, r5, r7, pc}
; VFP2-NEXT: .p2align 3
@@ -2118,27 +2028,18 @@ define i64 @test_signed_i64_f64(double %f) nounwind {
; FP16-NEXT: vldr d2, .LCPI17_1
; FP16-NEXT: vcmp.f64 d1, d0
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
+; FP16-NEXT: itt lt
; FP16-NEXT: movlt r0, #0
-; FP16-NEXT: vcmp.f64 d1, d2
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
-; FP16-NEXT: movgt.w r0, #-1
-; FP16-NEXT: vcmp.f64 d1, d1
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it vs
-; FP16-NEXT: movvs r0, #0
-; FP16-NEXT: vcmp.f64 d1, d0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
; FP16-NEXT: movlt.w r1, #-2147483648
; FP16-NEXT: vcmp.f64 d1, d2
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
+; FP16-NEXT: itt gt
; FP16-NEXT: mvngt r1, #-2147483648
+; FP16-NEXT: movgt.w r0, #-1
; FP16-NEXT: vcmp.f64 d1, d1
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it vs
+; FP16-NEXT: itt vs
+; FP16-NEXT: movvs r0, #0
; FP16-NEXT: movvs r1, #0
; FP16-NEXT: pop {r4, r5, r7, pc}
; FP16-NEXT: .p2align 3
@@ -2287,51 +2188,24 @@ define i100 @test_signed_i100_f64(double %f) nounwind {
; VFP2-NEXT: vldr d18, .LCPI18_1
; VFP2-NEXT: vcmp.f64 d17, d16
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
+; VFP2-NEXT: itttt lt
; VFP2-NEXT: movlt r0, #0
-; VFP2-NEXT: vcmp.f64 d17, d18
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
-; VFP2-NEXT: movgt.w r0, #-1
-; VFP2-NEXT: vcmp.f64 d17, d17
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it vs
-; VFP2-NEXT: movvs r0, #0
-; VFP2-NEXT: vcmp.f64 d17, d16
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
; VFP2-NEXT: movlt r1, #0
-; VFP2-NEXT: vcmp.f64 d17, d18
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
-; VFP2-NEXT: movgt.w r1, #-1
-; VFP2-NEXT: vcmp.f64 d17, d17
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it vs
-; VFP2-NEXT: movvs r1, #0
-; VFP2-NEXT: vcmp.f64 d17, d16
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
; VFP2-NEXT: movlt r2, #0
-; VFP2-NEXT: vcmp.f64 d17, d18
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
-; VFP2-NEXT: movgt.w r2, #-1
-; VFP2-NEXT: vcmp.f64 d17, d17
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it vs
-; VFP2-NEXT: movvs r2, #0
-; VFP2-NEXT: vcmp.f64 d17, d16
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
; VFP2-NEXT: mvnlt r3, #7
; VFP2-NEXT: vcmp.f64 d17, d18
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
+; VFP2-NEXT: itttt gt
; VFP2-NEXT: movgt r3, #7
+; VFP2-NEXT: movgt.w r2, #-1
+; VFP2-NEXT: movgt.w r1, #-1
+; VFP2-NEXT: movgt.w r0, #-1
; VFP2-NEXT: vcmp.f64 d17, d17
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it vs
+; VFP2-NEXT: itttt vs
+; VFP2-NEXT: movvs r0, #0
+; VFP2-NEXT: movvs r1, #0
+; VFP2-NEXT: movvs r2, #0
; VFP2-NEXT: movvs r3, #0
; VFP2-NEXT: pop {r4, r5, r7, pc}
; VFP2-NEXT: .p2align 3
@@ -2350,56 +2224,29 @@ define i100 @test_signed_i100_f64(double %f) nounwind {
; FP16-NEXT: mov r4, r1
; FP16-NEXT: mov r5, r0
; FP16-NEXT: bl __fixdfti
-; FP16-NEXT: vldr d2, .LCPI18_0
-; FP16-NEXT: vmov d0, r5, r4
-; FP16-NEXT: vldr d1, .LCPI18_1
-; FP16-NEXT: vcmp.f64 d0, d2
+; FP16-NEXT: vldr d0, .LCPI18_0
+; FP16-NEXT: vmov d1, r5, r4
+; FP16-NEXT: vldr d2, .LCPI18_1
+; FP16-NEXT: vcmp.f64 d1, d0
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
+; FP16-NEXT: itttt lt
; FP16-NEXT: movlt r0, #0
-; FP16-NEXT: vcmp.f64 d0, d1
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
-; FP16-NEXT: movgt.w r0, #-1
-; FP16-NEXT: vcmp.f64 d0, d0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it vs
-; FP16-NEXT: movvs r0, #0
-; FP16-NEXT: vcmp.f64 d0, d2
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
; FP16-NEXT: movlt r1, #0
-; FP16-NEXT: vcmp.f64 d0, d1
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
-; FP16-NEXT: movgt.w r1, #-1
-; FP16-NEXT: vcmp.f64 d0, d0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it vs
-; FP16-NEXT: movvs r1, #0
-; FP16-NEXT: vcmp.f64 d0, d2
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
; FP16-NEXT: movlt r2, #0
-; FP16-NEXT: vcmp.f64 d0, d1
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
-; FP16-NEXT: movgt.w r2, #-1
-; FP16-NEXT: vcmp.f64 d0, d0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it vs
-; FP16-NEXT: movvs r2, #0
-; FP16-NEXT: vcmp.f64 d0, d2
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
; FP16-NEXT: mvnlt r3, #7
-; FP16-NEXT: vcmp.f64 d0, d1
+; FP16-NEXT: vcmp.f64 d1, d2
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
+; FP16-NEXT: itttt gt
; FP16-NEXT: movgt r3, #7
-; FP16-NEXT: vcmp.f64 d0, d0
+; FP16-NEXT: movgt.w r2, #-1
+; FP16-NEXT: movgt.w r1, #-1
+; FP16-NEXT: movgt.w r0, #-1
+; FP16-NEXT: vcmp.f64 d1, d1
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it vs
+; FP16-NEXT: itttt vs
+; FP16-NEXT: movvs r0, #0
+; FP16-NEXT: movvs r1, #0
+; FP16-NEXT: movvs r2, #0
; FP16-NEXT: movvs r3, #0
; FP16-NEXT: pop {r4, r5, r7, pc}
; FP16-NEXT: .p2align 3
@@ -2550,51 +2397,24 @@ define i128 @test_signed_i128_f64(double %f) nounwind {
; VFP2-NEXT: vldr d18, .LCPI19_1
; VFP2-NEXT: vcmp.f64 d17, d16
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
+; VFP2-NEXT: itttt lt
; VFP2-NEXT: movlt r0, #0
-; VFP2-NEXT: vcmp.f64 d17, d18
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
-; VFP2-NEXT: movgt.w r0, #-1
-; VFP2-NEXT: vcmp.f64 d17, d17
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it vs
-; VFP2-NEXT: movvs r0, #0
-; VFP2-NEXT: vcmp.f64 d17, d16
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
; VFP2-NEXT: movlt r1, #0
+; VFP2-NEXT: movlt r2, #0
+; VFP2-NEXT: movlt.w r3, #-2147483648
; VFP2-NEXT: vcmp.f64 d17, d18
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
+; VFP2-NEXT: itttt gt
+; VFP2-NEXT: mvngt r3, #-2147483648
+; VFP2-NEXT: movgt.w r2, #-1
; VFP2-NEXT: movgt.w r1, #-1
+; VFP2-NEXT: movgt.w r0, #-1
; VFP2-NEXT: vcmp.f64 d17, d17
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it vs
+; VFP2-NEXT: itttt vs
+; VFP2-NEXT: movvs r0, #0
; VFP2-NEXT: movvs r1, #0
-; VFP2-NEXT: vcmp.f64 d17, d16
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
-; VFP2-NEXT: movlt r2, #0
-; VFP2-NEXT: vcmp.f64 d17, d18
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
-; VFP2-NEXT: movgt.w r2, #-1
-; VFP2-NEXT: vcmp.f64 d17, d17
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it vs
; VFP2-NEXT: movvs r2, #0
-; VFP2-NEXT: vcmp.f64 d17, d16
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
-; VFP2-NEXT: movlt.w r3, #-2147483648
-; VFP2-NEXT: vcmp.f64 d17, d18
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
-; VFP2-NEXT: mvngt r3, #-2147483648
-; VFP2-NEXT: vcmp.f64 d17, d17
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it vs
; VFP2-NEXT: movvs r3, #0
; VFP2-NEXT: pop {r4, r5, r7, pc}
; VFP2-NEXT: .p2align 3
@@ -2613,56 +2433,29 @@ define i128 @test_signed_i128_f64(double %f) nounwind {
; FP16-NEXT: mov r4, r1
; FP16-NEXT: mov r5, r0
; FP16-NEXT: bl __fixdfti
-; FP16-NEXT: vldr d2, .LCPI19_0
-; FP16-NEXT: vmov d0, r5, r4
-; FP16-NEXT: vldr d1, .LCPI19_1
-; FP16-NEXT: vcmp.f64 d0, d2
+; FP16-NEXT: vldr d0, .LCPI19_0
+; FP16-NEXT: vmov d1, r5, r4
+; FP16-NEXT: vldr d2, .LCPI19_1
+; FP16-NEXT: vcmp.f64 d1, d0
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
+; FP16-NEXT: itttt lt
; FP16-NEXT: movlt r0, #0
-; FP16-NEXT: vcmp.f64 d0, d1
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
-; FP16-NEXT: movgt.w r0, #-1
-; FP16-NEXT: vcmp.f64 d0, d0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it vs
-; FP16-NEXT: movvs r0, #0
-; FP16-NEXT: vcmp.f64 d0, d2
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
; FP16-NEXT: movlt r1, #0
-; FP16-NEXT: vcmp.f64 d0, d1
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
-; FP16-NEXT: movgt.w r1, #-1
-; FP16-NEXT: vcmp.f64 d0, d0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it vs
-; FP16-NEXT: movvs r1, #0
-; FP16-NEXT: vcmp.f64 d0, d2
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
; FP16-NEXT: movlt r2, #0
-; FP16-NEXT: vcmp.f64 d0, d1
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
-; FP16-NEXT: movgt.w r2, #-1
-; FP16-NEXT: vcmp.f64 d0, d0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it vs
-; FP16-NEXT: movvs r2, #0
-; FP16-NEXT: vcmp.f64 d0, d2
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
; FP16-NEXT: movlt.w r3, #-2147483648
-; FP16-NEXT: vcmp.f64 d0, d1
+; FP16-NEXT: vcmp.f64 d1, d2
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
+; FP16-NEXT: itttt gt
; FP16-NEXT: mvngt r3, #-2147483648
-; FP16-NEXT: vcmp.f64 d0, d0
+; FP16-NEXT: movgt.w r2, #-1
+; FP16-NEXT: movgt.w r1, #-1
+; FP16-NEXT: movgt.w r0, #-1
+; FP16-NEXT: vcmp.f64 d1, d1
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it vs
+; FP16-NEXT: itttt vs
+; FP16-NEXT: movvs r0, #0
+; FP16-NEXT: movvs r1, #0
+; FP16-NEXT: movvs r2, #0
; FP16-NEXT: movvs r3, #0
; FP16-NEXT: pop {r4, r5, r7, pc}
; FP16-NEXT: .p2align 3
@@ -2949,11 +2742,11 @@ define i13 @test_signed_i13_f16(half %f) nounwind {
; VFP2-NEXT: bl __aeabi_h2f
; VFP2-NEXT: vmov s0, r0
; VFP2-NEXT: vldr s2, .LCPI22_0
+; VFP2-NEXT: vldr s6, .LCPI22_1
; VFP2-NEXT: vcvt.s32.f32 s4, s0
; VFP2-NEXT: vcmp.f32 s0, s2
-; VFP2-NEXT: vldr s2, .LCPI22_1
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s0, s2
+; VFP2-NEXT: vcmp.f32 s0, s6
; VFP2-NEXT: vmov r0, s4
; VFP2-NEXT: itt lt
; VFP2-NEXT: movwlt r0, #61440
@@ -3055,11 +2848,11 @@ define i16 @test_signed_i16_f16(half %f) nounwind {
; VFP2-NEXT: bl __aeabi_h2f
; VFP2-NEXT: vmov s0, r0
; VFP2-NEXT: vldr s2, .LCPI23_0
+; VFP2-NEXT: vldr s6, .LCPI23_1
; VFP2-NEXT: vcvt.s32.f32 s4, s0
; VFP2-NEXT: vcmp.f32 s0, s2
-; VFP2-NEXT: vldr s2, .LCPI23_1
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s0, s2
+; VFP2-NEXT: vcmp.f32 s0, s6
; VFP2-NEXT: vmov r0, s4
; VFP2-NEXT: itt lt
; VFP2-NEXT: movwlt r0, #32768
@@ -3161,11 +2954,11 @@ define i19 @test_signed_i19_f16(half %f) nounwind {
; VFP2-NEXT: bl __aeabi_h2f
; VFP2-NEXT: vmov s0, r0
; VFP2-NEXT: vldr s2, .LCPI24_0
+; VFP2-NEXT: vldr s6, .LCPI24_1
; VFP2-NEXT: vcvt.s32.f32 s4, s0
; VFP2-NEXT: vcmp.f32 s0, s2
-; VFP2-NEXT: vldr s2, .LCPI24_1
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s0, s2
+; VFP2-NEXT: vcmp.f32 s0, s6
; VFP2-NEXT: vmov r0, s4
; VFP2-NEXT: itt lt
; VFP2-NEXT: movlt r0, #0
@@ -3357,40 +3150,32 @@ define i50 @test_signed_i50_f16(half %f) nounwind {
;
; VFP2-LABEL: test_signed_i50_f16:
; VFP2: @ %bb.0:
-; VFP2-NEXT: .save {r7, lr}
-; VFP2-NEXT: push {r7, lr}
-; VFP2-NEXT: .vsave {d8}
-; VFP2-NEXT: vpush {d8}
+; VFP2-NEXT: .save {r4, lr}
+; VFP2-NEXT: push {r4, lr}
; VFP2-NEXT: bl __aeabi_h2f
-; VFP2-NEXT: vmov s16, r0
+; VFP2-NEXT: mov r4, r0
; VFP2-NEXT: bl __aeabi_f2lz
; VFP2-NEXT: vldr s0, .LCPI26_0
-; VFP2-NEXT: vldr s2, .LCPI26_1
-; VFP2-NEXT: vcmp.f32 s16, s0
+; VFP2-NEXT: vmov s2, r4
+; VFP2-NEXT: vldr s4, .LCPI26_1
+; VFP2-NEXT: vcmp.f32 s2, s0
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s16, s2
-; VFP2-NEXT: itt lt
+; VFP2-NEXT: ittt lt
; VFP2-NEXT: movlt r1, #0
; VFP2-NEXT: movtlt r1, #65534
+; VFP2-NEXT: movlt r0, #0
+; VFP2-NEXT: vcmp.f32 s2, s4
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s16, s0
-; VFP2-NEXT: itt gt
+; VFP2-NEXT: ittt gt
; VFP2-NEXT: movwgt r1, #65535
; VFP2-NEXT: movtgt r1, #1
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
-; VFP2-NEXT: movlt r0, #0
-; VFP2-NEXT: vcmp.f32 s16, s2
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
; VFP2-NEXT: movgt.w r0, #-1
-; VFP2-NEXT: vcmp.f32 s16, s16
+; VFP2-NEXT: vcmp.f32 s2, s2
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
; VFP2-NEXT: itt vs
; VFP2-NEXT: movvs r0, #0
; VFP2-NEXT: movvs r1, #0
-; VFP2-NEXT: vpop {d8}
-; VFP2-NEXT: pop {r7, pc}
+; VFP2-NEXT: pop {r4, pc}
; VFP2-NEXT: .p2align 2
; VFP2-NEXT: @ %bb.1:
; VFP2-NEXT: .LCPI26_0:
@@ -3412,21 +3197,15 @@ define i50 @test_signed_i50_f16(half %f) nounwind {
; FP16-NEXT: vldr s2, .LCPI26_1
; FP16-NEXT: vcmp.f32 s16, s0
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s2
-; FP16-NEXT: itt lt
+; FP16-NEXT: ittt lt
; FP16-NEXT: movlt r1, #0
; FP16-NEXT: movtlt r1, #65534
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s0
-; FP16-NEXT: itt gt
-; FP16-NEXT: movwgt r1, #65535
-; FP16-NEXT: movtgt r1, #1
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
; FP16-NEXT: movlt r0, #0
; FP16-NEXT: vcmp.f32 s16, s2
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
+; FP16-NEXT: ittt gt
+; FP16-NEXT: movwgt r1, #65535
+; FP16-NEXT: movtgt r1, #1
; FP16-NEXT: movgt.w r0, #-1
; FP16-NEXT: vcmp.f32 s16, s16
; FP16-NEXT: vmrs APSR_nzcv, fpscr
@@ -3531,27 +3310,18 @@ define i64 @test_signed_i64_f16(half %f) nounwind {
; VFP2-NEXT: vldr s4, .LCPI27_1
; VFP2-NEXT: vcmp.f32 s2, s0
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s2, s4
-; VFP2-NEXT: it lt
+; VFP2-NEXT: itt lt
; VFP2-NEXT: movlt r0, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s2, s2
-; VFP2-NEXT: it gt
-; VFP2-NEXT: movgt.w r0, #-1
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s2, s0
-; VFP2-NEXT: it vs
-; VFP2-NEXT: movvs r0, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
; VFP2-NEXT: movlt.w r1, #-2147483648
; VFP2-NEXT: vcmp.f32 s2, s4
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
+; VFP2-NEXT: itt gt
; VFP2-NEXT: mvngt r1, #-2147483648
+; VFP2-NEXT: movgt.w r0, #-1
; VFP2-NEXT: vcmp.f32 s2, s2
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it vs
+; VFP2-NEXT: itt vs
+; VFP2-NEXT: movvs r0, #0
; VFP2-NEXT: movvs r1, #0
; VFP2-NEXT: pop {r4, pc}
; VFP2-NEXT: .p2align 2
@@ -3575,27 +3345,18 @@ define i64 @test_signed_i64_f16(half %f) nounwind {
; FP16-NEXT: vldr s2, .LCPI27_1
; FP16-NEXT: vcmp.f32 s16, s0
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s2
-; FP16-NEXT: it lt
+; FP16-NEXT: itt lt
; FP16-NEXT: movlt r0, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s16
-; FP16-NEXT: it gt
-; FP16-NEXT: movgt.w r0, #-1
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s0
-; FP16-NEXT: it vs
-; FP16-NEXT: movvs r0, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
; FP16-NEXT: movlt.w r1, #-2147483648
; FP16-NEXT: vcmp.f32 s16, s2
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
+; FP16-NEXT: itt gt
; FP16-NEXT: mvngt r1, #-2147483648
+; FP16-NEXT: movgt.w r0, #-1
; FP16-NEXT: vcmp.f32 s16, s16
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it vs
+; FP16-NEXT: itt vs
+; FP16-NEXT: movvs r0, #0
; FP16-NEXT: movvs r1, #0
; FP16-NEXT: vpop {d8}
; FP16-NEXT: pop {r7, pc}
@@ -3737,51 +3498,24 @@ define i100 @test_signed_i100_f16(half %f) nounwind {
; VFP2-NEXT: vldr s4, .LCPI28_1
; VFP2-NEXT: vcmp.f32 s2, s0
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s2, s4
-; VFP2-NEXT: it lt
+; VFP2-NEXT: itttt lt
; VFP2-NEXT: movlt r0, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s2, s2
-; VFP2-NEXT: it gt
-; VFP2-NEXT: movgt.w r0, #-1
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s2, s0
-; VFP2-NEXT: it vs
-; VFP2-NEXT: movvs r0, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s2, s4
-; VFP2-NEXT: it lt
; VFP2-NEXT: movlt r1, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s2, s2
-; VFP2-NEXT: it gt
-; VFP2-NEXT: movgt.w r1, #-1
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s2, s0
-; VFP2-NEXT: it vs
-; VFP2-NEXT: movvs r1, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s2, s4
-; VFP2-NEXT: it lt
; VFP2-NEXT: movlt r2, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s2, s2
-; VFP2-NEXT: it gt
-; VFP2-NEXT: movgt.w r2, #-1
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s2, s0
-; VFP2-NEXT: it vs
-; VFP2-NEXT: movvs r2, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
; VFP2-NEXT: mvnlt r3, #7
; VFP2-NEXT: vcmp.f32 s2, s4
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
+; VFP2-NEXT: itttt gt
; VFP2-NEXT: movgt r3, #7
+; VFP2-NEXT: movgt.w r2, #-1
+; VFP2-NEXT: movgt.w r1, #-1
+; VFP2-NEXT: movgt.w r0, #-1
; VFP2-NEXT: vcmp.f32 s2, s2
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it vs
+; VFP2-NEXT: itttt vs
+; VFP2-NEXT: movvs r0, #0
+; VFP2-NEXT: movvs r1, #0
+; VFP2-NEXT: movvs r2, #0
; VFP2-NEXT: movvs r3, #0
; VFP2-NEXT: pop {r4, pc}
; VFP2-NEXT: .p2align 2
@@ -3805,51 +3539,24 @@ define i100 @test_signed_i100_f16(half %f) nounwind {
; FP16-NEXT: vldr s2, .LCPI28_1
; FP16-NEXT: vcmp.f32 s16, s0
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s2
-; FP16-NEXT: it lt
+; FP16-NEXT: itttt lt
; FP16-NEXT: movlt r0, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s16
-; FP16-NEXT: it gt
-; FP16-NEXT: movgt.w r0, #-1
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s0
-; FP16-NEXT: it vs
-; FP16-NEXT: movvs r0, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s2
-; FP16-NEXT: it lt
; FP16-NEXT: movlt r1, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s16
-; FP16-NEXT: it gt
-; FP16-NEXT: movgt.w r1, #-1
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s0
-; FP16-NEXT: it vs
-; FP16-NEXT: movvs r1, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s2
-; FP16-NEXT: it lt
; FP16-NEXT: movlt r2, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s16
-; FP16-NEXT: it gt
-; FP16-NEXT: movgt.w r2, #-1
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s0
-; FP16-NEXT: it vs
-; FP16-NEXT: movvs r2, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
; FP16-NEXT: mvnlt r3, #7
; FP16-NEXT: vcmp.f32 s16, s2
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
+; FP16-NEXT: itttt gt
; FP16-NEXT: movgt r3, #7
+; FP16-NEXT: movgt.w r2, #-1
+; FP16-NEXT: movgt.w r1, #-1
+; FP16-NEXT: movgt.w r0, #-1
; FP16-NEXT: vcmp.f32 s16, s16
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it vs
+; FP16-NEXT: itttt vs
+; FP16-NEXT: movvs r0, #0
+; FP16-NEXT: movvs r1, #0
+; FP16-NEXT: movvs r2, #0
; FP16-NEXT: movvs r3, #0
; FP16-NEXT: vpop {d8}
; FP16-NEXT: pop {r7, pc}
@@ -3994,51 +3701,24 @@ define i128 @test_signed_i128_f16(half %f) nounwind {
; VFP2-NEXT: vldr s4, .LCPI29_1
; VFP2-NEXT: vcmp.f32 s2, s0
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s2, s4
-; VFP2-NEXT: it lt
+; VFP2-NEXT: itttt lt
; VFP2-NEXT: movlt r0, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s2, s2
-; VFP2-NEXT: it gt
-; VFP2-NEXT: movgt.w r0, #-1
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s2, s0
-; VFP2-NEXT: it vs
-; VFP2-NEXT: movvs r0, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s2, s4
-; VFP2-NEXT: it lt
; VFP2-NEXT: movlt r1, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s2, s2
-; VFP2-NEXT: it gt
-; VFP2-NEXT: movgt.w r1, #-1
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s2, s0
-; VFP2-NEXT: it vs
-; VFP2-NEXT: movvs r1, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s2, s4
-; VFP2-NEXT: it lt
; VFP2-NEXT: movlt r2, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s2, s2
-; VFP2-NEXT: it gt
-; VFP2-NEXT: movgt.w r2, #-1
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s2, s0
-; VFP2-NEXT: it vs
-; VFP2-NEXT: movvs r2, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
; VFP2-NEXT: movlt.w r3, #-2147483648
; VFP2-NEXT: vcmp.f32 s2, s4
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
+; VFP2-NEXT: itttt gt
; VFP2-NEXT: mvngt r3, #-2147483648
+; VFP2-NEXT: movgt.w r2, #-1
+; VFP2-NEXT: movgt.w r1, #-1
+; VFP2-NEXT: movgt.w r0, #-1
; VFP2-NEXT: vcmp.f32 s2, s2
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it vs
+; VFP2-NEXT: itttt vs
+; VFP2-NEXT: movvs r0, #0
+; VFP2-NEXT: movvs r1, #0
+; VFP2-NEXT: movvs r2, #0
; VFP2-NEXT: movvs r3, #0
; VFP2-NEXT: pop {r4, pc}
; VFP2-NEXT: .p2align 2
@@ -4062,51 +3742,24 @@ define i128 @test_signed_i128_f16(half %f) nounwind {
; FP16-NEXT: vldr s2, .LCPI29_1
; FP16-NEXT: vcmp.f32 s16, s0
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s2
-; FP16-NEXT: it lt
+; FP16-NEXT: itttt lt
; FP16-NEXT: movlt r0, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s16
-; FP16-NEXT: it gt
-; FP16-NEXT: movgt.w r0, #-1
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s0
-; FP16-NEXT: it vs
-; FP16-NEXT: movvs r0, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s2
-; FP16-NEXT: it lt
; FP16-NEXT: movlt r1, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s16
-; FP16-NEXT: it gt
-; FP16-NEXT: movgt.w r1, #-1
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s0
-; FP16-NEXT: it vs
-; FP16-NEXT: movvs r1, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s2
-; FP16-NEXT: it lt
; FP16-NEXT: movlt r2, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s16
-; FP16-NEXT: it gt
-; FP16-NEXT: movgt.w r2, #-1
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s0
-; FP16-NEXT: it vs
-; FP16-NEXT: movvs r2, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
; FP16-NEXT: movlt.w r3, #-2147483648
; FP16-NEXT: vcmp.f32 s16, s2
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
+; FP16-NEXT: itttt gt
; FP16-NEXT: mvngt r3, #-2147483648
+; FP16-NEXT: movgt.w r2, #-1
+; FP16-NEXT: movgt.w r1, #-1
+; FP16-NEXT: movgt.w r0, #-1
; FP16-NEXT: vcmp.f32 s16, s16
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it vs
+; FP16-NEXT: itttt vs
+; FP16-NEXT: movvs r0, #0
+; FP16-NEXT: movvs r1, #0
+; FP16-NEXT: movvs r2, #0
; FP16-NEXT: movvs r3, #0
; FP16-NEXT: vpop {d8}
; FP16-NEXT: pop {r7, pc}
diff --git a/llvm/test/CodeGen/ARM/fptoui-sat-scalar.ll b/llvm/test/CodeGen/ARM/fptoui-sat-scalar.ll
index 3438fb113015cb..14eb67104eddac 100644
--- a/llvm/test/CodeGen/ARM/fptoui-sat-scalar.ll
+++ b/llvm/test/CodeGen/ARM/fptoui-sat-scalar.ll
@@ -503,8 +503,8 @@ define i50 @test_signed_i50_f32(float %f) nounwind {
; VFP-NEXT: vcmp.f32 s16, #0
; VFP-NEXT: vmrs APSR_nzcv, fpscr
; VFP-NEXT: itt lt
-; VFP-NEXT: movlt r0, #0
; VFP-NEXT: movlt r1, #0
+; VFP-NEXT: movlt r0, #0
; VFP-NEXT: vcmp.f32 s16, s0
; VFP-NEXT: vmrs APSR_nzcv, fpscr
; VFP-NEXT: ittt gt
@@ -586,19 +586,13 @@ define i64 @test_signed_i64_f32(float %f) nounwind {
; VFP-NEXT: vldr s0, .LCPI7_0
; VFP-NEXT: vcmp.f32 s16, #0
; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: it lt
+; VFP-NEXT: itt lt
+; VFP-NEXT: movlt r1, #0
; VFP-NEXT: movlt r0, #0
; VFP-NEXT: vcmp.f32 s16, s0
; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s16, #0
-; VFP-NEXT: it gt
+; VFP-NEXT: itt gt
; VFP-NEXT: movgt.w r0, #-1
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: it lt
-; VFP-NEXT: movlt r1, #0
-; VFP-NEXT: vcmp.f32 s16, s0
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: it gt
; VFP-NEXT: movgt.w r1, #-1
; VFP-NEXT: vpop {d8}
; VFP-NEXT: pop {r7, pc}
@@ -701,35 +695,17 @@ define i100 @test_signed_i100_f32(float %f) nounwind {
; VFP-NEXT: vldr s0, .LCPI8_0
; VFP-NEXT: vcmp.f32 s16, #0
; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: it lt
+; VFP-NEXT: itttt lt
+; VFP-NEXT: movlt r3, #0
+; VFP-NEXT: movlt r2, #0
+; VFP-NEXT: movlt r1, #0
; VFP-NEXT: movlt r0, #0
; VFP-NEXT: vcmp.f32 s16, s0
; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s16, #0
-; VFP-NEXT: it gt
+; VFP-NEXT: itttt gt
; VFP-NEXT: movgt.w r0, #-1
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s16, s0
-; VFP-NEXT: it lt
-; VFP-NEXT: movlt r1, #0
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s16, #0
-; VFP-NEXT: it gt
; VFP-NEXT: movgt.w r1, #-1
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s16, s0
-; VFP-NEXT: it lt
-; VFP-NEXT: movlt r2, #0
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s16, #0
-; VFP-NEXT: it gt
; VFP-NEXT: movgt.w r2, #-1
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: it lt
-; VFP-NEXT: movlt r3, #0
-; VFP-NEXT: vcmp.f32 s16, s0
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: it gt
; VFP-NEXT: movgt r3, #15
; VFP-NEXT: vpop {d8}
; VFP-NEXT: pop {r7, pc}
@@ -831,35 +807,17 @@ define i128 @test_signed_i128_f32(float %f) nounwind {
; VFP-NEXT: vldr s0, .LCPI9_0
; VFP-NEXT: vcmp.f32 s16, #0
; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: it lt
+; VFP-NEXT: itttt lt
+; VFP-NEXT: movlt r3, #0
+; VFP-NEXT: movlt r2, #0
+; VFP-NEXT: movlt r1, #0
; VFP-NEXT: movlt r0, #0
; VFP-NEXT: vcmp.f32 s16, s0
; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s16, #0
-; VFP-NEXT: it gt
+; VFP-NEXT: itttt gt
; VFP-NEXT: movgt.w r0, #-1
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s16, s0
-; VFP-NEXT: it lt
-; VFP-NEXT: movlt r1, #0
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s16, #0
-; VFP-NEXT: it gt
; VFP-NEXT: movgt.w r1, #-1
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s16, s0
-; VFP-NEXT: it lt
-; VFP-NEXT: movlt r2, #0
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: vcmp.f32 s16, #0
-; VFP-NEXT: it gt
; VFP-NEXT: movgt.w r2, #-1
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: it lt
-; VFP-NEXT: movlt r3, #0
-; VFP-NEXT: vcmp.f32 s16, s0
-; VFP-NEXT: vmrs APSR_nzcv, fpscr
-; VFP-NEXT: it gt
; VFP-NEXT: movgt.w r3, #-1
; VFP-NEXT: vpop {d8}
; VFP-NEXT: pop {r7, pc}
@@ -1453,8 +1411,8 @@ define i50 @test_signed_i50_f64(double %f) nounwind {
; VFP2-NEXT: vldr d16, .LCPI16_0
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
; VFP2-NEXT: itt lt
-; VFP2-NEXT: movlt r0, #0
; VFP2-NEXT: movlt r1, #0
+; VFP2-NEXT: movlt r0, #0
; VFP2-NEXT: vcmp.f64 d8, d16
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
; VFP2-NEXT: ittt gt
@@ -1564,19 +1522,13 @@ define i64 @test_signed_i64_f64(double %f) nounwind {
; VFP2-NEXT: vcmp.f64 d8, #0
; VFP2-NEXT: vldr d16, .LCPI17_0
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
+; VFP2-NEXT: itt lt
+; VFP2-NEXT: movlt r1, #0
; VFP2-NEXT: movlt r0, #0
; VFP2-NEXT: vcmp.f64 d8, d16
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
+; VFP2-NEXT: itt gt
; VFP2-NEXT: movgt.w r0, #-1
-; VFP2-NEXT: vcmp.f64 d8, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
-; VFP2-NEXT: movlt r1, #0
-; VFP2-NEXT: vcmp.f64 d8, d16
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
; VFP2-NEXT: movgt.w r1, #-1
; VFP2-NEXT: vpop {d8}
; VFP2-NEXT: pop {r7, pc}
@@ -1597,19 +1549,13 @@ define i64 @test_signed_i64_f64(double %f) nounwind {
; FP16-NEXT: vcmp.f64 d8, #0
; FP16-NEXT: vldr d0, .LCPI17_0
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
+; FP16-NEXT: itt lt
+; FP16-NEXT: movlt r1, #0
; FP16-NEXT: movlt r0, #0
; FP16-NEXT: vcmp.f64 d8, d0
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
+; FP16-NEXT: itt gt
; FP16-NEXT: movgt.w r0, #-1
-; FP16-NEXT: vcmp.f64 d8, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
-; FP16-NEXT: movlt r1, #0
-; FP16-NEXT: vcmp.f64 d8, d0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
; FP16-NEXT: movgt.w r1, #-1
; FP16-NEXT: vpop {d8}
; FP16-NEXT: pop {r7, pc}
@@ -1719,35 +1665,17 @@ define i100 @test_signed_i100_f64(double %f) nounwind {
; VFP2-NEXT: vcmp.f64 d8, #0
; VFP2-NEXT: vldr d16, .LCPI18_0
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
+; VFP2-NEXT: itttt lt
+; VFP2-NEXT: movlt r3, #0
+; VFP2-NEXT: movlt r2, #0
+; VFP2-NEXT: movlt r1, #0
; VFP2-NEXT: movlt r0, #0
; VFP2-NEXT: vcmp.f64 d8, d16
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
+; VFP2-NEXT: itttt gt
; VFP2-NEXT: movgt.w r0, #-1
-; VFP2-NEXT: vcmp.f64 d8, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
-; VFP2-NEXT: movlt r1, #0
-; VFP2-NEXT: vcmp.f64 d8, d16
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
; VFP2-NEXT: movgt.w r1, #-1
-; VFP2-NEXT: vcmp.f64 d8, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
-; VFP2-NEXT: movlt r2, #0
-; VFP2-NEXT: vcmp.f64 d8, d16
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
; VFP2-NEXT: movgt.w r2, #-1
-; VFP2-NEXT: vcmp.f64 d8, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
-; VFP2-NEXT: movlt r3, #0
-; VFP2-NEXT: vcmp.f64 d8, d16
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
; VFP2-NEXT: movgt r3, #15
; VFP2-NEXT: vpop {d8}
; VFP2-NEXT: pop {r7, pc}
@@ -1768,35 +1696,17 @@ define i100 @test_signed_i100_f64(double %f) nounwind {
; FP16-NEXT: vcmp.f64 d8, #0
; FP16-NEXT: vldr d0, .LCPI18_0
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
+; FP16-NEXT: itttt lt
+; FP16-NEXT: movlt r3, #0
+; FP16-NEXT: movlt r2, #0
+; FP16-NEXT: movlt r1, #0
; FP16-NEXT: movlt r0, #0
; FP16-NEXT: vcmp.f64 d8, d0
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
+; FP16-NEXT: itttt gt
; FP16-NEXT: movgt.w r0, #-1
-; FP16-NEXT: vcmp.f64 d8, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
-; FP16-NEXT: movlt r1, #0
-; FP16-NEXT: vcmp.f64 d8, d0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
; FP16-NEXT: movgt.w r1, #-1
-; FP16-NEXT: vcmp.f64 d8, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
-; FP16-NEXT: movlt r2, #0
-; FP16-NEXT: vcmp.f64 d8, d0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
; FP16-NEXT: movgt.w r2, #-1
-; FP16-NEXT: vcmp.f64 d8, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
-; FP16-NEXT: movlt r3, #0
-; FP16-NEXT: vcmp.f64 d8, d0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
; FP16-NEXT: movgt r3, #15
; FP16-NEXT: vpop {d8}
; FP16-NEXT: pop {r7, pc}
@@ -1902,35 +1812,17 @@ define i128 @test_signed_i128_f64(double %f) nounwind {
; VFP2-NEXT: vcmp.f64 d8, #0
; VFP2-NEXT: vldr d16, .LCPI19_0
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
+; VFP2-NEXT: itttt lt
+; VFP2-NEXT: movlt r3, #0
+; VFP2-NEXT: movlt r2, #0
+; VFP2-NEXT: movlt r1, #0
; VFP2-NEXT: movlt r0, #0
; VFP2-NEXT: vcmp.f64 d8, d16
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
+; VFP2-NEXT: itttt gt
; VFP2-NEXT: movgt.w r0, #-1
-; VFP2-NEXT: vcmp.f64 d8, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
-; VFP2-NEXT: movlt r1, #0
-; VFP2-NEXT: vcmp.f64 d8, d16
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
; VFP2-NEXT: movgt.w r1, #-1
-; VFP2-NEXT: vcmp.f64 d8, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
-; VFP2-NEXT: movlt r2, #0
-; VFP2-NEXT: vcmp.f64 d8, d16
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
; VFP2-NEXT: movgt.w r2, #-1
-; VFP2-NEXT: vcmp.f64 d8, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
-; VFP2-NEXT: movlt r3, #0
-; VFP2-NEXT: vcmp.f64 d8, d16
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
; VFP2-NEXT: movgt.w r3, #-1
; VFP2-NEXT: vpop {d8}
; VFP2-NEXT: pop {r7, pc}
@@ -1951,35 +1843,17 @@ define i128 @test_signed_i128_f64(double %f) nounwind {
; FP16-NEXT: vcmp.f64 d8, #0
; FP16-NEXT: vldr d0, .LCPI19_0
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
+; FP16-NEXT: itttt lt
+; FP16-NEXT: movlt r3, #0
+; FP16-NEXT: movlt r2, #0
+; FP16-NEXT: movlt r1, #0
; FP16-NEXT: movlt r0, #0
; FP16-NEXT: vcmp.f64 d8, d0
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
+; FP16-NEXT: itttt gt
; FP16-NEXT: movgt.w r0, #-1
-; FP16-NEXT: vcmp.f64 d8, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
-; FP16-NEXT: movlt r1, #0
-; FP16-NEXT: vcmp.f64 d8, d0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
; FP16-NEXT: movgt.w r1, #-1
-; FP16-NEXT: vcmp.f64 d8, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
-; FP16-NEXT: movlt r2, #0
-; FP16-NEXT: vcmp.f64 d8, d0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
; FP16-NEXT: movgt.w r2, #-1
-; FP16-NEXT: vcmp.f64 d8, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
-; FP16-NEXT: movlt r3, #0
-; FP16-NEXT: vcmp.f64 d8, d0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
; FP16-NEXT: movgt.w r3, #-1
; FP16-NEXT: vpop {d8}
; FP16-NEXT: pop {r7, pc}
@@ -2526,27 +2400,25 @@ define i50 @test_signed_i50_f16(half %f) nounwind {
;
; VFP2-LABEL: test_signed_i50_f16:
; VFP2: @ %bb.0:
-; VFP2-NEXT: .save {r7, lr}
-; VFP2-NEXT: push {r7, lr}
-; VFP2-NEXT: .vsave {d8}
-; VFP2-NEXT: vpush {d8}
+; VFP2-NEXT: .save {r4, lr}
+; VFP2-NEXT: push {r4, lr}
; VFP2-NEXT: bl __aeabi_h2f
-; VFP2-NEXT: vmov s16, r0
+; VFP2-NEXT: mov r4, r0
; VFP2-NEXT: bl __aeabi_f2ulz
-; VFP2-NEXT: vldr s0, .LCPI26_0
-; VFP2-NEXT: vcmp.f32 s16, #0
+; VFP2-NEXT: vmov s0, r4
+; VFP2-NEXT: vldr s2, .LCPI26_0
+; VFP2-NEXT: vcmp.f32 s0, #0
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
; VFP2-NEXT: itt lt
-; VFP2-NEXT: movlt r0, #0
; VFP2-NEXT: movlt r1, #0
-; VFP2-NEXT: vcmp.f32 s16, s0
+; VFP2-NEXT: movlt r0, #0
+; VFP2-NEXT: vcmp.f32 s0, s2
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
; VFP2-NEXT: ittt gt
; VFP2-NEXT: movwgt r1, #65535
; VFP2-NEXT: movtgt r1, #3
; VFP2-NEXT: movgt.w r0, #-1
-; VFP2-NEXT: vpop {d8}
-; VFP2-NEXT: pop {r7, pc}
+; VFP2-NEXT: pop {r4, pc}
; VFP2-NEXT: .p2align 2
; VFP2-NEXT: @ %bb.1:
; VFP2-NEXT: .LCPI26_0:
@@ -2566,8 +2438,8 @@ define i50 @test_signed_i50_f16(half %f) nounwind {
; FP16-NEXT: vcmp.f32 s16, #0
; FP16-NEXT: vmrs APSR_nzcv, fpscr
; FP16-NEXT: itt lt
-; FP16-NEXT: movlt r0, #0
; FP16-NEXT: movlt r1, #0
+; FP16-NEXT: movlt r0, #0
; FP16-NEXT: vcmp.f32 s16, s0
; FP16-NEXT: vmrs APSR_nzcv, fpscr
; FP16-NEXT: ittt gt
@@ -2642,32 +2514,24 @@ define i64 @test_signed_i64_f16(half %f) nounwind {
;
; VFP2-LABEL: test_signed_i64_f16:
; VFP2: @ %bb.0:
-; VFP2-NEXT: .save {r7, lr}
-; VFP2-NEXT: push {r7, lr}
-; VFP2-NEXT: .vsave {d8}
-; VFP2-NEXT: vpush {d8}
+; VFP2-NEXT: .save {r4, lr}
+; VFP2-NEXT: push {r4, lr}
; VFP2-NEXT: bl __aeabi_h2f
-; VFP2-NEXT: vmov s16, r0
+; VFP2-NEXT: mov r4, r0
; VFP2-NEXT: bl __aeabi_f2ulz
-; VFP2-NEXT: vldr s0, .LCPI27_0
-; VFP2-NEXT: vcmp.f32 s16, #0
+; VFP2-NEXT: vmov s0, r4
+; VFP2-NEXT: vldr s2, .LCPI27_0
+; VFP2-NEXT: vcmp.f32 s0, #0
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
+; VFP2-NEXT: itt lt
+; VFP2-NEXT: movlt r1, #0
; VFP2-NEXT: movlt r0, #0
-; VFP2-NEXT: vcmp.f32 s16, s0
+; VFP2-NEXT: vcmp.f32 s0, s2
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s16, #0
-; VFP2-NEXT: it gt
+; VFP2-NEXT: itt gt
; VFP2-NEXT: movgt.w r0, #-1
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
-; VFP2-NEXT: movlt r1, #0
-; VFP2-NEXT: vcmp.f32 s16, s0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
; VFP2-NEXT: movgt.w r1, #-1
-; VFP2-NEXT: vpop {d8}
-; VFP2-NEXT: pop {r7, pc}
+; VFP2-NEXT: pop {r4, pc}
; VFP2-NEXT: .p2align 2
; VFP2-NEXT: @ %bb.1:
; VFP2-NEXT: .LCPI27_0:
@@ -2686,19 +2550,13 @@ define i64 @test_signed_i64_f16(half %f) nounwind {
; FP16-NEXT: vldr s0, .LCPI27_0
; FP16-NEXT: vcmp.f32 s16, #0
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
+; FP16-NEXT: itt lt
+; FP16-NEXT: movlt r1, #0
; FP16-NEXT: movlt r0, #0
; FP16-NEXT: vcmp.f32 s16, s0
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, #0
-; FP16-NEXT: it gt
+; FP16-NEXT: itt gt
; FP16-NEXT: movgt.w r0, #-1
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
-; FP16-NEXT: movlt r1, #0
-; FP16-NEXT: vcmp.f32 s16, s0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
; FP16-NEXT: movgt.w r1, #-1
; FP16-NEXT: vpop {d8}
; FP16-NEXT: pop {r7, pc}
@@ -2794,48 +2652,28 @@ define i100 @test_signed_i100_f16(half %f) nounwind {
;
; VFP2-LABEL: test_signed_i100_f16:
; VFP2: @ %bb.0:
-; VFP2-NEXT: .save {r7, lr}
-; VFP2-NEXT: push {r7, lr}
-; VFP2-NEXT: .vsave {d8}
-; VFP2-NEXT: vpush {d8}
+; VFP2-NEXT: .save {r4, lr}
+; VFP2-NEXT: push {r4, lr}
; VFP2-NEXT: bl __aeabi_h2f
-; VFP2-NEXT: vmov s16, r0
+; VFP2-NEXT: mov r4, r0
; VFP2-NEXT: bl __fixunssfti
-; VFP2-NEXT: vldr s0, .LCPI28_0
-; VFP2-NEXT: vcmp.f32 s16, #0
+; VFP2-NEXT: vmov s0, r4
+; VFP2-NEXT: vldr s2, .LCPI28_0
+; VFP2-NEXT: vcmp.f32 s0, #0
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
+; VFP2-NEXT: itttt lt
+; VFP2-NEXT: movlt r3, #0
+; VFP2-NEXT: movlt r2, #0
+; VFP2-NEXT: movlt r1, #0
; VFP2-NEXT: movlt r0, #0
-; VFP2-NEXT: vcmp.f32 s16, s0
+; VFP2-NEXT: vcmp.f32 s0, s2
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s16, #0
-; VFP2-NEXT: it gt
+; VFP2-NEXT: itttt gt
; VFP2-NEXT: movgt.w r0, #-1
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s16, s0
-; VFP2-NEXT: it lt
-; VFP2-NEXT: movlt r1, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s16, #0
-; VFP2-NEXT: it gt
; VFP2-NEXT: movgt.w r1, #-1
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s16, s0
-; VFP2-NEXT: it lt
-; VFP2-NEXT: movlt r2, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s16, #0
-; VFP2-NEXT: it gt
; VFP2-NEXT: movgt.w r2, #-1
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
-; VFP2-NEXT: movlt r3, #0
-; VFP2-NEXT: vcmp.f32 s16, s0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
; VFP2-NEXT: movgt r3, #15
-; VFP2-NEXT: vpop {d8}
-; VFP2-NEXT: pop {r7, pc}
+; VFP2-NEXT: pop {r4, pc}
; VFP2-NEXT: .p2align 2
; VFP2-NEXT: @ %bb.1:
; VFP2-NEXT: .LCPI28_0:
@@ -2854,35 +2692,17 @@ define i100 @test_signed_i100_f16(half %f) nounwind {
; FP16-NEXT: vldr s0, .LCPI28_0
; FP16-NEXT: vcmp.f32 s16, #0
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
+; FP16-NEXT: itttt lt
+; FP16-NEXT: movlt r3, #0
+; FP16-NEXT: movlt r2, #0
+; FP16-NEXT: movlt r1, #0
; FP16-NEXT: movlt r0, #0
; FP16-NEXT: vcmp.f32 s16, s0
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, #0
-; FP16-NEXT: it gt
+; FP16-NEXT: itttt gt
; FP16-NEXT: movgt.w r0, #-1
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s0
-; FP16-NEXT: it lt
-; FP16-NEXT: movlt r1, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, #0
-; FP16-NEXT: it gt
; FP16-NEXT: movgt.w r1, #-1
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s0
-; FP16-NEXT: it lt
-; FP16-NEXT: movlt r2, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, #0
-; FP16-NEXT: it gt
; FP16-NEXT: movgt.w r2, #-1
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
-; FP16-NEXT: movlt r3, #0
-; FP16-NEXT: vcmp.f32 s16, s0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
; FP16-NEXT: movgt r3, #15
; FP16-NEXT: vpop {d8}
; FP16-NEXT: pop {r7, pc}
@@ -2977,48 +2797,28 @@ define i128 @test_signed_i128_f16(half %f) nounwind {
;
; VFP2-LABEL: test_signed_i128_f16:
; VFP2: @ %bb.0:
-; VFP2-NEXT: .save {r7, lr}
-; VFP2-NEXT: push {r7, lr}
-; VFP2-NEXT: .vsave {d8}
-; VFP2-NEXT: vpush {d8}
+; VFP2-NEXT: .save {r4, lr}
+; VFP2-NEXT: push {r4, lr}
; VFP2-NEXT: bl __aeabi_h2f
-; VFP2-NEXT: vmov s16, r0
+; VFP2-NEXT: mov r4, r0
; VFP2-NEXT: bl __fixunssfti
-; VFP2-NEXT: vldr s0, .LCPI29_0
-; VFP2-NEXT: vcmp.f32 s16, #0
+; VFP2-NEXT: vmov s0, r4
+; VFP2-NEXT: vldr s2, .LCPI29_0
+; VFP2-NEXT: vcmp.f32 s0, #0
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
+; VFP2-NEXT: itttt lt
+; VFP2-NEXT: movlt r3, #0
+; VFP2-NEXT: movlt r2, #0
+; VFP2-NEXT: movlt r1, #0
; VFP2-NEXT: movlt r0, #0
-; VFP2-NEXT: vcmp.f32 s16, s0
+; VFP2-NEXT: vcmp.f32 s0, s2
; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s16, #0
-; VFP2-NEXT: it gt
+; VFP2-NEXT: itttt gt
; VFP2-NEXT: movgt.w r0, #-1
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s16, s0
-; VFP2-NEXT: it lt
-; VFP2-NEXT: movlt r1, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s16, #0
-; VFP2-NEXT: it gt
; VFP2-NEXT: movgt.w r1, #-1
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s16, s0
-; VFP2-NEXT: it lt
-; VFP2-NEXT: movlt r2, #0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: vcmp.f32 s16, #0
-; VFP2-NEXT: it gt
; VFP2-NEXT: movgt.w r2, #-1
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it lt
-; VFP2-NEXT: movlt r3, #0
-; VFP2-NEXT: vcmp.f32 s16, s0
-; VFP2-NEXT: vmrs APSR_nzcv, fpscr
-; VFP2-NEXT: it gt
; VFP2-NEXT: movgt.w r3, #-1
-; VFP2-NEXT: vpop {d8}
-; VFP2-NEXT: pop {r7, pc}
+; VFP2-NEXT: pop {r4, pc}
; VFP2-NEXT: .p2align 2
; VFP2-NEXT: @ %bb.1:
; VFP2-NEXT: .LCPI29_0:
@@ -3037,35 +2837,17 @@ define i128 @test_signed_i128_f16(half %f) nounwind {
; FP16-NEXT: vldr s0, .LCPI29_0
; FP16-NEXT: vcmp.f32 s16, #0
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
+; FP16-NEXT: itttt lt
+; FP16-NEXT: movlt r3, #0
+; FP16-NEXT: movlt r2, #0
+; FP16-NEXT: movlt r1, #0
; FP16-NEXT: movlt r0, #0
; FP16-NEXT: vcmp.f32 s16, s0
; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, #0
-; FP16-NEXT: it gt
+; FP16-NEXT: itttt gt
; FP16-NEXT: movgt.w r0, #-1
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s0
-; FP16-NEXT: it lt
-; FP16-NEXT: movlt r1, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, #0
-; FP16-NEXT: it gt
; FP16-NEXT: movgt.w r1, #-1
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, s0
-; FP16-NEXT: it lt
-; FP16-NEXT: movlt r2, #0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: vcmp.f32 s16, #0
-; FP16-NEXT: it gt
; FP16-NEXT: movgt.w r2, #-1
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it lt
-; FP16-NEXT: movlt r3, #0
-; FP16-NEXT: vcmp.f32 s16, s0
-; FP16-NEXT: vmrs APSR_nzcv, fpscr
-; FP16-NEXT: it gt
; FP16-NEXT: movgt.w r3, #-1
; FP16-NEXT: vpop {d8}
; FP16-NEXT: pop {r7, pc}
diff --git a/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll b/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
index feb790821e8754..4003af5d44be81 100644
--- a/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
+++ b/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll
@@ -16,12 +16,12 @@ declare <2 x double> @llvm.maxnum.v2f64(<2 x double>, <2 x double>)
define float @fminnum32_intrinsic(float %x, float %y) {
; ARMV7-LABEL: fminnum32_intrinsic:
; ARMV7: @ %bb.0:
-; ARMV7-NEXT: vmov s0, r0
-; ARMV7-NEXT: vmov s2, r1
-; ARMV7-NEXT: vcmp.f32 s0, s2
+; ARMV7-NEXT: vmov s0, r1
+; ARMV7-NEXT: vmov s2, r0
+; ARMV7-NEXT: vcmp.f32 s2, s0
; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
-; ARMV7-NEXT: vmovlt.f32 s2, s0
-; ARMV7-NEXT: vmov r0, s2
+; ARMV7-NEXT: vmovlt.f32 s0, s2
+; ARMV7-NEXT: vmov r0, s0
; ARMV7-NEXT: bx lr
;
; ARMV8-LABEL: fminnum32_intrinsic:
@@ -102,12 +102,12 @@ define float @fminnum32_non_zero_intrinsic(float %x) {
define float @fmaxnum32_intrinsic(float %x, float %y) {
; ARMV7-LABEL: fmaxnum32_intrinsic:
; ARMV7: @ %bb.0:
-; ARMV7-NEXT: vmov s0, r0
-; ARMV7-NEXT: vmov s2, r1
-; ARMV7-NEXT: vcmp.f32 s0, s2
+; ARMV7-NEXT: vmov s0, r1
+; ARMV7-NEXT: vmov s2, r0
+; ARMV7-NEXT: vcmp.f32 s2, s0
; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
-; ARMV7-NEXT: vmovgt.f32 s2, s0
-; ARMV7-NEXT: vmov r0, s2
+; ARMV7-NEXT: vmovgt.f32 s0, s2
+; ARMV7-NEXT: vmov r0, s0
; ARMV7-NEXT: bx lr
;
; ARMV8-LABEL: fmaxnum32_intrinsic:
@@ -160,12 +160,12 @@ define float @fmaxnum32_nsz_intrinsic(float %x, float %y) {
define float @fmaxnum32_zero_intrinsic(float %x) {
; ARMV7-LABEL: fmaxnum32_zero_intrinsic:
; ARMV7: @ %bb.0:
-; ARMV7-NEXT: vmov s2, r0
-; ARMV7-NEXT: vldr s0, .LCPI5_0
-; ARMV7-NEXT: vcmp.f32 s2, #0
+; ARMV7-NEXT: vmov s0, r0
+; ARMV7-NEXT: vldr s2, .LCPI5_0
+; ARMV7-NEXT: vcmp.f32 s0, #0
; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
-; ARMV7-NEXT: vmovgt.f32 s0, s2
-; ARMV7-NEXT: vmov r0, s0
+; ARMV7-NEXT: vmovgt.f32 s2, s0
+; ARMV7-NEXT: vmov r0, s2
; ARMV7-NEXT: bx lr
; ARMV7-NEXT: .p2align 2
; ARMV7-NEXT: @ %bb.1:
@@ -425,12 +425,12 @@ define double at fmaxnum64_nsz_intrinsic(double %x, double %y) {
define double @fmaxnum64_zero_intrinsic(double %x) {
; ARMV7-LABEL: fmaxnum64_zero_intrinsic:
; ARMV7: @ %bb.0:
-; ARMV7-NEXT: vmov d17, r0, r1
-; ARMV7-NEXT: vcmp.f64 d17, #0
+; ARMV7-NEXT: vmov d16, r0, r1
+; ARMV7-NEXT: vcmp.f64 d16, #0
; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
-; ARMV7-NEXT: vmov.i32 d16, #0x0
-; ARMV7-NEXT: vmovgt.f64 d16, d17
-; ARMV7-NEXT: vmov r0, r1, d16
+; ARMV7-NEXT: vmov.i32 d17, #0x0
+; ARMV7-NEXT: vmovgt.f64 d17, d16
+; ARMV7-NEXT: vmov r0, r1, d17
; ARMV7-NEXT: bx lr
;
; ARMV8-LABEL: fmaxnum64_zero_intrinsic:
@@ -1065,18 +1065,18 @@ define <2 x double> @fminnumv264_one_zero_intrinsic(<2 x double> %x) {
;
; ARMV8M-LABEL: fminnumv264_one_zero_intrinsic:
; ARMV8M: @ %bb.0:
-; ARMV8M-NEXT: vmov d3, r2, r3
-; ARMV8M-NEXT: vldr d1, .LCPI27_0
-; ARMV8M-NEXT: vcmp.f64 d3, #0
+; ARMV8M-NEXT: vmov d1, r2, r3
+; ARMV8M-NEXT: vldr d0, .LCPI27_0
+; ARMV8M-NEXT: vcmp.f64 d1, #0
; ARMV8M-NEXT: vmrs APSR_nzcv, fpscr
; ARMV8M-NEXT: vmov d2, r0, r1
-; ARMV8M-NEXT: vmov.f64 d0, #-1.000000e+00
-; ARMV8M-NEXT: vcmp.f64 d0, d2
-; ARMV8M-NEXT: vmovlt.f64 d1, d3
+; ARMV8M-NEXT: vmov.f64 d3, #-1.000000e+00
+; ARMV8M-NEXT: vcmp.f64 d3, d2
+; ARMV8M-NEXT: vmovlt.f64 d0, d1
; ARMV8M-NEXT: vmrs APSR_nzcv, fpscr
-; ARMV8M-NEXT: vmov r2, r3, d1
-; ARMV8M-NEXT: vselgt.f64 d0, d2, d0
-; ARMV8M-NEXT: vmov r0, r1, d0
+; ARMV8M-NEXT: vmov r2, r3, d0
+; ARMV8M-NEXT: vselgt.f64 d1, d2, d3
+; ARMV8M-NEXT: vmov r0, r1, d1
; ARMV8M-NEXT: bx lr
; ARMV8M-NEXT: .p2align 3
; ARMV8M-NEXT: @ %bb.1:
@@ -1186,18 +1186,18 @@ define <2 x double> @fmaxnumv264_nsz_intrinsic(<2 x double> %x, <2 x double> %y)
define <2 x double> @fmaxnumv264_zero_intrinsic(<2 x double> %x) {
; ARMV7-LABEL: fmaxnumv264_zero_intrinsic:
; ARMV7: @ %bb.0:
-; ARMV7-NEXT: vldr d17, .LCPI30_0
-; ARMV7-NEXT: vmov d18, r2, r3
-; ARMV7-NEXT: vmov d19, r0, r1
-; ARMV7-NEXT: vcmp.f64 d18, d17
+; ARMV7-NEXT: vmov d18, r0, r1
+; ARMV7-NEXT: vldr d16, .LCPI30_0
+; ARMV7-NEXT: vcmp.f64 d18, #0
; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
-; ARMV7-NEXT: vmov.i32 d16, #0x0
-; ARMV7-NEXT: vcmp.f64 d19, #0
+; ARMV7-NEXT: vmov d19, r2, r3
+; ARMV7-NEXT: vcmp.f64 d19, d16
+; ARMV7-NEXT: vmov.i32 d17, #0x0
; ARMV7-NEXT: vmovgt.f64 d17, d18
; ARMV7-NEXT: vmrs APSR_nzcv, fpscr
-; ARMV7-NEXT: vmov r2, r3, d17
+; ARMV7-NEXT: vmov r0, r1, d17
; ARMV7-NEXT: vmovgt.f64 d16, d19
-; ARMV7-NEXT: vmov r0, r1, d16
+; ARMV7-NEXT: vmov r2, r3, d16
; ARMV7-NEXT: bx lr
; ARMV7-NEXT: .p2align 3
; ARMV7-NEXT: @ %bb.1:
@@ -1225,26 +1225,26 @@ define <2 x double> @fmaxnumv264_zero_intrinsic(<2 x double> %x) {
; ARMV8M-LABEL: fmaxnumv264_zero_intrinsic:
; ARMV8M: @ %bb.0:
; ARMV8M-NEXT: vmov d2, r0, r1
-; ARMV8M-NEXT: vldr d0, .LCPI30_0
+; ARMV8M-NEXT: vldr d1, .LCPI30_1
; ARMV8M-NEXT: vcmp.f64 d2, #0
; ARMV8M-NEXT: vmrs APSR_nzcv, fpscr
; ARMV8M-NEXT: vmov d3, r2, r3
-; ARMV8M-NEXT: vcmp.f64 d3, d0
-; ARMV8M-NEXT: vldr d1, .LCPI30_1
-; ARMV8M-NEXT: vselgt.f64 d1, d2, d1
+; ARMV8M-NEXT: vcmp.f64 d3, d1
+; ARMV8M-NEXT: vldr d0, .LCPI30_0
+; ARMV8M-NEXT: vselgt.f64 d0, d2, d0
; ARMV8M-NEXT: vmrs APSR_nzcv, fpscr
-; ARMV8M-NEXT: vmov r0, r1, d1
-; ARMV8M-NEXT: vselgt.f64 d0, d3, d0
-; ARMV8M-NEXT: vmov r2, r3, d0
+; ARMV8M-NEXT: vmov r0, r1, d0
+; ARMV8M-NEXT: vselgt.f64 d1, d3, d1
+; ARMV8M-NEXT: vmov r2, r3, d1
; ARMV8M-NEXT: bx lr
; ARMV8M-NEXT: .p2align 3
; ARMV8M-NEXT: @ %bb.1:
; ARMV8M-NEXT: .LCPI30_0:
-; ARMV8M-NEXT: .long 0 @ double -0
-; ARMV8M-NEXT: .long 2147483648
-; ARMV8M-NEXT: .LCPI30_1:
; ARMV8M-NEXT: .long 0 @ double 0
; ARMV8M-NEXT: .long 0
+; ARMV8M-NEXT: .LCPI30_1:
+; ARMV8M-NEXT: .long 0 @ double -0
+; ARMV8M-NEXT: .long 2147483648
%a = call nnan <2 x double> @llvm.maxnum.v2f64(<2 x double> %x, <2 x double><double 0.0, double -0.0>)
ret <2 x double> %a
}
diff --git a/llvm/test/CodeGen/ARM/select.ll b/llvm/test/CodeGen/ARM/select.ll
index 24ca9aeac7f2db..496a6c0f5acbbe 100644
--- a/llvm/test/CodeGen/ARM/select.ll
+++ b/llvm/test/CodeGen/ARM/select.ll
@@ -164,13 +164,13 @@ define double @f7(double %a, double %b) {
; CHECK-VFP-LABEL: f7:
; CHECK-VFP: @ %bb.0:
; CHECK-VFP-NEXT: vldr d17, .LCPI6_0
-; CHECK-VFP-NEXT: vmov d19, r0, r1
+; CHECK-VFP-NEXT: vmov d18, r0, r1
; CHECK-VFP-NEXT: vmov.f64 d16, #-1.000000e+00
-; CHECK-VFP-NEXT: vcmp.f64 d19, d17
+; CHECK-VFP-NEXT: vcmp.f64 d18, d17
; CHECK-VFP-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-VFP-NEXT: vmov d18, r2, r3
-; CHECK-VFP-NEXT: vmovmi.f64 d18, d16
-; CHECK-VFP-NEXT: vmov r0, r1, d18
+; CHECK-VFP-NEXT: vmov d19, r2, r3
+; CHECK-VFP-NEXT: vmovmi.f64 d19, d16
+; CHECK-VFP-NEXT: vmov r0, r1, d19
; CHECK-VFP-NEXT: bx lr
; CHECK-VFP-NEXT: .p2align 3
; CHECK-VFP-NEXT: @ %bb.1:
@@ -181,14 +181,14 @@ define double @f7(double %a, double %b) {
; CHECK-NEON-LABEL: f7:
; CHECK-NEON: @ %bb.0:
; CHECK-NEON-NEXT: vldr d17, LCPI6_0
-; CHECK-NEON-NEXT: vmov d19, r0, r1
-; CHECK-NEON-NEXT: vmov d18, r2, r3
-; CHECK-NEON-NEXT: vcmp.f64 d19, d17
+; CHECK-NEON-NEXT: vmov d18, r0, r1
+; CHECK-NEON-NEXT: vmov d19, r2, r3
+; CHECK-NEON-NEXT: vcmp.f64 d18, d17
; CHECK-NEON-NEXT: vmov.f64 d16, #-1.000000e+00
; CHECK-NEON-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEON-NEXT: it mi
-; CHECK-NEON-NEXT: vmovmi.f64 d18, d16
-; CHECK-NEON-NEXT: vmov r0, r1, d18
+; CHECK-NEON-NEXT: vmovmi.f64 d19, d16
+; CHECK-NEON-NEXT: vmov r0, r1, d19
; CHECK-NEON-NEXT: bx lr
; CHECK-NEON-NEXT: .p2align 3
; CHECK-NEON-NEXT: @ %bb.1:
diff --git a/llvm/test/CodeGen/Thumb2/mve-fmas.ll b/llvm/test/CodeGen/Thumb2/mve-fmas.ll
index 8016b940b8d514..377440e1bbc939 100644
--- a/llvm/test/CodeGen/Thumb2/mve-fmas.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-fmas.ll
@@ -896,17 +896,17 @@ define arm_aapcs_vfpcc <4 x float> @vfma32_v1_pred(<4 x float> %src1, <4 x float
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
-; CHECK-MVE-NEXT: vmov.f32 s14, s0
-; CHECK-MVE-NEXT: vmov.f32 s12, s1
-; CHECK-MVE-NEXT: vmla.f32 s14, s4, s8
-; CHECK-MVE-NEXT: vmov.f32 s4, s3
-; CHECK-MVE-NEXT: vmov.f32 s8, s2
-; CHECK-MVE-NEXT: vmla.f32 s12, s5, s9
-; CHECK-MVE-NEXT: vmla.f32 s4, s7, s11
-; CHECK-MVE-NEXT: vmla.f32 s8, s6, s10
+; CHECK-MVE-NEXT: vmov.f32 s14, s2
+; CHECK-MVE-NEXT: vmov.f32 s12, s3
+; CHECK-MVE-NEXT: vmla.f32 s14, s6, s10
+; CHECK-MVE-NEXT: vmov.f32 s10, s1
+; CHECK-MVE-NEXT: vmla.f32 s12, s7, s11
+; CHECK-MVE-NEXT: vmla.f32 s10, s5, s9
+; CHECK-MVE-NEXT: vmov.f32 s9, s0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
+; CHECK-MVE-NEXT: vmla.f32 s9, s4, s8
; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
@@ -914,13 +914,13 @@ define arm_aapcs_vfpcc <4 x float> @vfma32_v1_pred(<4 x float> %src1, <4 x float
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4
+; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s12
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s8
+; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s14
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s12
+; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s14
+; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s9
; CHECK-MVE-NEXT: bx lr
entry:
%0 = fmul <4 x float> %src2, %src3
@@ -949,17 +949,17 @@ define arm_aapcs_vfpcc <4 x float> @vfma32_v2_pred(<4 x float> %src1, <4 x float
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
-; CHECK-MVE-NEXT: vmov.f32 s14, s0
-; CHECK-MVE-NEXT: vmov.f32 s12, s1
-; CHECK-MVE-NEXT: vmla.f32 s14, s4, s8
-; CHECK-MVE-NEXT: vmov.f32 s4, s3
-; CHECK-MVE-NEXT: vmov.f32 s8, s2
-; CHECK-MVE-NEXT: vmla.f32 s12, s5, s9
-; CHECK-MVE-NEXT: vmla.f32 s4, s7, s11
-; CHECK-MVE-NEXT: vmla.f32 s8, s6, s10
+; CHECK-MVE-NEXT: vmov.f32 s14, s2
+; CHECK-MVE-NEXT: vmov.f32 s12, s3
+; CHECK-MVE-NEXT: vmla.f32 s14, s6, s10
+; CHECK-MVE-NEXT: vmov.f32 s10, s1
+; CHECK-MVE-NEXT: vmla.f32 s12, s7, s11
+; CHECK-MVE-NEXT: vmla.f32 s10, s5, s9
+; CHECK-MVE-NEXT: vmov.f32 s9, s0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
+; CHECK-MVE-NEXT: vmla.f32 s9, s4, s8
; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
@@ -967,13 +967,13 @@ define arm_aapcs_vfpcc <4 x float> @vfma32_v2_pred(<4 x float> %src1, <4 x float
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4
+; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s12
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s8
+; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s14
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s12
+; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s14
+; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s9
; CHECK-MVE-NEXT: bx lr
entry:
%0 = fmul <4 x float> %src2, %src3
@@ -1002,17 +1002,17 @@ define arm_aapcs_vfpcc <4 x float> @vfms32_pred(<4 x float> %src1, <4 x float> %
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
-; CHECK-MVE-NEXT: vmov.f32 s14, s0
-; CHECK-MVE-NEXT: vmov.f32 s12, s1
-; CHECK-MVE-NEXT: vmls.f32 s14, s4, s8
-; CHECK-MVE-NEXT: vmov.f32 s4, s3
-; CHECK-MVE-NEXT: vmov.f32 s8, s2
-; CHECK-MVE-NEXT: vmls.f32 s12, s5, s9
-; CHECK-MVE-NEXT: vmls.f32 s4, s7, s11
-; CHECK-MVE-NEXT: vmls.f32 s8, s6, s10
+; CHECK-MVE-NEXT: vmov.f32 s14, s2
+; CHECK-MVE-NEXT: vmov.f32 s12, s3
+; CHECK-MVE-NEXT: vmls.f32 s14, s6, s10
+; CHECK-MVE-NEXT: vmov.f32 s10, s1
+; CHECK-MVE-NEXT: vmls.f32 s12, s7, s11
+; CHECK-MVE-NEXT: vmls.f32 s10, s5, s9
+; CHECK-MVE-NEXT: vmov.f32 s9, s0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
+; CHECK-MVE-NEXT: vmls.f32 s9, s4, s8
; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
@@ -1020,13 +1020,13 @@ define arm_aapcs_vfpcc <4 x float> @vfms32_pred(<4 x float> %src1, <4 x float> %
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4
+; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s12
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s8
+; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s14
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s12
+; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s14
+; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s9
; CHECK-MVE-NEXT: bx lr
entry:
%0 = fmul <4 x float> %src2, %src3
@@ -1058,14 +1058,14 @@ define arm_aapcs_vfpcc <4 x float> @vfmar32_pred(<4 x float> %src1, <4 x float>
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
-; CHECK-MVE-NEXT: vmov.f32 s12, s0
-; CHECK-MVE-NEXT: vmov.f32 s14, s2
-; CHECK-MVE-NEXT: vmov.f32 s10, s1
-; CHECK-MVE-NEXT: vmla.f32 s12, s4, s8
-; CHECK-MVE-NEXT: vmov.f32 s4, s3
-; CHECK-MVE-NEXT: vmla.f32 s14, s6, s8
-; CHECK-MVE-NEXT: vmla.f32 s10, s5, s8
-; CHECK-MVE-NEXT: vmla.f32 s4, s7, s8
+; CHECK-MVE-NEXT: vmov.f32 s10, s3
+; CHECK-MVE-NEXT: vmov.f32 s12, s2
+; CHECK-MVE-NEXT: vmov.f32 s14, s1
+; CHECK-MVE-NEXT: vmov.f32 s9, s0
+; CHECK-MVE-NEXT: vmla.f32 s10, s7, s8
+; CHECK-MVE-NEXT: vmla.f32 s12, s6, s8
+; CHECK-MVE-NEXT: vmla.f32 s14, s5, s8
+; CHECK-MVE-NEXT: vmla.f32 s9, s4, s8
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
@@ -1076,13 +1076,13 @@ define arm_aapcs_vfpcc <4 x float> @vfmar32_pred(<4 x float> %src1, <4 x float>
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4
+; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s10
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s14
+; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s12
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10
+; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s14
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s12
+; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s9
; CHECK-MVE-NEXT: bx lr
entry:
%i = insertelement <4 x float> undef, float %src3, i32 0
@@ -1115,13 +1115,13 @@ define arm_aapcs_vfpcc <4 x float> @vfmas32_pred(<4 x float> %src1, <4 x float>
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
-; CHECK-MVE-NEXT: vmov.f32 s12, s8
; CHECK-MVE-NEXT: vmov.f32 s10, s8
-; CHECK-MVE-NEXT: vmla.f32 s12, s0, s4
-; CHECK-MVE-NEXT: vmov.f32 s4, s8
-; CHECK-MVE-NEXT: vmla.f32 s8, s2, s6
-; CHECK-MVE-NEXT: vmla.f32 s10, s1, s5
-; CHECK-MVE-NEXT: vmla.f32 s4, s3, s7
+; CHECK-MVE-NEXT: vmov.f32 s12, s8
+; CHECK-MVE-NEXT: vmov.f32 s14, s8
+; CHECK-MVE-NEXT: vmla.f32 s8, s0, s4
+; CHECK-MVE-NEXT: vmla.f32 s10, s3, s7
+; CHECK-MVE-NEXT: vmla.f32 s12, s2, s6
+; CHECK-MVE-NEXT: vmla.f32 s14, s1, s5
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
@@ -1132,13 +1132,13 @@ define arm_aapcs_vfpcc <4 x float> @vfmas32_pred(<4 x float> %src1, <4 x float>
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: cmp r2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s4
+; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s10
; CHECK-MVE-NEXT: cmp r3, #0
-; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s8
+; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s12
; CHECK-MVE-NEXT: cmp r0, #0
-; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10
+; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s14
; CHECK-MVE-NEXT: cmp r1, #0
-; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s12
+; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s8
; CHECK-MVE-NEXT: bx lr
entry:
%i = insertelement <4 x float> undef, float %src3, i32 0
diff --git a/llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll b/llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
index 81b6a6940a7d6b..75b6cb3e1272bc 100644
--- a/llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
@@ -42,54 +42,36 @@ define arm_aapcs_vfpcc <2 x i32> @test_signed_v2f32_v2i32(<2 x float> %f) {
; CHECK-NEXT: vldr s20, .LCPI1_1
; CHECK-NEXT: vcmp.f32 s17, s18
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt.w r4, #-1
; CHECK-NEXT: movlt.w r5, #-2147483648
; CHECK-NEXT: vcmp.f32 s17, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itt gt
; CHECK-NEXT: mvngt r5, #-2147483648
+; CHECK-NEXT: movgt r4, #0
; CHECK-NEXT: vcmp.f32 s17, s17
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
+; CHECK-NEXT: itt vs
+; CHECK-NEXT: movvs r4, #0
; CHECK-NEXT: movvs r5, #0
; CHECK-NEXT: bl __aeabi_f2lz
; CHECK-NEXT: vcmp.f32 s16, s18
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
; CHECK-NEXT: movlt.w r0, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s16
-; CHECK-NEXT: it gt
-; CHECK-NEXT: mvngt r0, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s18
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r4, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s17
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r4, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s18
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r4, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
; CHECK-NEXT: movlt.w r1, #-1
; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itt gt
; CHECK-NEXT: movgt r1, #0
+; CHECK-NEXT: mvngt r0, #-2147483648
; CHECK-NEXT: vcmp.f32 s16, s16
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
+; CHECK-NEXT: itt vs
+; CHECK-NEXT: movvs r0, #0
; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
; CHECK-NEXT: vmov q0[3], q0[1], r1, r4
; CHECK-NEXT: vpop {d8, d9, d10}
; CHECK-NEXT: pop {r4, r5, r7, pc}
@@ -1275,54 +1257,36 @@ define arm_aapcs_vfpcc <2 x i32> @test_signed_v2f16_v2i32(<2 x half> %f) {
; CHECK-NEXT: mov r4, r1
; CHECK-NEXT: vcmp.f32 s18, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt.w r4, #-1
; CHECK-NEXT: movlt.w r5, #-2147483648
; CHECK-NEXT: vcmp.f32 s18, s22
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itt gt
; CHECK-NEXT: mvngt r5, #-2147483648
+; CHECK-NEXT: movgt r4, #0
; CHECK-NEXT: vcmp.f32 s18, s18
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
+; CHECK-NEXT: itt vs
+; CHECK-NEXT: movvs r4, #0
; CHECK-NEXT: movvs r5, #0
; CHECK-NEXT: bl __aeabi_f2lz
; CHECK-NEXT: vcmp.f32 s16, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s22
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
; CHECK-NEXT: movlt.w r0, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s16
-; CHECK-NEXT: it gt
-; CHECK-NEXT: mvngt r0, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s22
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r4, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s18
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r4, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r4, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
; CHECK-NEXT: movlt.w r1, #-1
; CHECK-NEXT: vcmp.f32 s16, s22
-; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itt gt
; CHECK-NEXT: movgt r1, #0
+; CHECK-NEXT: mvngt r0, #-2147483648
; CHECK-NEXT: vcmp.f32 s16, s16
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
+; CHECK-NEXT: itt vs
+; CHECK-NEXT: movvs r0, #0
; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
; CHECK-NEXT: vmov q0[3], q0[1], r1, r4
; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r4, r5, r7, pc}
@@ -1568,9 +1532,9 @@ define arm_aapcs_vfpcc <4 x i8> @test_signed_v4f32_v4i8(<4 x float> %f) {
; CHECK-MVE-NEXT: vmaxnm.f32 s12, s2, s4
; CHECK-MVE-NEXT: vmaxnm.f32 s10, s0, s4
; CHECK-MVE-NEXT: vminnm.f32 s12, s12, s6
-; CHECK-MVE-NEXT: vmaxnm.f32 s8, s1, s4
+; CHECK-MVE-NEXT: vmaxnm.f32 s8, s3, s4
; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s6
-; CHECK-MVE-NEXT: vmaxnm.f32 s4, s3, s4
+; CHECK-MVE-NEXT: vmaxnm.f32 s4, s1, s4
; CHECK-MVE-NEXT: vcvt.s32.f32 s12, s12
; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s6
; CHECK-MVE-NEXT: vminnm.f32 s4, s4, s6
@@ -1588,10 +1552,10 @@ define arm_aapcs_vfpcc <4 x i8> @test_signed_v4f32_v4i8(<4 x float> %f) {
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov r2, s4
+; CHECK-MVE-NEXT: vmov r2, s8
; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
-; CHECK-MVE-NEXT: vmov r3, s8
+; CHECK-MVE-NEXT: vmov r3, s4
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -1627,9 +1591,9 @@ define arm_aapcs_vfpcc <4 x i13> @test_signed_v4f32_v4i13(<4 x float> %f) {
; CHECK-MVE-NEXT: vmaxnm.f32 s12, s2, s4
; CHECK-MVE-NEXT: vmaxnm.f32 s10, s0, s4
; CHECK-MVE-NEXT: vminnm.f32 s12, s12, s6
-; CHECK-MVE-NEXT: vmaxnm.f32 s8, s1, s4
+; CHECK-MVE-NEXT: vmaxnm.f32 s8, s3, s4
; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s6
-; CHECK-MVE-NEXT: vmaxnm.f32 s4, s3, s4
+; CHECK-MVE-NEXT: vmaxnm.f32 s4, s1, s4
; CHECK-MVE-NEXT: vcvt.s32.f32 s12, s12
; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s6
; CHECK-MVE-NEXT: vminnm.f32 s4, s4, s6
@@ -1647,10 +1611,10 @@ define arm_aapcs_vfpcc <4 x i13> @test_signed_v4f32_v4i13(<4 x float> %f) {
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov r2, s4
+; CHECK-MVE-NEXT: vmov r2, s8
; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
-; CHECK-MVE-NEXT: vmov r3, s8
+; CHECK-MVE-NEXT: vmov r3, s4
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -1686,9 +1650,9 @@ define arm_aapcs_vfpcc <4 x i16> @test_signed_v4f32_v4i16(<4 x float> %f) {
; CHECK-MVE-NEXT: vmaxnm.f32 s12, s2, s4
; CHECK-MVE-NEXT: vmaxnm.f32 s10, s0, s4
; CHECK-MVE-NEXT: vminnm.f32 s12, s12, s6
-; CHECK-MVE-NEXT: vmaxnm.f32 s8, s1, s4
+; CHECK-MVE-NEXT: vmaxnm.f32 s8, s3, s4
; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s6
-; CHECK-MVE-NEXT: vmaxnm.f32 s4, s3, s4
+; CHECK-MVE-NEXT: vmaxnm.f32 s4, s1, s4
; CHECK-MVE-NEXT: vcvt.s32.f32 s12, s12
; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s6
; CHECK-MVE-NEXT: vminnm.f32 s4, s4, s6
@@ -1706,10 +1670,10 @@ define arm_aapcs_vfpcc <4 x i16> @test_signed_v4f32_v4i16(<4 x float> %f) {
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov r2, s4
+; CHECK-MVE-NEXT: vmov r2, s8
; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
-; CHECK-MVE-NEXT: vmov r3, s8
+; CHECK-MVE-NEXT: vmov r3, s4
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -1743,9 +1707,9 @@ define arm_aapcs_vfpcc <4 x i19> @test_signed_v4f32_v4i19(<4 x float> %f) {
; CHECK-MVE-NEXT: vmaxnm.f32 s12, s2, s4
; CHECK-MVE-NEXT: vmaxnm.f32 s10, s0, s4
; CHECK-MVE-NEXT: vminnm.f32 s12, s12, s6
-; CHECK-MVE-NEXT: vmaxnm.f32 s8, s1, s4
+; CHECK-MVE-NEXT: vmaxnm.f32 s8, s3, s4
; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s6
-; CHECK-MVE-NEXT: vmaxnm.f32 s4, s3, s4
+; CHECK-MVE-NEXT: vmaxnm.f32 s4, s1, s4
; CHECK-MVE-NEXT: vcvt.s32.f32 s12, s12
; CHECK-MVE-NEXT: vminnm.f32 s8, s8, s6
; CHECK-MVE-NEXT: vminnm.f32 s4, s4, s6
@@ -1763,10 +1727,10 @@ define arm_aapcs_vfpcc <4 x i19> @test_signed_v4f32_v4i19(<4 x float> %f) {
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov r2, s4
+; CHECK-MVE-NEXT: vmov r2, s8
; CHECK-MVE-NEXT: vcmp.f32 s1, s1
; CHECK-MVE-NEXT: vmov q0[2], q0[0], r1, r0
-; CHECK-MVE-NEXT: vmov r3, s8
+; CHECK-MVE-NEXT: vmov r3, s4
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
@@ -1821,146 +1785,122 @@ define arm_aapcs_vfpcc <4 x i32> @test_signed_v4f32_v4i32_duplicate(<4 x float>
define arm_aapcs_vfpcc <4 x i50> @test_signed_v4f32_v4i50(<4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i50:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
-; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r11, lr}
+; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r11, lr}
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: mov r8, r0
+; CHECK-NEXT: vmov r0, s19
+; CHECK-NEXT: bl __aeabi_f2lz
+; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: vmov r0, s18
+; CHECK-NEXT: mov r7, r1
; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: mov r9, r0
-; CHECK-NEXT: vmov r0, s19
-; CHECK-NEXT: vldr s20, .LCPI28_0
+; CHECK-NEXT: mov r6, r0
+; CHECK-NEXT: vmov r0, s17
; CHECK-NEXT: mov r5, r1
-; CHECK-NEXT: vmov r6, s16
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt lt
-; CHECK-NEXT: movlt r5, #0
-; CHECK-NEXT: movtlt r5, #65534
; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: vldr s22, .LCPI28_1
-; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: mov r9, r0
+; CHECK-NEXT: vmov r0, s16
+; CHECK-NEXT: vldr s22, .LCPI28_0
+; CHECK-NEXT: mov r11, r1
+; CHECK-NEXT: vldr s20, .LCPI28_1
+; CHECK-NEXT: vcmp.f32 s17, s22
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: mov r7, r1
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: vcmp.f32 s18, s22
; CHECK-NEXT: itt lt
-; CHECK-NEXT: movlt r7, #0
-; CHECK-NEXT: movtlt r7, #65534
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt gt
-; CHECK-NEXT: movwgt r5, #65535
-; CHECK-NEXT: movtgt r5, #1
-; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: mov r10, r1
+; CHECK-NEXT: movwlt r11, #0
+; CHECK-NEXT: movtlt r11, #65534
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s22
+; CHECK-NEXT: vcmp.f32 s17, s20
; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: movlt.w r9, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s22
-; CHECK-NEXT: itt gt
-; CHECK-NEXT: movwgt r7, #65535
-; CHECK-NEXT: movtgt r7, #1
+; CHECK-NEXT: vcmp.f32 s17, s17
+; CHECK-NEXT: ittt gt
+; CHECK-NEXT: movwgt r11, #65535
+; CHECK-NEXT: movtgt r11, #1
+; CHECK-NEXT: movgt.w r9, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s16, s16
+; CHECK-NEXT: vcmp.f32 s18, s22
+; CHECK-NEXT: itt vs
+; CHECK-NEXT: movvs.w r9, #0
+; CHECK-NEXT: movvs.w r11, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str.w r0, [r8]
-; CHECK-NEXT: vmov r0, s17
-; CHECK-NEXT: vcmp.f32 s19, s20
+; CHECK-NEXT: vcmp.f32 s18, s20
+; CHECK-NEXT: ittt lt
+; CHECK-NEXT: movlt r5, #0
+; CHECK-NEXT: movtlt r5, #65534
+; CHECK-NEXT: movlt r6, #0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vcmp.f32 s18, s18
+; CHECK-NEXT: ittt gt
+; CHECK-NEXT: movwgt r5, #65535
+; CHECK-NEXT: movtgt r5, #1
+; CHECK-NEXT: movgt.w r6, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s19, s22
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt vs
+; CHECK-NEXT: movvs r6, #0
+; CHECK-NEXT: movvs r5, #0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: ittt lt
+; CHECK-NEXT: movlt r7, #0
+; CHECK-NEXT: movtlt r7, #65534
; CHECK-NEXT: movlt r4, #0
+; CHECK-NEXT: vcmp.f32 s19, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s19
-; CHECK-NEXT: it gt
+; CHECK-NEXT: ittt gt
+; CHECK-NEXT: movwgt r7, #65535
+; CHECK-NEXT: movtgt r7, #1
; CHECK-NEXT: movgt.w r4, #-1
+; CHECK-NEXT: vcmp.f32 s19, s19
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s20
; CHECK-NEXT: itt vs
; CHECK-NEXT: movvs r4, #0
; CHECK-NEXT: movvs r7, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r9, #0
-; CHECK-NEXT: vcmp.f32 s18, s22
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r9, #-1
-; CHECK-NEXT: vcmp.f32 s18, s18
-; CHECK-NEXT: mov r1, r7
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt vs
-; CHECK-NEXT: movvs.w r9, #0
-; CHECK-NEXT: movvs r5, #0
-; CHECK-NEXT: bfc r1, #18, #14
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: bfc r5, #18, #14
-; CHECK-NEXT: mov r6, r9
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: lsll r4, r1, #22
-; CHECK-NEXT: lsrl r6, r5, #28
-; CHECK-NEXT: itt lt
-; CHECK-NEXT: movwlt r10, #0
-; CHECK-NEXT: movtlt r10, #65534
-; CHECK-NEXT: vcmp.f32 s16, s22
-; CHECK-NEXT: orrs r1, r5
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt gt
-; CHECK-NEXT: movwgt r10, #65535
-; CHECK-NEXT: movtgt r10, #1
-; CHECK-NEXT: str.w r1, [r8, #20]
; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: orr.w r2, r6, r4
+; CHECK-NEXT: vcmp.f32 s16, s22
+; CHECK-NEXT: bfc r5, #18, #14
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt lt
+; CHECK-NEXT: ittt lt
; CHECK-NEXT: movlt r1, #0
; CHECK-NEXT: movtlt r1, #65534
-; CHECK-NEXT: vcmp.f32 s17, s22
+; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: vcmp.f32 s16, s20
+; CHECK-NEXT: mov r2, r6
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt gt
+; CHECK-NEXT: ittt gt
; CHECK-NEXT: movwgt r1, #65535
; CHECK-NEXT: movtgt r1, #1
-; CHECK-NEXT: str.w r2, [r8, #16]
-; CHECK-NEXT: lsrs r2, r7, #10
-; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: strb.w r2, [r8, #24]
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s17, s22
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s17, s17
+; CHECK-NEXT: vcmp.f32 s16, s16
+; CHECK-NEXT: lsrl r2, r5, #28
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt vs
+; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: movvs r1, #0
-; CHECK-NEXT: bfc r1, #18, #14
-; CHECK-NEXT: mov r2, r0
-; CHECK-NEXT: lsrl r2, r1, #14
-; CHECK-NEXT: vcmp.f32 s16, s16
-; CHECK-NEXT: orr.w r1, r1, r9, lsl #4
+; CHECK-NEXT: str.w r0, [r8]
+; CHECK-NEXT: lsrs r0, r7, #10
+; CHECK-NEXT: bfc r7, #18, #14
+; CHECK-NEXT: bfc r11, #18, #14
+; CHECK-NEXT: lsll r4, r7, #22
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: strd r2, r1, [r8, #8]
+; CHECK-NEXT: orr.w r3, r5, r7
+; CHECK-NEXT: str.w r3, [r8, #20]
+; CHECK-NEXT: orr.w r2, r2, r4
+; CHECK-NEXT: str.w r2, [r8, #16]
+; CHECK-NEXT: strb.w r0, [r8, #24]
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: lsrl r0, r11, #14
+; CHECK-NEXT: orr.w r2, r11, r6, lsl #4
+; CHECK-NEXT: strd r0, r2, [r8, #8]
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs.w r10, #0
-; CHECK-NEXT: bfc r10, #18, #14
-; CHECK-NEXT: orr.w r0, r10, r0, lsl #18
+; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: bfc r1, #18, #14
+; CHECK-NEXT: orr.w r0, r1, r9, lsl #18
; CHECK-NEXT: str.w r0, [r8, #4]
; CHECK-NEXT: vpop {d8, d9, d10, d11}
-; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}
+; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r11, pc}
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI28_0:
@@ -1974,131 +1914,98 @@ define arm_aapcs_vfpcc <4 x i50> @test_signed_v4f32_v4i50(<4 x float> %f) {
define arm_aapcs_vfpcc <4 x i64> @test_signed_v4f32_v4i64(<4 x float> %f) {
; CHECK-LABEL: test_signed_v4f32_v4i64:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, lr}
-; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, lr}
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+; CHECK-NEXT: .pad #4
+; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vmov r0, s19
; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: mov r10, r0
+; CHECK-NEXT: mov r11, r0
; CHECK-NEXT: vmov r0, s18
; CHECK-NEXT: vldr s22, .LCPI29_0
-; CHECK-NEXT: mov r9, r1
+; CHECK-NEXT: mov r10, r1
; CHECK-NEXT: vldr s20, .LCPI29_1
-; CHECK-NEXT: vmov r8, s16
+; CHECK-NEXT: vmov r9, s17
; CHECK-NEXT: vcmp.f32 s19, s22
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r10, #0
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt.w r10, #-2147483648
+; CHECK-NEXT: movlt.w r11, #0
; CHECK-NEXT: vcmp.f32 s19, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r10, #-1
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: movgt.w r11, #-1
+; CHECK-NEXT: mvngt r10, #-2147483648
; CHECK-NEXT: vcmp.f32 s19, s19
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vmov r4, s17
-; CHECK-NEXT: it vs
+; CHECK-NEXT: vmov r8, s16
+; CHECK-NEXT: itt vs
; CHECK-NEXT: movvs.w r10, #0
+; CHECK-NEXT: movvs.w r11, #0
; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: vcmp.f32 s18, s22
; CHECK-NEXT: mov r7, r0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r7, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s18
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r7, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s22
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r7, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r9, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s19
-; CHECK-NEXT: it gt
-; CHECK-NEXT: mvngt r9, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: mov r6, r1
; CHECK-NEXT: vcmp.f32 s18, s22
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs.w r9, #0
+; CHECK-NEXT: mov r6, r1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt r7, #0
; CHECK-NEXT: movlt.w r6, #-2147483648
; CHECK-NEXT: vcmp.f32 s18, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: mov r0, r4
-; CHECK-NEXT: it gt
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: itt gt
; CHECK-NEXT: mvngt r6, #-2147483648
+; CHECK-NEXT: movgt.w r7, #-1
; CHECK-NEXT: vcmp.f32 s18, s18
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
+; CHECK-NEXT: itt vs
+; CHECK-NEXT: movvs r7, #0
; CHECK-NEXT: movvs r6, #0
; CHECK-NEXT: bl __aeabi_f2lz
; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: vcmp.f32 s17, s22
+; CHECK-NEXT: mov r4, r1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt.w r4, #-2147483648
; CHECK-NEXT: movlt r5, #0
; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: mov r0, r8
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: itt gt
; CHECK-NEXT: movgt.w r5, #-1
+; CHECK-NEXT: mvngt r4, #-2147483648
; CHECK-NEXT: vcmp.f32 s17, s17
-; CHECK-NEXT: mov r4, r1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
+; CHECK-NEXT: itt vs
+; CHECK-NEXT: movvs r4, #0
; CHECK-NEXT: movvs r5, #0
; CHECK-NEXT: bl __aeabi_f2lz
; CHECK-NEXT: vcmp.f32 s16, s22
-; CHECK-NEXT: vmov q1[2], q1[0], r7, r10
+; CHECK-NEXT: vmov q1[2], q1[0], r7, r11
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s16
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s22
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r4, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s17
-; CHECK-NEXT: it gt
-; CHECK-NEXT: mvngt r4, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s22
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r4, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
; CHECK-NEXT: movlt.w r1, #-2147483648
; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
+; CHECK-NEXT: vmov q1[3], q1[1], r6, r10
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itt gt
; CHECK-NEXT: mvngt r1, #-2147483648
+; CHECK-NEXT: movgt.w r0, #-1
; CHECK-NEXT: vcmp.f32 s16, s16
-; CHECK-NEXT: vmov q1[3], q1[1], r6, r9
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
+; CHECK-NEXT: itt vs
+; CHECK-NEXT: movvs r0, #0
; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
; CHECK-NEXT: vmov q0[3], q0[1], r1, r4
; CHECK-NEXT: vpop {d8, d9, d10, d11}
-; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}
+; CHECK-NEXT: add sp, #4
+; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI29_0:
@@ -2118,568 +2025,370 @@ define arm_aapcs_vfpcc <4 x i100> @test_signed_v4f32_v4i100(<4 x float> %f) {
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-NEXT: .pad #8
+; CHECK-NEXT: sub sp, #8
; CHECK-NEXT: vmov q4, q0
-; CHECK-NEXT: mov r9, r0
-; CHECK-NEXT: vmov r0, s18
+; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vmov r0, s17
; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: mov r10, r3
-; CHECK-NEXT: vmov r3, s16
+; CHECK-NEXT: mov r7, r0
+; CHECK-NEXT: vmov r0, s18
; CHECK-NEXT: vldr s22, .LCPI30_0
-; CHECK-NEXT: vmov r7, s17
+; CHECK-NEXT: mov r11, r1
; CHECK-NEXT: vldr s20, .LCPI30_1
-; CHECK-NEXT: vmov r4, s19
-; CHECK-NEXT: vcmp.f32 s18, s22
+; CHECK-NEXT: mov r10, r2
+; CHECK-NEXT: vcmp.f32 s17, s22
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: mvnlt r3, #7
+; CHECK-NEXT: movlt.w r10, #0
+; CHECK-NEXT: movlt r7, #0
+; CHECK-NEXT: movlt.w r11, #0
+; CHECK-NEXT: vcmp.f32 s17, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s18
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt.w r11, #-1
+; CHECK-NEXT: movgt.w r7, #-1
+; CHECK-NEXT: movgt.w r10, #-1
+; CHECK-NEXT: movgt r3, #7
+; CHECK-NEXT: vcmp.f32 s17, s17
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s22
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: str.w r2, [r9, #33]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s18
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s22
+; CHECK-NEXT: movvs r3, #0
+; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: itt vs
+; CHECK-NEXT: movvs.w r10, #0
+; CHECK-NEXT: movvs r7, #0
+; CHECK-NEXT: str r7, [sp] @ 4-byte Spill
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: movvs.w r11, #0
+; CHECK-NEXT: bl __fixsfti
+; CHECK-NEXT: vcmp.f32 s18, s22
+; CHECK-NEXT: mov r5, r3
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str.w r1, [r9, #29]
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: movlt r1, #0
; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: mvnlt r5, #7
; CHECK-NEXT: vcmp.f32 s18, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt r5, #7
; CHECK-NEXT: movgt.w r0, #-1
+; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: movgt.w r2, #-1
; CHECK-NEXT: vcmp.f32 s18, s18
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs
+; CHECK-NEXT: movvs r2, #0
+; CHECK-NEXT: str.w r2, [r4, #33]
+; CHECK-NEXT: it vs
+; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: str.w r1, [r4, #29]
+; CHECK-NEXT: vmov r1, s19
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str.w r0, [r9, #25]
-; CHECK-NEXT: mov r0, r3
+; CHECK-NEXT: str.w r0, [r4, #25]
+; CHECK-NEXT: it vs
+; CHECK-NEXT: movvs r5, #0
+; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vcmp.f32 s16, s22
-; CHECK-NEXT: mov r11, r3
+; CHECK-NEXT: mov r7, r0
+; CHECK-NEXT: vmov r0, s16
+; CHECK-NEXT: vcmp.f32 s19, s22
+; CHECK-NEXT: mov r9, r1
+; CHECK-NEXT: mov r6, r2
+; CHECK-NEXT: mov r8, r3
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: mvnlt r8, #7
+; CHECK-NEXT: movlt r6, #0
+; CHECK-NEXT: movlt.w r9, #0
+; CHECK-NEXT: movlt r7, #0
+; CHECK-NEXT: vcmp.f32 s19, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s16
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt.w r7, #-1
+; CHECK-NEXT: movgt.w r9, #-1
+; CHECK-NEXT: movgt.w r6, #-1
+; CHECK-NEXT: movgt.w r8, #7
+; CHECK-NEXT: vcmp.f32 s19, s19
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: itttt vs
+; CHECK-NEXT: movvs.w r8, #0
+; CHECK-NEXT: movvs r6, #0
+; CHECK-NEXT: movvs.w r9, #0
+; CHECK-NEXT: movvs r7, #0
+; CHECK-NEXT: bl __fixsfti
; CHECK-NEXT: vcmp.f32 s16, s22
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: str.w r2, [r9, #8]
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s16
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s22
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str.w r1, [r9, #4]
-; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: mvnlt r3, #7
; CHECK-NEXT: vcmp.f32 s16, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt r3, #7
; CHECK-NEXT: movgt.w r0, #-1
+; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: movgt.w r2, #-1
; CHECK-NEXT: vcmp.f32 s16, s16
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs
+; CHECK-NEXT: movvs r2, #0
+; CHECK-NEXT: str r2, [r4, #8]
+; CHECK-NEXT: it vs
+; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: str r1, [r4, #4]
+; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str.w r0, [r9]
-; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: str r0, [r4]
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: lsrl r0, r9, #28
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: orr.w r1, r9, r6, lsl #4
+; CHECK-NEXT: str.w r1, [r4, #45]
+; CHECK-NEXT: and r1, r8, #15
+; CHECK-NEXT: str.w r0, [r4, #41]
+; CHECK-NEXT: and r0, r5, #15
+; CHECK-NEXT: lsrl r6, r1, #28
+; CHECK-NEXT: strb.w r6, [r4, #49]
+; CHECK-NEXT: orr.w r0, r0, r7, lsl #4
+; CHECK-NEXT: str.w r0, [r4, #37]
+; CHECK-NEXT: ldr r2, [sp] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: lsrl r0, r11, #28
+; CHECK-NEXT: orr.w r1, r11, r10, lsl #4
+; CHECK-NEXT: strd r0, r1, [r4, #16]
+; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: and r1, r0, #15
+; CHECK-NEXT: lsrl r10, r1, #28
+; CHECK-NEXT: strb.w r10, [r4, #24]
+; CHECK-NEXT: it vs
+; CHECK-NEXT: movvs r3, #0
+; CHECK-NEXT: and r0, r3, #15
+; CHECK-NEXT: orr.w r0, r0, r2, lsl #4
+; CHECK-NEXT: str r0, [r4, #12]
+; CHECK-NEXT: add sp, #8
+; CHECK-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-NEXT: add sp, #4
+; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+; CHECK-NEXT: .p2align 2
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI30_0:
+; CHECK-NEXT: .long 0xf1000000 @ float -6.338253E+29
+; CHECK-NEXT: .LCPI30_1:
+; CHECK-NEXT: .long 0x70ffffff @ float 6.33825262E+29
+ %x = call <4 x i100> @llvm.fptosi.sat.v4f32.v4i100(<4 x float> %f)
+ ret <4 x i100> %x
+}
+
+define arm_aapcs_vfpcc <4 x i128> @test_signed_v4f32_v4i128(<4 x float> %f) {
+; CHECK-LABEL: test_signed_v4f32_v4i128:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-NEXT: .pad #4
+; CHECK-NEXT: sub sp, #4
+; CHECK-NEXT: .vsave {d8, d9, d10, d11}
+; CHECK-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-NEXT: vmov q4, q0
+; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vmov r0, s19
; CHECK-NEXT: bl __fixsfti
+; CHECK-NEXT: mov r5, r0
+; CHECK-NEXT: vmov r0, s18
+; CHECK-NEXT: vldr s22, .LCPI31_0
+; CHECK-NEXT: vmov r7, s16
+; CHECK-NEXT: vldr s20, .LCPI31_1
+; CHECK-NEXT: vmov r6, s17
; CHECK-NEXT: vcmp.f32 s19, s22
-; CHECK-NEXT: mov r6, r0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r6, #0
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt.w r3, #-2147483648
+; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r5, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s19, s19
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r6, #-1
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt.w r5, #-1
+; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: mvngt r3, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s22
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r6, #0
+; CHECK-NEXT: movvs r3, #0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: ittt vs
+; CHECK-NEXT: movvs r2, #0
+; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: movvs r5, #0
+; CHECK-NEXT: strd r5, r1, [r4, #48]
+; CHECK-NEXT: strd r2, r3, [r4, #56]
+; CHECK-NEXT: bl __fixsfti
+; CHECK-NEXT: vcmp.f32 s18, s22
+; CHECK-NEXT: add.w r12, r4, #32
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: mvnlt r10, #7
; CHECK-NEXT: vcmp.f32 s18, s20
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt.w r3, #-2147483648
+; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r10, #7
; CHECK-NEXT: vcmp.f32 s18, s18
-; CHECK-NEXT: mov r5, r1
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt.w r0, #-1
+; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: mvngt r3, #-2147483648
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: ittt vs
+; CHECK-NEXT: movvs r3, #0
+; CHECK-NEXT: movvs r2, #0
+; CHECK-NEXT: movvs r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs.w r10, #0
-; CHECK-NEXT: and r0, r10, #15
-; CHECK-NEXT: mov r4, r2
-; CHECK-NEXT: orr.w r0, r0, r6, lsl #4
-; CHECK-NEXT: str.w r0, [r9, #37]
-; CHECK-NEXT: mov r0, r7
-; CHECK-NEXT: mov r8, r3
+; CHECK-NEXT: movvs r0, #0
+; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
+; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: bl __fixsfti
; CHECK-NEXT: vcmp.f32 s17, s22
+; CHECK-NEXT: add.w r12, r4, #16
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt.w r3, #-2147483648
+; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: movlt r1, #0
; CHECK-NEXT: movlt r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s17, s17
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itttt gt
; CHECK-NEXT: movgt.w r0, #-1
+; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: mvngt r3, #-2147483648
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: ittt vs
+; CHECK-NEXT: movvs r3, #0
+; CHECK-NEXT: movvs r2, #0
+; CHECK-NEXT: movvs r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s22
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r0, #0
+; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: bl __fixsfti
+; CHECK-NEXT: vcmp.f32 s16, s22
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: mvnlt r11, #7
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s16
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r11, #7
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s22
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs.w r11, #0
-; CHECK-NEXT: and r7, r11, #15
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: orr.w r7, r7, r0, lsl #4
-; CHECK-NEXT: str.w r7, [r9, #12]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r5, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s19
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r5, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s22
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r5, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r4, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s19
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r4, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: lsrl r6, r5, #28
-; CHECK-NEXT: vcmp.f32 s19, s22
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r4, #0
-; CHECK-NEXT: orr.w r7, r5, r4, lsl #4
-; CHECK-NEXT: str.w r7, [r9, #45]
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str.w r6, [r9, #41]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: mvnlt r8, #7
-; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r8, #7
-; CHECK-NEXT: vcmp.f32 s19, s19
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs.w r8, #0
-; CHECK-NEXT: and r5, r8, #15
-; CHECK-NEXT: vcmp.f32 s17, s22
-; CHECK-NEXT: lsrl r4, r5, #28
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: strb.w r4, [r9, #49]
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt.w r3, #-2147483648
+; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s17
-; CHECK-NEXT: it gt
+; CHECK-NEXT: vcmp.f32 s16, s16
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt.w r0, #-1
; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s22
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: lsrl r0, r1, #28
-; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vcmp.f32 s17, s17
+; CHECK-NEXT: mvngt r3, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
+; CHECK-NEXT: ittt vs
+; CHECK-NEXT: movvs r3, #0
; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: orr.w r1, r1, r2, lsl #4
-; CHECK-NEXT: vcmp.f32 s17, s22
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: strd r0, r1, [r9, #16]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: mvnlt r3, #7
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r3, #7
-; CHECK-NEXT: vcmp.f32 s17, s17
+; CHECK-NEXT: movvs r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r3, #0
-; CHECK-NEXT: and r1, r3, #15
-; CHECK-NEXT: lsrl r2, r1, #28
-; CHECK-NEXT: strb.w r2, [r9, #24]
+; CHECK-NEXT: movvs r0, #0
+; CHECK-NEXT: stm r4!, {r0, r1, r2, r3}
; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: add sp, #4
-; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI30_0:
-; CHECK-NEXT: .long 0xf1000000 @ float -6.338253E+29
-; CHECK-NEXT: .LCPI30_1:
-; CHECK-NEXT: .long 0x70ffffff @ float 6.33825262E+29
- %x = call <4 x i100> @llvm.fptosi.sat.v4f32.v4i100(<4 x float> %f)
- ret <4 x i100> %x
+; CHECK-NEXT: .LCPI31_0:
+; CHECK-NEXT: .long 0xff000000 @ float -1.70141183E+38
+; CHECK-NEXT: .LCPI31_1:
+; CHECK-NEXT: .long 0x7effffff @ float 1.70141173E+38
+ %x = call <4 x i128> @llvm.fptosi.sat.v4f32.v4i128(<4 x float> %f)
+ ret <4 x i128> %x
}
-define arm_aapcs_vfpcc <4 x i128> @test_signed_v4f32_v4i128(<4 x float> %f) {
-; CHECK-LABEL: test_signed_v4f32_v4i128:
+;
+; 2-Vector double to signed integer -- result size variation
+;
+
+declare <2 x i1> @llvm.fptosi.sat.v2f64.v2i1 (<2 x double>)
+declare <2 x i8> @llvm.fptosi.sat.v2f64.v2i8 (<2 x double>)
+declare <2 x i13> @llvm.fptosi.sat.v2f64.v2i13 (<2 x double>)
+declare <2 x i16> @llvm.fptosi.sat.v2f64.v2i16 (<2 x double>)
+declare <2 x i19> @llvm.fptosi.sat.v2f64.v2i19 (<2 x double>)
+declare <2 x i50> @llvm.fptosi.sat.v2f64.v2i50 (<2 x double>)
+declare <2 x i64> @llvm.fptosi.sat.v2f64.v2i64 (<2 x double>)
+declare <2 x i100> @llvm.fptosi.sat.v2f64.v2i100(<2 x double>)
+declare <2 x i128> @llvm.fptosi.sat.v2f64.v2i128(<2 x double>)
+
+define arm_aapcs_vfpcc <2 x i1> @test_signed_v2f64_v2i1(<2 x double> %f) {
+; CHECK-LABEL: test_signed_v2f64_v2i1:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
-; CHECK-NEXT: push {r4, r5, r6, r7, lr}
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4
-; CHECK-NEXT: .vsave {d8, d9, d10, d11}
-; CHECK-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-NEXT: .vsave {d8, d9}
+; CHECK-NEXT: vpush {d8, d9}
+; CHECK-NEXT: .pad #24
+; CHECK-NEXT: sub sp, #24
; CHECK-NEXT: vmov q4, q0
-; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vmov r0, s19
-; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vmov r5, s18
-; CHECK-NEXT: vldr s22, .LCPI31_0
-; CHECK-NEXT: vldr s20, .LCPI31_1
-; CHECK-NEXT: vmov r7, s16
-; CHECK-NEXT: vcmp.f32 s19, s22
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r3, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s19
-; CHECK-NEXT: it gt
-; CHECK-NEXT: mvngt r3, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s22
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r3, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: str r3, [r4, #60]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s19
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s22
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: str r2, [r4, #56]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s19
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s22
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #52]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s19, s19
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str r0, [r4, #48]
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: vmov r6, s17
-; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vcmp.f32 s18, s22
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r3, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s18
-; CHECK-NEXT: it gt
-; CHECK-NEXT: mvngt r3, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s22
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r3, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: str r3, [r4, #44]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s18
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s22
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: str r2, [r4, #40]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s18
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s22
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #36]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s18, s18
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str r0, [r4, #32]
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vcmp.f32 s17, s22
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r3, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s17
-; CHECK-NEXT: it gt
-; CHECK-NEXT: mvngt r3, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s22
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r3, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: str r3, [r4, #28]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s17
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s22
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: str r2, [r4, #24]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s17
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s22
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #20]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s17, s17
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str r0, [r4, #16]
-; CHECK-NEXT: mov r0, r7
-; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vcmp.f32 s16, s22
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r3, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s16
-; CHECK-NEXT: it gt
-; CHECK-NEXT: mvngt r3, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s22
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r3, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: str r3, [r4, #12]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s16
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s22
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: str r2, [r4, #8]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s16
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s22
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #4]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s16, s16
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str r0, [r4]
-; CHECK-NEXT: vpop {d8, d9, d10, d11}
-; CHECK-NEXT: add sp, #4
-; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI31_0:
-; CHECK-NEXT: .long 0xff000000 @ float -1.70141183E+38
-; CHECK-NEXT: .LCPI31_1:
-; CHECK-NEXT: .long 0x7effffff @ float 1.70141173E+38
- %x = call <4 x i128> @llvm.fptosi.sat.v4f32.v4i128(<4 x float> %f)
- ret <4 x i128> %x
-}
-
-;
-; 2-Vector double to signed integer -- result size variation
-;
-
-declare <2 x i1> @llvm.fptosi.sat.v2f64.v2i1 (<2 x double>)
-declare <2 x i8> @llvm.fptosi.sat.v2f64.v2i8 (<2 x double>)
-declare <2 x i13> @llvm.fptosi.sat.v2f64.v2i13 (<2 x double>)
-declare <2 x i16> @llvm.fptosi.sat.v2f64.v2i16 (<2 x double>)
-declare <2 x i19> @llvm.fptosi.sat.v2f64.v2i19 (<2 x double>)
-declare <2 x i50> @llvm.fptosi.sat.v2f64.v2i50 (<2 x double>)
-declare <2 x i64> @llvm.fptosi.sat.v2f64.v2i64 (<2 x double>)
-declare <2 x i100> @llvm.fptosi.sat.v2f64.v2i100(<2 x double>)
-declare <2 x i128> @llvm.fptosi.sat.v2f64.v2i128(<2 x double>)
-
-define arm_aapcs_vfpcc <2 x i1> @test_signed_v2f64_v2i1(<2 x double> %f) {
-; CHECK-LABEL: test_signed_v2f64_v2i1:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEXT: .pad #4
-; CHECK-NEXT: sub sp, #4
-; CHECK-NEXT: .vsave {d8, d9}
-; CHECK-NEXT: vpush {d8, d9}
-; CHECK-NEXT: .pad #24
-; CHECK-NEXT: sub sp, #24
-; CHECK-NEXT: vmov q4, q0
-; CHECK-NEXT: vldr d0, .LCPI32_0
-; CHECK-NEXT: vmov r8, r7, d8
-; CHECK-NEXT: str r0, [sp, #20] @ 4-byte Spill
-; CHECK-NEXT: vmov r2, r3, d0
-; CHECK-NEXT: mov r0, r8
-; CHECK-NEXT: mov r1, r7
-; CHECK-NEXT: strd r2, r3, [sp, #12] @ 8-byte Folded Spill
-; CHECK-NEXT: bl __aeabi_dcmpgt
-; CHECK-NEXT: vldr d0, .LCPI32_1
-; CHECK-NEXT: mov r9, r0
-; CHECK-NEXT: mov r0, r8
-; CHECK-NEXT: mov r1, r7
-; CHECK-NEXT: vmov r2, r3, d0
-; CHECK-NEXT: strd r2, r3, [sp, #4] @ 8-byte Folded Spill
-; CHECK-NEXT: bl __aeabi_dcmpge
-; CHECK-NEXT: mov r10, r0
-; CHECK-NEXT: mov r0, r8
-; CHECK-NEXT: mov r1, r7
-; CHECK-NEXT: bl __aeabi_d2iz
-; CHECK-NEXT: mov r11, r0
-; CHECK-NEXT: cmp.w r10, #0
-; CHECK-NEXT: it eq
-; CHECK-NEXT: moveq.w r11, #-1
-; CHECK-NEXT: mov r0, r8
-; CHECK-NEXT: mov r1, r7
-; CHECK-NEXT: mov r2, r8
-; CHECK-NEXT: mov r3, r7
-; CHECK-NEXT: cmp.w r9, #0
-; CHECK-NEXT: vmov r6, r5, d9
-; CHECK-NEXT: it ne
-; CHECK-NEXT: movne.w r11, #0
-; CHECK-NEXT: bl __aeabi_dcmpun
-; CHECK-NEXT: cmp r0, #0
-; CHECK-NEXT: it ne
-; CHECK-NEXT: movne.w r11, #0
-; CHECK-NEXT: and r0, r11, #1
-; CHECK-NEXT: ldrd r2, r3, [sp, #12] @ 8-byte Folded Reload
-; CHECK-NEXT: rsbs r0, r0, #0
-; CHECK-NEXT: movs r4, #0
-; CHECK-NEXT: bfi r4, r0, #0, #1
+; CHECK-NEXT: vldr d0, .LCPI32_0
+; CHECK-NEXT: vmov r8, r7, d8
+; CHECK-NEXT: str r0, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT: vmov r2, r3, d0
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mov r1, r7
+; CHECK-NEXT: strd r2, r3, [sp, #12] @ 8-byte Folded Spill
+; CHECK-NEXT: bl __aeabi_dcmpgt
+; CHECK-NEXT: vldr d0, .LCPI32_1
+; CHECK-NEXT: mov r9, r0
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mov r1, r7
+; CHECK-NEXT: vmov r2, r3, d0
+; CHECK-NEXT: strd r2, r3, [sp, #4] @ 8-byte Folded Spill
+; CHECK-NEXT: bl __aeabi_dcmpge
+; CHECK-NEXT: mov r10, r0
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mov r1, r7
+; CHECK-NEXT: bl __aeabi_d2iz
+; CHECK-NEXT: mov r11, r0
+; CHECK-NEXT: cmp.w r10, #0
+; CHECK-NEXT: it eq
+; CHECK-NEXT: moveq.w r11, #-1
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: mov r1, r7
+; CHECK-NEXT: mov r2, r8
+; CHECK-NEXT: mov r3, r7
+; CHECK-NEXT: cmp.w r9, #0
+; CHECK-NEXT: vmov r6, r5, d9
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r11, #0
+; CHECK-NEXT: bl __aeabi_dcmpun
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: it ne
+; CHECK-NEXT: movne.w r11, #0
+; CHECK-NEXT: and r0, r11, #1
+; CHECK-NEXT: ldrd r2, r3, [sp, #12] @ 8-byte Folded Reload
+; CHECK-NEXT: rsbs r0, r0, #0
+; CHECK-NEXT: movs r4, #0
+; CHECK-NEXT: bfi r4, r0, #0, #1
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: mov r1, r5
; CHECK-NEXT: bl __aeabi_dcmpgt
@@ -4244,33 +3953,37 @@ define arm_aapcs_vfpcc <8 x i1> @test_signed_v8f16_v8i1(<8 x half> %f) {
; CHECK-NEXT: .vsave {d8}
; CHECK-NEXT: vpush {d8}
; CHECK-NEXT: vcvtb.f32.f16 s15, s0
-; CHECK-NEXT: vmov.f32 s5, #-1.000000e+00
-; CHECK-NEXT: vldr s7, .LCPI42_0
-; CHECK-NEXT: vmaxnm.f32 s16, s15, s5
+; CHECK-NEXT: vmov.f32 s7, #-1.000000e+00
+; CHECK-NEXT: vldr s5, .LCPI42_0
+; CHECK-NEXT: vmaxnm.f32 s16, s15, s7
; CHECK-NEXT: vcvtt.f32.f16 s12, s2
; CHECK-NEXT: vcvtt.f32.f16 s9, s1
-; CHECK-NEXT: vminnm.f32 s16, s16, s7
+; CHECK-NEXT: vminnm.f32 s16, s16, s5
; CHECK-NEXT: vcvtt.f32.f16 s4, s3
; CHECK-NEXT: vcvt.s32.f32 s16, s16
; CHECK-NEXT: vcvtb.f32.f16 s8, s3
; CHECK-NEXT: vcvtb.f32.f16 s2, s2
; CHECK-NEXT: vcvtb.f32.f16 s1, s1
; CHECK-NEXT: vcvtt.f32.f16 s0, s0
-; CHECK-NEXT: vmaxnm.f32 s6, s4, s5
-; CHECK-NEXT: vmaxnm.f32 s10, s8, s5
-; CHECK-NEXT: vmaxnm.f32 s14, s12, s5
-; CHECK-NEXT: vmaxnm.f32 s3, s2, s5
-; CHECK-NEXT: vmaxnm.f32 s11, s9, s5
-; CHECK-NEXT: vmaxnm.f32 s13, s1, s5
-; CHECK-NEXT: vmaxnm.f32 s5, s0, s5
-; CHECK-NEXT: vminnm.f32 s5, s5, s7
-; CHECK-NEXT: vminnm.f32 s13, s13, s7
-; CHECK-NEXT: vcvt.s32.f32 s5, s5
-; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: vmaxnm.f32 s6, s4, s7
+; CHECK-NEXT: vmaxnm.f32 s10, s8, s7
+; CHECK-NEXT: vmaxnm.f32 s14, s12, s7
+; CHECK-NEXT: vmaxnm.f32 s3, s2, s7
+; CHECK-NEXT: vmaxnm.f32 s11, s9, s7
+; CHECK-NEXT: vmaxnm.f32 s13, s1, s7
+; CHECK-NEXT: vmaxnm.f32 s7, s0, s7
+; CHECK-NEXT: vminnm.f32 s6, s6, s5
+; CHECK-NEXT: vminnm.f32 s10, s10, s5
+; CHECK-NEXT: vminnm.f32 s14, s14, s5
+; CHECK-NEXT: vminnm.f32 s3, s3, s5
+; CHECK-NEXT: vminnm.f32 s11, s11, s5
+; CHECK-NEXT: vminnm.f32 s13, s13, s5
+; CHECK-NEXT: vminnm.f32 s5, s7, s5
; CHECK-NEXT: vcmp.f32 s15, s15
-; CHECK-NEXT: vminnm.f32 s11, s11, s7
-; CHECK-NEXT: vmov r2, s16
+; CHECK-NEXT: vcvt.s32.f32 s5, s5
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vmov r2, s16
+; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r2, #0
; CHECK-NEXT: vcvt.s32.f32 s13, s13
@@ -4280,60 +3993,56 @@ define arm_aapcs_vfpcc <8 x i1> @test_signed_v8f16_v8i1(<8 x half> %f) {
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: bfi r1, r2, #0, #1
; CHECK-NEXT: vcvt.s32.f32 s11, s11
+; CHECK-NEXT: vcmp.f32 s1, s1
; CHECK-NEXT: vmov r2, s5
-; CHECK-NEXT: vminnm.f32 s3, s3, s7
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: vcmp.f32 s1, s1
-; CHECK-NEXT: and r2, r2, #1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: rsb.w r2, r2, #0
+; CHECK-NEXT: and r2, r2, #1
; CHECK-NEXT: vcvt.s32.f32 s3, s3
+; CHECK-NEXT: rsb.w r2, r2, #0
+; CHECK-NEXT: vcmp.f32 s9, s9
; CHECK-NEXT: bfi r1, r2, #1, #1
; CHECK-NEXT: vmov r2, s13
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: vminnm.f32 s14, s14, s7
-; CHECK-NEXT: and r2, r2, #1
-; CHECK-NEXT: vcmp.f32 s9, s9
-; CHECK-NEXT: rsbs r2, r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: and r2, r2, #1
+; CHECK-NEXT: vcvt.s32.f32 s14, s14
+; CHECK-NEXT: rsb.w r2, r2, #0
+; CHECK-NEXT: vcmp.f32 s2, s2
; CHECK-NEXT: bfi r1, r2, #2, #1
; CHECK-NEXT: vmov r2, s11
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: vcvt.s32.f32 s14, s14
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: and r2, r2, #1
-; CHECK-NEXT: vminnm.f32 s10, s10, s7
-; CHECK-NEXT: rsbs r2, r2, #0
-; CHECK-NEXT: vcmp.f32 s2, s2
+; CHECK-NEXT: vcvt.s32.f32 s10, s10
+; CHECK-NEXT: rsb.w r2, r2, #0
+; CHECK-NEXT: vcmp.f32 s12, s12
; CHECK-NEXT: bfi r1, r2, #3, #1
; CHECK-NEXT: vmov r2, s3
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: vcvt.s32.f32 s10, s10
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: and r2, r2, #1
-; CHECK-NEXT: rsbs r2, r2, #0
-; CHECK-NEXT: vminnm.f32 s6, s6, s7
+; CHECK-NEXT: vcvt.s32.f32 s6, s6
+; CHECK-NEXT: rsb.w r2, r2, #0
+; CHECK-NEXT: vcmp.f32 s8, s8
; CHECK-NEXT: bfi r1, r2, #4, #1
-; CHECK-NEXT: vcmp.f32 s12, s12
; CHECK-NEXT: vmov r2, s14
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: vcvt.s32.f32 s6, s6
-; CHECK-NEXT: and r2, r2, #1
-; CHECK-NEXT: vcmp.f32 s8, s8
-; CHECK-NEXT: rsbs r2, r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: and r2, r2, #1
+; CHECK-NEXT: vcmp.f32 s4, s4
+; CHECK-NEXT: rsb.w r2, r2, #0
; CHECK-NEXT: bfi r1, r2, #5, #1
; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: vcmp.f32 s4, s4
-; CHECK-NEXT: and r2, r2, #1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: and r2, r2, #1
; CHECK-NEXT: rsb.w r2, r2, #0
; CHECK-NEXT: bfi r1, r2, #6, #1
; CHECK-NEXT: vmov r2, s6
@@ -4360,40 +4069,40 @@ define arm_aapcs_vfpcc <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
; CHECK-MVE-NEXT: .vsave {d8}
; CHECK-MVE-NEXT: vpush {d8}
-; CHECK-MVE-NEXT: vldr s8, .LCPI43_1
+; CHECK-MVE-NEXT: vldr s6, .LCPI43_1
; CHECK-MVE-NEXT: vcvtt.f32.f16 s13, s3
; CHECK-MVE-NEXT: vcvtb.f32.f16 s3, s3
-; CHECK-MVE-NEXT: vldr s6, .LCPI43_0
-; CHECK-MVE-NEXT: vmaxnm.f32 s16, s3, s8
-; CHECK-MVE-NEXT: vcvtt.f32.f16 s4, s0
-; CHECK-MVE-NEXT: vcvtt.f32.f16 s12, s1
+; CHECK-MVE-NEXT: vldr s4, .LCPI43_0
+; CHECK-MVE-NEXT: vmaxnm.f32 s16, s3, s6
; CHECK-MVE-NEXT: vcvtt.f32.f16 s7, s2
-; CHECK-MVE-NEXT: vmaxnm.f32 s15, s13, s8
-; CHECK-MVE-NEXT: vminnm.f32 s16, s16, s6
-; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT: vcvtb.f32.f16 s1, s1
+; CHECK-MVE-NEXT: vmaxnm.f32 s15, s13, s6
+; CHECK-MVE-NEXT: vminnm.f32 s16, s16, s4
; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2
-; CHECK-MVE-NEXT: vmaxnm.f32 s10, s4, s8
-; CHECK-MVE-NEXT: vmaxnm.f32 s14, s12, s8
-; CHECK-MVE-NEXT: vmaxnm.f32 s5, s0, s8
-; CHECK-MVE-NEXT: vmaxnm.f32 s9, s7, s8
-; CHECK-MVE-NEXT: vmaxnm.f32 s11, s1, s8
-; CHECK-MVE-NEXT: vminnm.f32 s15, s15, s6
+; CHECK-MVE-NEXT: vminnm.f32 s15, s15, s4
+; CHECK-MVE-NEXT: vmaxnm.f32 s11, s2, s6
; CHECK-MVE-NEXT: vcvt.s32.f32 s16, s16
-; CHECK-MVE-NEXT: vmaxnm.f32 s8, s2, s8
-; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s6
-; CHECK-MVE-NEXT: vminnm.f32 s14, s14, s6
-; CHECK-MVE-NEXT: vminnm.f32 s5, s5, s6
-; CHECK-MVE-NEXT: vminnm.f32 s9, s9, s6
-; CHECK-MVE-NEXT: vminnm.f32 s11, s11, s6
-; CHECK-MVE-NEXT: vminnm.f32 s6, s8, s6
+; CHECK-MVE-NEXT: vcvtt.f32.f16 s12, s1
+; CHECK-MVE-NEXT: vmaxnm.f32 s9, s7, s6
+; CHECK-MVE-NEXT: vminnm.f32 s11, s11, s4
+; CHECK-MVE-NEXT: vcvtb.f32.f16 s1, s1
; CHECK-MVE-NEXT: vcvt.s32.f32 s15, s15
-; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s6
-; CHECK-MVE-NEXT: vcvt.s32.f32 s9, s9
+; CHECK-MVE-NEXT: vcvtb.f32.f16 s8, s0
+; CHECK-MVE-NEXT: vmaxnm.f32 s5, s1, s6
+; CHECK-MVE-NEXT: vminnm.f32 s9, s9, s4
; CHECK-MVE-NEXT: vcvt.s32.f32 s11, s11
-; CHECK-MVE-NEXT: vcvt.s32.f32 s14, s14
+; CHECK-MVE-NEXT: vmaxnm.f32 s10, s8, s6
+; CHECK-MVE-NEXT: vmaxnm.f32 s14, s12, s6
+; CHECK-MVE-NEXT: vminnm.f32 s5, s5, s4
+; CHECK-MVE-NEXT: vcvt.s32.f32 s9, s9
+; CHECK-MVE-NEXT: vcvtt.f32.f16 s0, s0
+; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s4
+; CHECK-MVE-NEXT: vminnm.f32 s14, s14, s4
; CHECK-MVE-NEXT: vcvt.s32.f32 s5, s5
+; CHECK-MVE-NEXT: vmaxnm.f32 s6, s0, s6
+; CHECK-MVE-NEXT: vminnm.f32 s4, s6, s4
; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s10
+; CHECK-MVE-NEXT: vcvt.s32.f32 s14, s14
+; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r12, s16
@@ -4406,7 +4115,7 @@ define arm_aapcs_vfpcc <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs.w lr, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov r2, s6
+; CHECK-MVE-NEXT: vmov r2, s11
; CHECK-MVE-NEXT: vcmp.f32 s7, s7
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #0
@@ -4416,22 +4125,22 @@ define arm_aapcs_vfpcc <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r3, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov r0, s11
+; CHECK-MVE-NEXT: vmov r0, s5
; CHECK-MVE-NEXT: vcmp.f32 s12, s12
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s14
-; CHECK-MVE-NEXT: vmov r4, s5
+; CHECK-MVE-NEXT: vmov r4, s10
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s0, s0
+; CHECK-MVE-NEXT: vcmp.f32 s8, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r4, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-MVE-NEXT: vmov.16 q0[0], r4
-; CHECK-MVE-NEXT: vmov r5, s10
+; CHECK-MVE-NEXT: vmov r5, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r5, #0
@@ -4468,40 +4177,40 @@ define arm_aapcs_vfpcc <8 x i13> @test_signed_v8f16_v8i13(<8 x half> %f) {
; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
; CHECK-MVE-NEXT: .vsave {d8}
; CHECK-MVE-NEXT: vpush {d8}
-; CHECK-MVE-NEXT: vldr s8, .LCPI44_1
+; CHECK-MVE-NEXT: vldr s6, .LCPI44_1
; CHECK-MVE-NEXT: vcvtt.f32.f16 s13, s3
; CHECK-MVE-NEXT: vcvtb.f32.f16 s3, s3
-; CHECK-MVE-NEXT: vldr s6, .LCPI44_0
-; CHECK-MVE-NEXT: vmaxnm.f32 s16, s3, s8
-; CHECK-MVE-NEXT: vcvtt.f32.f16 s4, s0
-; CHECK-MVE-NEXT: vcvtt.f32.f16 s12, s1
+; CHECK-MVE-NEXT: vldr s4, .LCPI44_0
+; CHECK-MVE-NEXT: vmaxnm.f32 s16, s3, s6
; CHECK-MVE-NEXT: vcvtt.f32.f16 s7, s2
-; CHECK-MVE-NEXT: vmaxnm.f32 s15, s13, s8
-; CHECK-MVE-NEXT: vminnm.f32 s16, s16, s6
-; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT: vcvtb.f32.f16 s1, s1
+; CHECK-MVE-NEXT: vmaxnm.f32 s15, s13, s6
+; CHECK-MVE-NEXT: vminnm.f32 s16, s16, s4
; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2
-; CHECK-MVE-NEXT: vmaxnm.f32 s10, s4, s8
-; CHECK-MVE-NEXT: vmaxnm.f32 s14, s12, s8
-; CHECK-MVE-NEXT: vmaxnm.f32 s5, s0, s8
-; CHECK-MVE-NEXT: vmaxnm.f32 s9, s7, s8
-; CHECK-MVE-NEXT: vmaxnm.f32 s11, s1, s8
-; CHECK-MVE-NEXT: vminnm.f32 s15, s15, s6
+; CHECK-MVE-NEXT: vminnm.f32 s15, s15, s4
+; CHECK-MVE-NEXT: vmaxnm.f32 s11, s2, s6
; CHECK-MVE-NEXT: vcvt.s32.f32 s16, s16
-; CHECK-MVE-NEXT: vmaxnm.f32 s8, s2, s8
-; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s6
-; CHECK-MVE-NEXT: vminnm.f32 s14, s14, s6
-; CHECK-MVE-NEXT: vminnm.f32 s5, s5, s6
-; CHECK-MVE-NEXT: vminnm.f32 s9, s9, s6
-; CHECK-MVE-NEXT: vminnm.f32 s11, s11, s6
-; CHECK-MVE-NEXT: vminnm.f32 s6, s8, s6
+; CHECK-MVE-NEXT: vcvtt.f32.f16 s12, s1
+; CHECK-MVE-NEXT: vmaxnm.f32 s9, s7, s6
+; CHECK-MVE-NEXT: vminnm.f32 s11, s11, s4
+; CHECK-MVE-NEXT: vcvtb.f32.f16 s1, s1
; CHECK-MVE-NEXT: vcvt.s32.f32 s15, s15
-; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s6
-; CHECK-MVE-NEXT: vcvt.s32.f32 s9, s9
+; CHECK-MVE-NEXT: vcvtb.f32.f16 s8, s0
+; CHECK-MVE-NEXT: vmaxnm.f32 s5, s1, s6
+; CHECK-MVE-NEXT: vminnm.f32 s9, s9, s4
; CHECK-MVE-NEXT: vcvt.s32.f32 s11, s11
-; CHECK-MVE-NEXT: vcvt.s32.f32 s14, s14
+; CHECK-MVE-NEXT: vmaxnm.f32 s10, s8, s6
+; CHECK-MVE-NEXT: vmaxnm.f32 s14, s12, s6
+; CHECK-MVE-NEXT: vminnm.f32 s5, s5, s4
+; CHECK-MVE-NEXT: vcvt.s32.f32 s9, s9
+; CHECK-MVE-NEXT: vcvtt.f32.f16 s0, s0
+; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s4
+; CHECK-MVE-NEXT: vminnm.f32 s14, s14, s4
; CHECK-MVE-NEXT: vcvt.s32.f32 s5, s5
+; CHECK-MVE-NEXT: vmaxnm.f32 s6, s0, s6
+; CHECK-MVE-NEXT: vminnm.f32 s4, s6, s4
; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s10
+; CHECK-MVE-NEXT: vcvt.s32.f32 s14, s14
+; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
; CHECK-MVE-NEXT: vcmp.f32 s3, s3
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r12, s16
@@ -4514,7 +4223,7 @@ define arm_aapcs_vfpcc <8 x i13> @test_signed_v8f16_v8i13(<8 x half> %f) {
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs.w lr, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov r2, s6
+; CHECK-MVE-NEXT: vmov r2, s11
; CHECK-MVE-NEXT: vcmp.f32 s7, s7
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #0
@@ -4524,22 +4233,22 @@ define arm_aapcs_vfpcc <8 x i13> @test_signed_v8f16_v8i13(<8 x half> %f) {
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r3, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov r0, s11
+; CHECK-MVE-NEXT: vmov r0, s5
; CHECK-MVE-NEXT: vcmp.f32 s12, s12
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s14
-; CHECK-MVE-NEXT: vmov r4, s5
+; CHECK-MVE-NEXT: vmov r4, s10
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s0, s0
+; CHECK-MVE-NEXT: vcmp.f32 s8, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r4, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s4
+; CHECK-MVE-NEXT: vcmp.f32 s0, s0
; CHECK-MVE-NEXT: vmov.16 q0[0], r4
-; CHECK-MVE-NEXT: vmov r5, s10
+; CHECK-MVE-NEXT: vmov r5, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r5, #0
@@ -4578,838 +4287,273 @@ define arm_aapcs_vfpcc <8 x i16> @test_signed_v8f16_v8i16(<8 x half> %f) {
; CHECK-MVE-NEXT: push {r4, r5, r7, lr}
; CHECK-MVE-NEXT: .vsave {d8}
; CHECK-MVE-NEXT: vpush {d8}
-; CHECK-MVE-NEXT: vldr s8, .LCPI45_1
+; CHECK-MVE-NEXT: vldr s6, .LCPI45_1
; CHECK-MVE-NEXT: vcvtt.f32.f16 s13, s3
-; CHECK-MVE-NEXT: vcvtb.f32.f16 s3, s3
-; CHECK-MVE-NEXT: vldr s6, .LCPI45_0
-; CHECK-MVE-NEXT: vmaxnm.f32 s16, s3, s8
-; CHECK-MVE-NEXT: vcvtt.f32.f16 s4, s0
-; CHECK-MVE-NEXT: vcvtt.f32.f16 s12, s1
-; CHECK-MVE-NEXT: vcvtt.f32.f16 s7, s2
-; CHECK-MVE-NEXT: vmaxnm.f32 s15, s13, s8
-; CHECK-MVE-NEXT: vminnm.f32 s16, s16, s6
-; CHECK-MVE-NEXT: vcvtb.f32.f16 s0, s0
-; CHECK-MVE-NEXT: vcvtb.f32.f16 s1, s1
-; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2
-; CHECK-MVE-NEXT: vmaxnm.f32 s10, s4, s8
-; CHECK-MVE-NEXT: vmaxnm.f32 s14, s12, s8
-; CHECK-MVE-NEXT: vmaxnm.f32 s5, s0, s8
-; CHECK-MVE-NEXT: vmaxnm.f32 s9, s7, s8
-; CHECK-MVE-NEXT: vmaxnm.f32 s11, s1, s8
-; CHECK-MVE-NEXT: vminnm.f32 s15, s15, s6
-; CHECK-MVE-NEXT: vcvt.s32.f32 s16, s16
-; CHECK-MVE-NEXT: vmaxnm.f32 s8, s2, s8
-; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s6
-; CHECK-MVE-NEXT: vminnm.f32 s14, s14, s6
-; CHECK-MVE-NEXT: vminnm.f32 s5, s5, s6
-; CHECK-MVE-NEXT: vminnm.f32 s9, s9, s6
-; CHECK-MVE-NEXT: vminnm.f32 s11, s11, s6
-; CHECK-MVE-NEXT: vminnm.f32 s6, s8, s6
-; CHECK-MVE-NEXT: vcvt.s32.f32 s15, s15
-; CHECK-MVE-NEXT: vcvt.s32.f32 s6, s6
-; CHECK-MVE-NEXT: vcvt.s32.f32 s9, s9
-; CHECK-MVE-NEXT: vcvt.s32.f32 s11, s11
-; CHECK-MVE-NEXT: vcvt.s32.f32 s14, s14
-; CHECK-MVE-NEXT: vcvt.s32.f32 s5, s5
-; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s10
-; CHECK-MVE-NEXT: vcmp.f32 s3, s3
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov r12, s16
-; CHECK-MVE-NEXT: vcmp.f32 s13, s13
-; CHECK-MVE-NEXT: it vs
-; CHECK-MVE-NEXT: movvs.w r12, #0
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov lr, s15
-; CHECK-MVE-NEXT: vcmp.f32 s2, s2
-; CHECK-MVE-NEXT: it vs
-; CHECK-MVE-NEXT: movvs.w lr, #0
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov r2, s6
-; CHECK-MVE-NEXT: vcmp.f32 s7, s7
-; CHECK-MVE-NEXT: it vs
-; CHECK-MVE-NEXT: movvs r2, #0
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov r3, s9
-; CHECK-MVE-NEXT: vcmp.f32 s1, s1
-; CHECK-MVE-NEXT: it vs
-; CHECK-MVE-NEXT: movvs r3, #0
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov r0, s11
-; CHECK-MVE-NEXT: vcmp.f32 s12, s12
-; CHECK-MVE-NEXT: it vs
-; CHECK-MVE-NEXT: movvs r0, #0
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmov r1, s14
-; CHECK-MVE-NEXT: vmov r4, s5
-; CHECK-MVE-NEXT: it vs
-; CHECK-MVE-NEXT: movvs r1, #0
-; CHECK-MVE-NEXT: vcmp.f32 s0, s0
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: it vs
-; CHECK-MVE-NEXT: movvs r4, #0
-; CHECK-MVE-NEXT: vcmp.f32 s4, s4
-; CHECK-MVE-NEXT: vmov.16 q0[0], r4
-; CHECK-MVE-NEXT: vmov r5, s10
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: it vs
-; CHECK-MVE-NEXT: movvs r5, #0
-; CHECK-MVE-NEXT: vmov.16 q0[1], r5
-; CHECK-MVE-NEXT: vmov.16 q0[2], r0
-; CHECK-MVE-NEXT: vmov.16 q0[3], r1
-; CHECK-MVE-NEXT: vmov.16 q0[4], r2
-; CHECK-MVE-NEXT: vmov.16 q0[5], r3
-; CHECK-MVE-NEXT: vmov.16 q0[6], r12
-; CHECK-MVE-NEXT: vmov.16 q0[7], lr
-; CHECK-MVE-NEXT: vpop {d8}
-; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
-; CHECK-MVE-NEXT: .p2align 2
-; CHECK-MVE-NEXT: @ %bb.1:
-; CHECK-MVE-NEXT: .LCPI45_0:
-; CHECK-MVE-NEXT: .long 0x46fffe00 @ float 32767
-; CHECK-MVE-NEXT: .LCPI45_1:
-; CHECK-MVE-NEXT: .long 0xc7000000 @ float -32768
-;
-; CHECK-MVEFP-LABEL: test_signed_v8f16_v8i16:
-; CHECK-MVEFP: @ %bb.0:
-; CHECK-MVEFP-NEXT: vcvt.s16.f16 q0, q0
-; CHECK-MVEFP-NEXT: bx lr
- %x = call <8 x i16> @llvm.fptosi.sat.v8f16.v8i16(<8 x half> %f)
- ret <8 x i16> %x
-}
-
-define arm_aapcs_vfpcc <8 x i19> @test_signed_v8f16_v8i19(<8 x half> %f) {
-; CHECK-LABEL: test_signed_v8f16_v8i19:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r7, r9, r11, lr}
-; CHECK-NEXT: push.w {r4, r5, r7, r9, r11, lr}
-; CHECK-NEXT: vldr s4, .LCPI46_0
-; CHECK-NEXT: vcvtb.f32.f16 s8, s1
-; CHECK-NEXT: vcvtt.f32.f16 s12, s1
-; CHECK-NEXT: vcvtt.f32.f16 s1, s0
-; CHECK-NEXT: vldr s6, .LCPI46_1
-; CHECK-NEXT: vmaxnm.f32 s5, s1, s4
-; CHECK-NEXT: vcvtb.f32.f16 s0, s0
-; CHECK-NEXT: vmaxnm.f32 s14, s12, s4
-; CHECK-NEXT: vminnm.f32 s5, s5, s6
-; CHECK-NEXT: vmaxnm.f32 s7, s0, s4
-; CHECK-NEXT: vminnm.f32 s7, s7, s6
-; CHECK-NEXT: vcvt.s32.f32 s5, s5
-; CHECK-NEXT: vcvt.s32.f32 s7, s7
-; CHECK-NEXT: vminnm.f32 s14, s14, s6
-; CHECK-NEXT: vcvt.s32.f32 s14, s14
-; CHECK-NEXT: vmaxnm.f32 s10, s8, s4
-; CHECK-NEXT: vminnm.f32 s10, s10, s6
-; CHECK-NEXT: vcmp.f32 s1, s1
-; CHECK-NEXT: vcvt.s32.f32 s10, s10
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s0, s0
-; CHECK-NEXT: mov.w r7, #0
-; CHECK-NEXT: vcvtb.f32.f16 s0, s2
-; CHECK-NEXT: mov.w r9, #0
-; CHECK-NEXT: vmov r2, s5
-; CHECK-NEXT: mov.w r5, #0
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: vmov r1, s7
-; CHECK-NEXT: bfc r2, #19, #13
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r1, #0
-; CHECK-NEXT: vcmp.f32 s12, s12
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s8, s8
-; CHECK-NEXT: lsll r2, r7, #19
-; CHECK-NEXT: bfc r1, #19, #13
-; CHECK-NEXT: vmov r12, s14
-; CHECK-NEXT: vmaxnm.f32 s8, s0, s4
-; CHECK-NEXT: orr.w r1, r1, r2
-; CHECK-NEXT: str r1, [r0]
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs.w r12, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s0, s0
-; CHECK-NEXT: vcvtt.f32.f16 s0, s2
-; CHECK-NEXT: vmaxnm.f32 s2, s0, s4
-; CHECK-NEXT: vminnm.f32 s8, s8, s6
-; CHECK-NEXT: vminnm.f32 s2, s2, s6
-; CHECK-NEXT: vmov r3, s10
-; CHECK-NEXT: vcvt.s32.f32 s2, s2
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r3, #0
-; CHECK-NEXT: vcvt.s32.f32 s8, s8
-; CHECK-NEXT: bfc r3, #19, #13
-; CHECK-NEXT: mov r2, r12
-; CHECK-NEXT: movs r1, #0
-; CHECK-NEXT: bfc r2, #19, #13
-; CHECK-NEXT: mov r4, r3
-; CHECK-NEXT: lsrl r2, r1, #7
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s0, s0
-; CHECK-NEXT: lsrl r4, r9, #26
-; CHECK-NEXT: vcvtt.f32.f16 s0, s3
-; CHECK-NEXT: mov lr, r1
-; CHECK-NEXT: orr.w r1, r4, r2
-; CHECK-NEXT: vmov r4, s2
-; CHECK-NEXT: vmaxnm.f32 s2, s0, s4
-; CHECK-NEXT: vmov r2, s8
-; CHECK-NEXT: vminnm.f32 s2, s2, s6
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: vcvt.s32.f32 s2, s2
-; CHECK-NEXT: bfc r2, #19, #13
-; CHECK-NEXT: lsll r2, r5, #12
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r4, #0
-; CHECK-NEXT: orrs r2, r1
-; CHECK-NEXT: bfc r4, #19, #13
-; CHECK-NEXT: movs r1, #0
-; CHECK-NEXT: lsll r4, r1, #31
-; CHECK-NEXT: vcmp.f32 s0, s0
-; CHECK-NEXT: orrs r2, r4
-; CHECK-NEXT: str r2, [r0, #8]
-; CHECK-NEXT: orr.w r2, r7, r3, lsl #6
-; CHECK-NEXT: vcvtb.f32.f16 s0, s3
-; CHECK-NEXT: orr.w r3, r2, r12, lsl #25
-; CHECK-NEXT: vmov r2, s2
-; CHECK-NEXT: vmaxnm.f32 s2, s0, s4
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vminnm.f32 s2, s2, s6
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: vcvt.s32.f32 s2, s2
-; CHECK-NEXT: bfc r2, #19, #13
-; CHECK-NEXT: movs r7, #0
-; CHECK-NEXT: vcmp.f32 s0, s0
-; CHECK-NEXT: lsll r2, r7, #5
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: mov.w r11, #0
-; CHECK-NEXT: vmov r7, s2
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r7, #0
-; CHECK-NEXT: mov r4, r7
-; CHECK-NEXT: bfc r4, #19, #13
-; CHECK-NEXT: lsrl r4, r11, #14
-; CHECK-NEXT: orrs r2, r4
-; CHECK-NEXT: strh r2, [r0, #16]
-; CHECK-NEXT: str r3, [r0, #4]
-; CHECK-NEXT: lsrs r2, r2, #16
-; CHECK-NEXT: strb r2, [r0, #18]
-; CHECK-NEXT: orr.w r2, r9, lr
-; CHECK-NEXT: orrs r2, r5
-; CHECK-NEXT: orrs r1, r2
-; CHECK-NEXT: orr.w r1, r1, r7, lsl #18
-; CHECK-NEXT: str r1, [r0, #12]
-; CHECK-NEXT: pop.w {r4, r5, r7, r9, r11, pc}
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI46_0:
-; CHECK-NEXT: .long 0xc8800000 @ float -262144
-; CHECK-NEXT: .LCPI46_1:
-; CHECK-NEXT: .long 0x487fffc0 @ float 262143
- %x = call <8 x i19> @llvm.fptosi.sat.v8f16.v8i19(<8 x half> %f)
- ret <8 x i19> %x
-}
-
-define arm_aapcs_vfpcc <8 x i32> @test_signed_v8f16_v8i32_duplicate(<8 x half> %f) {
-; CHECK-LABEL: test_signed_v8f16_v8i32_duplicate:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: vmovx.f16 s4, s3
-; CHECK-NEXT: vmovx.f16 s6, s0
-; CHECK-NEXT: vcvt.s32.f16 s8, s4
-; CHECK-NEXT: vmovx.f16 s4, s2
-; CHECK-NEXT: vcvt.s32.f16 s10, s4
-; CHECK-NEXT: vmovx.f16 s4, s1
-; CHECK-NEXT: vcvt.s32.f16 s14, s2
-; CHECK-NEXT: vcvt.s32.f16 s2, s1
-; CHECK-NEXT: vcvt.s32.f16 s0, s0
-; CHECK-NEXT: vcvt.s32.f16 s4, s4
-; CHECK-NEXT: vcvt.s32.f16 s6, s6
-; CHECK-NEXT: vmov r0, s2
-; CHECK-NEXT: vmov r1, s0
-; CHECK-NEXT: vcvt.s32.f16 s12, s3
-; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
-; CHECK-NEXT: vmov r0, s4
-; CHECK-NEXT: vmov r1, s6
-; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
-; CHECK-NEXT: vmov r0, s12
-; CHECK-NEXT: vmov r1, s14
-; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
-; CHECK-NEXT: vmov r0, s8
-; CHECK-NEXT: vmov r1, s10
-; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
-; CHECK-NEXT: bx lr
- %x = call <8 x i32> @llvm.fptosi.sat.v8f16.v8i32(<8 x half> %f)
- ret <8 x i32> %x
-}
-
-define arm_aapcs_vfpcc <8 x i50> @test_signed_v8f16_v8i50(<8 x half> %f) {
-; CHECK-LABEL: test_signed_v8f16_v8i50:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEXT: .pad #4
-; CHECK-NEXT: sub sp, #4
-; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: vmov q4, q0
-; CHECK-NEXT: mov r9, r0
-; CHECK-NEXT: vcvtt.f32.f16 s30, s19
-; CHECK-NEXT: vmov r0, s30
-; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: vcvtb.f32.f16 s26, s18
-; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vmov r0, s26
-; CHECK-NEXT: vldr s24, .LCPI48_1
-; CHECK-NEXT: vcvtb.f32.f16 s20, s16
-; CHECK-NEXT: vcvtb.f32.f16 s28, s19
-; CHECK-NEXT: vcmp.f32 s30, s24
-; CHECK-NEXT: mov r5, r1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vmov r7, s20
-; CHECK-NEXT: vldr s22, .LCPI48_0
-; CHECK-NEXT: vmov r6, s28
-; CHECK-NEXT: itt lt
-; CHECK-NEXT: movlt r5, #0
-; CHECK-NEXT: movtlt r5, #65534
-; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: vcmp.f32 s26, s24
-; CHECK-NEXT: mov r10, r1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s22
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s22
-; CHECK-NEXT: itt gt
-; CHECK-NEXT: movwgt r5, #65535
-; CHECK-NEXT: movtgt r5, #1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s26, s26
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str.w r0, [r9, #25]
-; CHECK-NEXT: mov r0, r7
-; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: vcmp.f32 s20, s24
-; CHECK-NEXT: mov r8, r1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s20, s22
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s20, s20
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s24
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str.w r0, [r9]
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r4, #0
-; CHECK-NEXT: vcmp.f32 s30, s22
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r4, #-1
-; CHECK-NEXT: vcmp.f32 s30, s30
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt vs
-; CHECK-NEXT: movvs r4, #0
-; CHECK-NEXT: movvs r5, #0
-; CHECK-NEXT: mov r7, r5
-; CHECK-NEXT: bfc r7, #18, #14
-; CHECK-NEXT: lsll r4, r7, #22
-; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: vcmp.f32 s28, s24
-; CHECK-NEXT: mov r6, r0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s22
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r6, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s28
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r6, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s24
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r6, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: movtlt r1, #65534
-; CHECK-NEXT: vcmp.f32 s28, s22
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s28
-; CHECK-NEXT: itt gt
-; CHECK-NEXT: movwgt r1, #65535
-; CHECK-NEXT: movtgt r1, #1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r1, #0
-; CHECK-NEXT: mov r2, r6
-; CHECK-NEXT: bfc r1, #18, #14
-; CHECK-NEXT: vcvtt.f32.f16 s28, s18
-; CHECK-NEXT: lsrl r2, r1, #28
-; CHECK-NEXT: orr.w r0, r1, r7
-; CHECK-NEXT: str.w r0, [r9, #45]
-; CHECK-NEXT: vmov r0, s28
-; CHECK-NEXT: orrs r4, r2
-; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: vcmp.f32 s28, s24
-; CHECK-NEXT: mov r7, r0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: movtlt r1, #65534
-; CHECK-NEXT: vcmp.f32 s28, s22
-; CHECK-NEXT: vcvtb.f32.f16 s18, s17
-; CHECK-NEXT: lsrs r0, r5, #10
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt gt
-; CHECK-NEXT: movwgt r1, #65535
-; CHECK-NEXT: movtgt r1, #1
-; CHECK-NEXT: str.w r4, [r9, #41]
-; CHECK-NEXT: strb.w r0, [r9, #49]
-; CHECK-NEXT: vmov r0, s18
-; CHECK-NEXT: vcmp.f32 s28, s24
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r7, #0
-; CHECK-NEXT: vcmp.f32 s28, s22
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r7, #-1
-; CHECK-NEXT: vcmp.f32 s28, s28
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt vs
-; CHECK-NEXT: movvs r7, #0
-; CHECK-NEXT: movvs r1, #0
-; CHECK-NEXT: bfc r1, #18, #14
-; CHECK-NEXT: mov r4, r7
-; CHECK-NEXT: lsrl r4, r1, #14
-; CHECK-NEXT: orr.w r6, r1, r6, lsl #4
-; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: vcvtt.f32.f16 s28, s17
-; CHECK-NEXT: mov r11, r0
-; CHECK-NEXT: vmov r0, s28
-; CHECK-NEXT: mov r5, r1
-; CHECK-NEXT: vcmp.f32 s18, s24
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt lt
-; CHECK-NEXT: movlt r5, #0
-; CHECK-NEXT: movtlt r5, #65534
-; CHECK-NEXT: vcmp.f32 s18, s22
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt gt
-; CHECK-NEXT: movwgt r5, #65535
-; CHECK-NEXT: movtgt r5, #1
-; CHECK-NEXT: str.w r6, [r9, #37]
-; CHECK-NEXT: str.w r4, [r9, #33]
-; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: vcmp.f32 s28, s24
-; CHECK-NEXT: mov r4, r1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s22
-; CHECK-NEXT: itt lt
-; CHECK-NEXT: movlt r4, #0
-; CHECK-NEXT: movtlt r4, #65534
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s24
-; CHECK-NEXT: itt gt
-; CHECK-NEXT: movwgt r4, #65535
-; CHECK-NEXT: movtgt r4, #1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt lt
-; CHECK-NEXT: movwlt r10, #0
-; CHECK-NEXT: movtlt r10, #65534
-; CHECK-NEXT: vcmp.f32 s26, s22
-; CHECK-NEXT: mov r6, r0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt gt
-; CHECK-NEXT: movwgt r10, #65535
-; CHECK-NEXT: movtgt r10, #1
-; CHECK-NEXT: vcmp.f32 s26, s26
-; CHECK-NEXT: vcvtt.f32.f16 s16, s16
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs.w r10, #0
-; CHECK-NEXT: bfc r10, #18, #14
-; CHECK-NEXT: vcmp.f32 s28, s24
-; CHECK-NEXT: orr.w r0, r10, r7, lsl #18
-; CHECK-NEXT: str.w r0, [r9, #29]
-; CHECK-NEXT: vmov r0, s16
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s22
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r6, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s28
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r6, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s24
-; CHECK-NEXT: itt vs
-; CHECK-NEXT: movvs r6, #0
-; CHECK-NEXT: movvs r4, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r11, #0
-; CHECK-NEXT: vcmp.f32 s18, s22
-; CHECK-NEXT: mov r1, r4
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r11, #-1
-; CHECK-NEXT: vcmp.f32 s18, s18
-; CHECK-NEXT: bfc r1, #18, #14
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt vs
-; CHECK-NEXT: movvs.w r11, #0
-; CHECK-NEXT: movvs r5, #0
-; CHECK-NEXT: vcmp.f32 s20, s24
-; CHECK-NEXT: bfc r5, #18, #14
-; CHECK-NEXT: mov r10, r11
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: lsll r6, r1, #22
-; CHECK-NEXT: lsrl r10, r5, #28
-; CHECK-NEXT: itt lt
-; CHECK-NEXT: movwlt r8, #0
-; CHECK-NEXT: movtlt r8, #65534
-; CHECK-NEXT: vcmp.f32 s20, s22
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt gt
-; CHECK-NEXT: movwgt r8, #65535
-; CHECK-NEXT: movtgt r8, #1
-; CHECK-NEXT: orrs r1, r5
-; CHECK-NEXT: str.w r1, [r9, #20]
-; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: vcmp.f32 s16, s24
-; CHECK-NEXT: orr.w r2, r10, r6
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: movtlt r1, #65534
-; CHECK-NEXT: vcmp.f32 s16, s22
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt gt
-; CHECK-NEXT: movwgt r1, #65535
-; CHECK-NEXT: movtgt r1, #1
-; CHECK-NEXT: str.w r2, [r9, #16]
-; CHECK-NEXT: lsrs r2, r4, #10
-; CHECK-NEXT: vcmp.f32 s16, s24
-; CHECK-NEXT: strb.w r2, [r9, #24]
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s16, s22
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s16, s16
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt vs
-; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: movvs r1, #0
-; CHECK-NEXT: bfc r1, #18, #14
-; CHECK-NEXT: mov r2, r0
-; CHECK-NEXT: lsrl r2, r1, #14
-; CHECK-NEXT: vcmp.f32 s20, s20
-; CHECK-NEXT: orr.w r1, r1, r11, lsl #4
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: strd r2, r1, [r9, #8]
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs.w r8, #0
-; CHECK-NEXT: bfc r8, #18, #14
-; CHECK-NEXT: orr.w r0, r8, r0, lsl #18
-; CHECK-NEXT: str.w r0, [r9, #4]
-; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: add sp, #4
-; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI48_0:
-; CHECK-NEXT: .long 0x57ffffff @ float 5.6294992E+14
-; CHECK-NEXT: .LCPI48_1:
-; CHECK-NEXT: .long 0xd8000000 @ float -5.62949953E+14
- %x = call <8 x i50> @llvm.fptosi.sat.v8f16.v8i50(<8 x half> %f)
- ret <8 x i50> %x
-}
-
-define arm_aapcs_vfpcc <8 x i64> @test_signed_v8f16_v8i64(<8 x half> %f) {
-; CHECK-LABEL: test_signed_v8f16_v8i64:
-; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
-; CHECK-NEXT: .pad #4
-; CHECK-NEXT: sub sp, #4
-; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: vmov q4, q0
-; CHECK-NEXT: vcvtt.f32.f16 s20, s19
-; CHECK-NEXT: vmov r0, s20
-; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: vcvtb.f32.f16 s22, s19
-; CHECK-NEXT: mov r9, r0
-; CHECK-NEXT: vmov r0, s22
-; CHECK-NEXT: vldr s30, .LCPI49_1
-; CHECK-NEXT: vldr s28, .LCPI49_0
-; CHECK-NEXT: vcvtb.f32.f16 s24, s16
-; CHECK-NEXT: vcmp.f32 s20, s30
-; CHECK-NEXT: vcvtt.f32.f16 s16, s16
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r9, #0
-; CHECK-NEXT: vcmp.f32 s20, s28
-; CHECK-NEXT: mov r8, r1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r9, #-1
-; CHECK-NEXT: vcmp.f32 s20, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vmov r4, s24
-; CHECK-NEXT: vmov r5, s16
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs.w r9, #0
-; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: vcmp.f32 s22, s30
-; CHECK-NEXT: mov r11, r0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s22, s28
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r11, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s22, s22
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r11, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s20, s30
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs.w r11, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s20, s28
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r8, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s20, s20
-; CHECK-NEXT: it gt
-; CHECK-NEXT: mvngt r8, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: mov r10, r1
-; CHECK-NEXT: vcmp.f32 s22, s30
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs.w r8, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r10, #-2147483648
-; CHECK-NEXT: vcmp.f32 s22, s28
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: it gt
-; CHECK-NEXT: mvngt r10, #-2147483648
-; CHECK-NEXT: vcmp.f32 s22, s22
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs.w r10, #0
-; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: mov r6, r0
-; CHECK-NEXT: vcmp.f32 s16, s30
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r6, #0
-; CHECK-NEXT: vcmp.f32 s16, s28
-; CHECK-NEXT: mov r0, r4
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r6, #-1
-; CHECK-NEXT: vcmp.f32 s16, s16
-; CHECK-NEXT: mov r5, r1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r6, #0
-; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: vcvtt.f32.f16 s19, s17
-; CHECK-NEXT: mov r7, r1
-; CHECK-NEXT: vmov r1, s19
-; CHECK-NEXT: vcmp.f32 s24, s30
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s24, s28
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s24, s24
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: vmov q5[2], q5[0], r0, r6
-; CHECK-NEXT: mov r0, r1
-; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: vcvtb.f32.f16 s17, s17
-; CHECK-NEXT: mov r6, r0
-; CHECK-NEXT: vmov r0, s17
-; CHECK-NEXT: mov r4, r1
-; CHECK-NEXT: vcmp.f32 s19, s30
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s28
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r6, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s19
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r6, #-1
+; CHECK-MVE-NEXT: vcvtb.f32.f16 s3, s3
+; CHECK-MVE-NEXT: vldr s4, .LCPI45_0
+; CHECK-MVE-NEXT: vmaxnm.f32 s16, s3, s6
+; CHECK-MVE-NEXT: vcvtt.f32.f16 s7, s2
+; CHECK-MVE-NEXT: vmaxnm.f32 s15, s13, s6
+; CHECK-MVE-NEXT: vminnm.f32 s16, s16, s4
+; CHECK-MVE-NEXT: vcvtb.f32.f16 s2, s2
+; CHECK-MVE-NEXT: vminnm.f32 s15, s15, s4
+; CHECK-MVE-NEXT: vmaxnm.f32 s11, s2, s6
+; CHECK-MVE-NEXT: vcvt.s32.f32 s16, s16
+; CHECK-MVE-NEXT: vcvtt.f32.f16 s12, s1
+; CHECK-MVE-NEXT: vmaxnm.f32 s9, s7, s6
+; CHECK-MVE-NEXT: vminnm.f32 s11, s11, s4
+; CHECK-MVE-NEXT: vcvtb.f32.f16 s1, s1
+; CHECK-MVE-NEXT: vcvt.s32.f32 s15, s15
+; CHECK-MVE-NEXT: vcvtb.f32.f16 s8, s0
+; CHECK-MVE-NEXT: vmaxnm.f32 s5, s1, s6
+; CHECK-MVE-NEXT: vminnm.f32 s9, s9, s4
+; CHECK-MVE-NEXT: vcvt.s32.f32 s11, s11
+; CHECK-MVE-NEXT: vmaxnm.f32 s10, s8, s6
+; CHECK-MVE-NEXT: vmaxnm.f32 s14, s12, s6
+; CHECK-MVE-NEXT: vminnm.f32 s5, s5, s4
+; CHECK-MVE-NEXT: vcvt.s32.f32 s9, s9
+; CHECK-MVE-NEXT: vcvtt.f32.f16 s0, s0
+; CHECK-MVE-NEXT: vminnm.f32 s10, s10, s4
+; CHECK-MVE-NEXT: vminnm.f32 s14, s14, s4
+; CHECK-MVE-NEXT: vcvt.s32.f32 s5, s5
+; CHECK-MVE-NEXT: vmaxnm.f32 s6, s0, s6
+; CHECK-MVE-NEXT: vminnm.f32 s4, s6, s4
+; CHECK-MVE-NEXT: vcvt.s32.f32 s10, s10
+; CHECK-MVE-NEXT: vcvt.s32.f32 s14, s14
+; CHECK-MVE-NEXT: vcvt.s32.f32 s4, s4
+; CHECK-MVE-NEXT: vcmp.f32 s3, s3
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmov r12, s16
+; CHECK-MVE-NEXT: vcmp.f32 s13, s13
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs.w r12, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmov lr, s15
+; CHECK-MVE-NEXT: vcmp.f32 s2, s2
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs.w lr, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmov r2, s11
+; CHECK-MVE-NEXT: vcmp.f32 s7, s7
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r2, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmov r3, s9
+; CHECK-MVE-NEXT: vcmp.f32 s1, s1
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r3, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmov r0, s5
+; CHECK-MVE-NEXT: vcmp.f32 s12, s12
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r0, #0
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmov r1, s14
+; CHECK-MVE-NEXT: vmov r4, s10
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r1, #0
+; CHECK-MVE-NEXT: vcmp.f32 s8, s8
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r4, #0
+; CHECK-MVE-NEXT: vcmp.f32 s0, s0
+; CHECK-MVE-NEXT: vmov.16 q0[0], r4
+; CHECK-MVE-NEXT: vmov r5, s4
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: it vs
+; CHECK-MVE-NEXT: movvs r5, #0
+; CHECK-MVE-NEXT: vmov.16 q0[1], r5
+; CHECK-MVE-NEXT: vmov.16 q0[2], r0
+; CHECK-MVE-NEXT: vmov.16 q0[3], r1
+; CHECK-MVE-NEXT: vmov.16 q0[4], r2
+; CHECK-MVE-NEXT: vmov.16 q0[5], r3
+; CHECK-MVE-NEXT: vmov.16 q0[6], r12
+; CHECK-MVE-NEXT: vmov.16 q0[7], lr
+; CHECK-MVE-NEXT: vpop {d8}
+; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
+; CHECK-MVE-NEXT: .p2align 2
+; CHECK-MVE-NEXT: @ %bb.1:
+; CHECK-MVE-NEXT: .LCPI45_0:
+; CHECK-MVE-NEXT: .long 0x46fffe00 @ float 32767
+; CHECK-MVE-NEXT: .LCPI45_1:
+; CHECK-MVE-NEXT: .long 0xc7000000 @ float -32768
+;
+; CHECK-MVEFP-LABEL: test_signed_v8f16_v8i16:
+; CHECK-MVEFP: @ %bb.0:
+; CHECK-MVEFP-NEXT: vcvt.s16.f16 q0, q0
+; CHECK-MVEFP-NEXT: bx lr
+ %x = call <8 x i16> @llvm.fptosi.sat.v8f16.v8i16(<8 x half> %f)
+ ret <8 x i16> %x
+}
+
+define arm_aapcs_vfpcc <8 x i19> @test_signed_v8f16_v8i19(<8 x half> %f) {
+; CHECK-LABEL: test_signed_v8f16_v8i19:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r7, r9, r11, lr}
+; CHECK-NEXT: push.w {r4, r5, r7, r9, r11, lr}
+; CHECK-NEXT: vldr s6, .LCPI46_1
+; CHECK-NEXT: vcvtb.f32.f16 s12, s0
+; CHECK-NEXT: vcvtt.f32.f16 s0, s0
+; CHECK-NEXT: vldr s4, .LCPI46_0
+; CHECK-NEXT: vmaxnm.f32 s5, s0, s6
+; CHECK-NEXT: vmaxnm.f32 s14, s12, s6
+; CHECK-NEXT: vminnm.f32 s5, s5, s4
+; CHECK-NEXT: vcvtt.f32.f16 s8, s1
+; CHECK-NEXT: vminnm.f32 s14, s14, s4
+; CHECK-NEXT: vcvt.s32.f32 s5, s5
+; CHECK-NEXT: vmaxnm.f32 s10, s8, s6
+; CHECK-NEXT: vcvt.s32.f32 s14, s14
+; CHECK-NEXT: vminnm.f32 s10, s10, s4
+; CHECK-NEXT: vcvtb.f32.f16 s1, s1
+; CHECK-NEXT: vcvt.s32.f32 s10, s10
+; CHECK-NEXT: vmaxnm.f32 s7, s1, s6
+; CHECK-NEXT: vminnm.f32 s7, s7, s4
+; CHECK-NEXT: vcmp.f32 s0, s0
+; CHECK-NEXT: vcvt.s32.f32 s7, s7
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s30
+; CHECK-NEXT: vcmp.f32 s12, s12
+; CHECK-NEXT: mov.w r7, #0
+; CHECK-NEXT: vmov r2, s5
+; CHECK-NEXT: vcvtb.f32.f16 s0, s2
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r6, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s28
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r5, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s16
-; CHECK-NEXT: it gt
-; CHECK-NEXT: mvngt r5, #-2147483648
+; CHECK-NEXT: movvs r2, #0
+; CHECK-NEXT: vmov r1, s14
+; CHECK-NEXT: bfc r2, #19, #13
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, s30
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r5, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r7, #-2147483648
-; CHECK-NEXT: vcmp.f32 s24, s28
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: mvngt r7, #-2147483648
-; CHECK-NEXT: vcmp.f32 s24, s24
+; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: vcmp.f32 s8, s8
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: lsll r2, r7, #19
+; CHECK-NEXT: bfc r1, #19, #13
+; CHECK-NEXT: vmov r12, s10
+; CHECK-NEXT: vcmp.f32 s1, s1
+; CHECK-NEXT: vmaxnm.f32 s8, s0, s6
+; CHECK-NEXT: orr.w r1, r1, r2
+; CHECK-NEXT: str r1, [r0]
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r7, #0
-; CHECK-NEXT: vmov q5[3], q5[1], r7, r5
-; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: vcvtt.f32.f16 s16, s18
-; CHECK-NEXT: mov r7, r1
-; CHECK-NEXT: vmov r1, s16
-; CHECK-NEXT: vcmp.f32 s17, s30
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s17, s28
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s17, s17
+; CHECK-NEXT: movvs.w r12, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vcmp.f32 s0, s0
+; CHECK-NEXT: vcvtt.f32.f16 s0, s2
+; CHECK-NEXT: vmaxnm.f32 s2, s0, s6
+; CHECK-NEXT: vminnm.f32 s8, s8, s4
+; CHECK-NEXT: vminnm.f32 s2, s2, s4
+; CHECK-NEXT: vmov r3, s7
+; CHECK-NEXT: vcvt.s32.f32 s2, s2
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: vmov q6[2], q6[0], r0, r6
-; CHECK-NEXT: mov r0, r1
-; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: vcvtb.f32.f16 s18, s18
-; CHECK-NEXT: mov r6, r0
-; CHECK-NEXT: vmov r0, s18
-; CHECK-NEXT: mov r5, r1
-; CHECK-NEXT: vcmp.f32 s16, s30
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s28
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r6, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s16
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r6, #-1
+; CHECK-NEXT: movvs r3, #0
+; CHECK-NEXT: vcvt.s32.f32 s8, s8
+; CHECK-NEXT: bfc r3, #19, #13
+; CHECK-NEXT: mov r2, r12
+; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: bfc r2, #19, #13
+; CHECK-NEXT: mov r4, r3
+; CHECK-NEXT: mov.w r9, #0
+; CHECK-NEXT: lsrl r2, r1, #7
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s30
+; CHECK-NEXT: vcmp.f32 s0, s0
+; CHECK-NEXT: lsrl r4, r9, #26
+; CHECK-NEXT: vcvtt.f32.f16 s0, s3
+; CHECK-NEXT: mov lr, r1
+; CHECK-NEXT: orr.w r1, r4, r2
+; CHECK-NEXT: vmov r4, s2
+; CHECK-NEXT: vmaxnm.f32 s2, s0, s6
+; CHECK-NEXT: vmov r2, s8
+; CHECK-NEXT: vminnm.f32 s2, s2, s4
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r6, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s28
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r4, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s19
-; CHECK-NEXT: it gt
-; CHECK-NEXT: mvngt r4, #-2147483648
+; CHECK-NEXT: movvs r2, #0
+; CHECK-NEXT: vcvt.s32.f32 s2, s2
+; CHECK-NEXT: bfc r2, #19, #13
+; CHECK-NEXT: movs r5, #0
+; CHECK-NEXT: lsll r2, r5, #12
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s30
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r4, #0
+; CHECK-NEXT: orrs r2, r1
+; CHECK-NEXT: bfc r4, #19, #13
+; CHECK-NEXT: movs r1, #0
+; CHECK-NEXT: lsll r4, r1, #31
+; CHECK-NEXT: vcmp.f32 s0, s0
+; CHECK-NEXT: orrs r2, r4
+; CHECK-NEXT: str r2, [r0, #8]
+; CHECK-NEXT: orr.w r2, r7, r3, lsl #6
+; CHECK-NEXT: vcvtb.f32.f16 s0, s3
+; CHECK-NEXT: orr.w r3, r2, r12, lsl #25
+; CHECK-NEXT: vmov r2, s2
+; CHECK-NEXT: vmaxnm.f32 s2, s0, s6
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r7, #-2147483648
-; CHECK-NEXT: vcmp.f32 s17, s28
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: mvngt r7, #-2147483648
-; CHECK-NEXT: vcmp.f32 s17, s17
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r7, #0
-; CHECK-NEXT: vmov q6[3], q6[1], r7, r4
-; CHECK-NEXT: bl __aeabi_f2lz
-; CHECK-NEXT: vcmp.f32 s18, s30
-; CHECK-NEXT: vmov q3[2], q3[0], r11, r9
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s28
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s18
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s30
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s28
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r5, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s16
-; CHECK-NEXT: it gt
-; CHECK-NEXT: mvngt r5, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s30
+; CHECK-NEXT: vminnm.f32 s2, s2, s4
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r5, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r1, #-2147483648
-; CHECK-NEXT: vcmp.f32 s18, s28
-; CHECK-NEXT: vmov q2[2], q2[0], r0, r6
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: mvngt r1, #-2147483648
-; CHECK-NEXT: vcmp.f32 s18, s18
-; CHECK-NEXT: vmov q3[3], q3[1], r10, r8
+; CHECK-NEXT: movvs r2, #0
+; CHECK-NEXT: vcvt.s32.f32 s2, s2
+; CHECK-NEXT: bfc r2, #19, #13
+; CHECK-NEXT: movs r7, #0
+; CHECK-NEXT: vcmp.f32 s0, s0
+; CHECK-NEXT: lsll r2, r7, #5
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: mov.w r11, #0
+; CHECK-NEXT: vmov r7, s2
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r1, #0
-; CHECK-NEXT: vmov q2[3], q2[1], r1, r5
-; CHECK-NEXT: vmov q0, q5
-; CHECK-NEXT: vmov q1, q6
-; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: add sp, #4
-; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+; CHECK-NEXT: movvs r7, #0
+; CHECK-NEXT: mov r4, r7
+; CHECK-NEXT: bfc r4, #19, #13
+; CHECK-NEXT: lsrl r4, r11, #14
+; CHECK-NEXT: orrs r2, r4
+; CHECK-NEXT: strh r2, [r0, #16]
+; CHECK-NEXT: str r3, [r0, #4]
+; CHECK-NEXT: lsrs r2, r2, #16
+; CHECK-NEXT: strb r2, [r0, #18]
+; CHECK-NEXT: orr.w r2, r9, lr
+; CHECK-NEXT: orrs r2, r5
+; CHECK-NEXT: orrs r1, r2
+; CHECK-NEXT: orr.w r1, r1, r7, lsl #18
+; CHECK-NEXT: str r1, [r0, #12]
+; CHECK-NEXT: pop.w {r4, r5, r7, r9, r11, pc}
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI49_0:
-; CHECK-NEXT: .long 0x5effffff @ float 9.22337149E+18
-; CHECK-NEXT: .LCPI49_1:
-; CHECK-NEXT: .long 0xdf000000 @ float -9.22337203E+18
- %x = call <8 x i64> @llvm.fptosi.sat.v8f16.v8i64(<8 x half> %f)
- ret <8 x i64> %x
+; CHECK-NEXT: .LCPI46_0:
+; CHECK-NEXT: .long 0x487fffc0 @ float 262143
+; CHECK-NEXT: .LCPI46_1:
+; CHECK-NEXT: .long 0xc8800000 @ float -262144
+ %x = call <8 x i19> @llvm.fptosi.sat.v8f16.v8i19(<8 x half> %f)
+ ret <8 x i19> %x
}
-define arm_aapcs_vfpcc <8 x i100> @test_signed_v8f16_v8i100(<8 x half> %f) {
-; CHECK-LABEL: test_signed_v8f16_v8i100:
+define arm_aapcs_vfpcc <8 x i32> @test_signed_v8f16_v8i32_duplicate(<8 x half> %f) {
+; CHECK-LABEL: test_signed_v8f16_v8i32_duplicate:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: vmovx.f16 s4, s3
+; CHECK-NEXT: vmovx.f16 s6, s0
+; CHECK-NEXT: vcvt.s32.f16 s8, s4
+; CHECK-NEXT: vmovx.f16 s4, s2
+; CHECK-NEXT: vcvt.s32.f16 s10, s4
+; CHECK-NEXT: vmovx.f16 s4, s1
+; CHECK-NEXT: vcvt.s32.f16 s14, s2
+; CHECK-NEXT: vcvt.s32.f16 s2, s1
+; CHECK-NEXT: vcvt.s32.f16 s0, s0
+; CHECK-NEXT: vcvt.s32.f16 s4, s4
+; CHECK-NEXT: vcvt.s32.f16 s6, s6
+; CHECK-NEXT: vmov r0, s2
+; CHECK-NEXT: vmov r1, s0
+; CHECK-NEXT: vcvt.s32.f16 s12, s3
+; CHECK-NEXT: vmov q0[2], q0[0], r1, r0
+; CHECK-NEXT: vmov r0, s4
+; CHECK-NEXT: vmov r1, s6
+; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
+; CHECK-NEXT: vmov r0, s12
+; CHECK-NEXT: vmov r1, s14
+; CHECK-NEXT: vmov q1[2], q1[0], r1, r0
+; CHECK-NEXT: vmov r0, s8
+; CHECK-NEXT: vmov r1, s10
+; CHECK-NEXT: vmov q1[3], q1[1], r1, r0
+; CHECK-NEXT: bx lr
+ %x = call <8 x i32> @llvm.fptosi.sat.v8f16.v8i32(<8 x half> %f)
+ ret <8 x i32> %x
+}
+
+define arm_aapcs_vfpcc <8 x i50> @test_signed_v8f16_v8i50(<8 x half> %f) {
+; CHECK-LABEL: test_signed_v8f16_v8i50:
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
@@ -5417,996 +4561,1039 @@ define arm_aapcs_vfpcc <8 x i100> @test_signed_v8f16_v8i100(<8 x half> %f) {
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: .pad #32
-; CHECK-NEXT: sub sp, #32
+; CHECK-NEXT: .pad #24
+; CHECK-NEXT: sub sp, #24
; CHECK-NEXT: vmov q4, q0
-; CHECK-NEXT: mov r11, r0
-; CHECK-NEXT: vcvtb.f32.f16 s21, s19
-; CHECK-NEXT: vcvtt.f32.f16 s24, s19
-; CHECK-NEXT: vmov r0, s21
-; CHECK-NEXT: vcvtb.f32.f16 s26, s16
+; CHECK-NEXT: mov r7, r0
+; CHECK-NEXT: vcvtt.f32.f16 s24, s17
+; CHECK-NEXT: vmov r0, s24
+; CHECK-NEXT: bl __aeabi_f2lz
; CHECK-NEXT: vcvtb.f32.f16 s28, s17
-; CHECK-NEXT: vcvtb.f32.f16 s30, s18
-; CHECK-NEXT: vldr s20, .LCPI50_2
-; CHECK-NEXT: vmov r8, s24
-; CHECK-NEXT: vmov r9, s26
-; CHECK-NEXT: vcvtt.f32.f16 s22, s18
-; CHECK-NEXT: vmov r6, s28
-; CHECK-NEXT: vmov r7, s30
-; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vldr s18, .LCPI50_3
-; CHECK-NEXT: mov r5, r3
-; CHECK-NEXT: vcmp.f32 s21, s18
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s21, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s21, s21
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s21, s18
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r2, #0
+; CHECK-NEXT: mov r8, r0
+; CHECK-NEXT: vmov r0, s28
+; CHECK-NEXT: mov r6, r1
+; CHECK-NEXT: bl __aeabi_f2lz
+; CHECK-NEXT: vcvtt.f32.f16 s30, s16
+; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vmov r0, s30
+; CHECK-NEXT: mov r5, r1
+; CHECK-NEXT: bl __aeabi_f2lz
+; CHECK-NEXT: vcvtb.f32.f16 s26, s18
+; CHECK-NEXT: mov r2, r0
+; CHECK-NEXT: vmov r0, s26
+; CHECK-NEXT: vldr s20, .LCPI48_0
+; CHECK-NEXT: vldr s22, .LCPI48_1
+; CHECK-NEXT: vcmp.f32 s30, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s21, s20
-; CHECK-NEXT: str.w r2, [r11, #83]
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movtlt r1, #65534
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s21, s21
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s21, s18
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str.w r1, [r11, #79]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s21, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s21, s21
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str.w r0, [r11, #75]
-; CHECK-NEXT: mov r0, r7
-; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vcmp.f32 s30, s18
-; CHECK-NEXT: mov r7, r3
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s20
+; CHECK-NEXT: vcmp.f32 s30, s22
; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s30, s30
-; CHECK-NEXT: it gt
+; CHECK-NEXT: ittt gt
+; CHECK-NEXT: movwgt r1, #65535
+; CHECK-NEXT: movtgt r1, #1
; CHECK-NEXT: movgt.w r2, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s18
+; CHECK-NEXT: vcmp.f32 s28, s20
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s20
-; CHECK-NEXT: str.w r2, [r11, #58]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s30
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s18
+; CHECK-NEXT: str r2, [sp, #20] @ 4-byte Spill
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str.w r1, [r11, #54]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s30, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s30, s30
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str.w r0, [r11, #50]
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vcmp.f32 s28, s18
-; CHECK-NEXT: str r3, [sp, #24] @ 4-byte Spill
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: vcmp.f32 s28, s22
+; CHECK-NEXT: str r1, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT: ittt lt
+; CHECK-NEXT: movlt r5, #0
+; CHECK-NEXT: movtlt r5, #65534
+; CHECK-NEXT: movlt r4, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s28, s28
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: ittt gt
+; CHECK-NEXT: movwgt r5, #65535
+; CHECK-NEXT: movtgt r5, #1
+; CHECK-NEXT: movgt.w r4, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s18
+; CHECK-NEXT: vcmp.f32 s24, s20
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s20
-; CHECK-NEXT: str.w r2, [r11, #33]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s28
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s18
+; CHECK-NEXT: movvs r4, #0
+; CHECK-NEXT: str r4, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: movvs r5, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str.w r1, [r11, #29]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s28, s20
+; CHECK-NEXT: str r5, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT: ittt lt
+; CHECK-NEXT: movlt r6, #0
+; CHECK-NEXT: movtlt r6, #65534
+; CHECK-NEXT: movlt.w r8, #0
+; CHECK-NEXT: vcmp.f32 s24, s22
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s28, s28
+; CHECK-NEXT: ittt gt
+; CHECK-NEXT: movwgt r6, #65535
+; CHECK-NEXT: movtgt r6, #1
+; CHECK-NEXT: movgt.w r8, #-1
+; CHECK-NEXT: vcmp.f32 s24, s24
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str.w r0, [r11, #25]
-; CHECK-NEXT: mov r0, r9
-; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vcmp.f32 s26, s18
-; CHECK-NEXT: str r3, [sp, #12] @ 4-byte Spill
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s26
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s18
+; CHECK-NEXT: movvs.w r8, #0
+; CHECK-NEXT: str.w r8, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: movvs r6, #0
+; CHECK-NEXT: str r6, [sp] @ 4-byte Spill
+; CHECK-NEXT: bl __aeabi_f2lz
; CHECK-NEXT: vcmp.f32 s26, s20
-; CHECK-NEXT: str.w r2, [r11, #8]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s26
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s18
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: mov r6, r1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str.w r1, [r11, #4]
-; CHECK-NEXT: it lt
+; CHECK-NEXT: ittt lt
+; CHECK-NEXT: movlt r6, #0
+; CHECK-NEXT: movtlt r6, #65534
; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s26, s20
+; CHECK-NEXT: vcmp.f32 s26, s22
+; CHECK-NEXT: vcvtt.f32.f16 s18, s18
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: ittt gt
+; CHECK-NEXT: movwgt r6, #65535
+; CHECK-NEXT: movtgt r6, #1
; CHECK-NEXT: movgt.w r0, #-1
; CHECK-NEXT: vcmp.f32 s26, s26
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str.w r0, [r11]
-; CHECK-NEXT: mov r0, r8
-; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vcmp.f32 s24, s18
-; CHECK-NEXT: mov r6, r0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, s20
-; CHECK-NEXT: str r3, [sp, #8] @ 4-byte Spill
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r6, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, s24
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r6, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s21, s18
+; CHECK-NEXT: str.w r0, [r7, #25]
+; CHECK-NEXT: vmov r0, s18
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r6, #0
+; CHECK-NEXT: bl __aeabi_f2lz
+; CHECK-NEXT: vcmp.f32 s18, s20
+; CHECK-NEXT: mov r8, r0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: mvnlt r5, #7
-; CHECK-NEXT: vcmp.f32 s21, s20
; CHECK-NEXT: mov r9, r1
+; CHECK-NEXT: vcmp.f32 s18, s22
+; CHECK-NEXT: ittt lt
+; CHECK-NEXT: movlt.w r8, #0
+; CHECK-NEXT: movwlt r9, #0
+; CHECK-NEXT: movtlt r9, #65534
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r5, #7
-; CHECK-NEXT: vcmp.f32 s21, s21
-; CHECK-NEXT: mov r8, r2
+; CHECK-NEXT: vcmp.f32 s18, s18
+; CHECK-NEXT: vcvtb.f32.f16 s18, s19
+; CHECK-NEXT: ittt gt
+; CHECK-NEXT: movwgt r9, #65535
+; CHECK-NEXT: movtgt r9, #1
+; CHECK-NEXT: movgt.w r8, #-1
+; CHECK-NEXT: vmov r0, s18
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r5, #0
-; CHECK-NEXT: and r0, r5, #15
-; CHECK-NEXT: orr.w r1, r0, r6, lsl #4
-; CHECK-NEXT: vmov r0, s22
-; CHECK-NEXT: str.w r1, [r11, #87]
-; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vcmp.f32 s22, s18
+; CHECK-NEXT: itt vs
+; CHECK-NEXT: movvs.w r8, #0
+; CHECK-NEXT: movvs.w r9, #0
+; CHECK-NEXT: bl __aeabi_f2lz
+; CHECK-NEXT: vcmp.f32 s18, s20
; CHECK-NEXT: mov r10, r0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s22, s20
-; CHECK-NEXT: str r2, [sp, #4] @ 4-byte Spill
-; CHECK-NEXT: mov r5, r1
-; CHECK-NEXT: str r3, [sp, #20] @ 4-byte Spill
-; CHECK-NEXT: it lt
+; CHECK-NEXT: mov r11, r1
+; CHECK-NEXT: vcmp.f32 s18, s22
+; CHECK-NEXT: ittt lt
; CHECK-NEXT: movlt.w r10, #0
+; CHECK-NEXT: movwlt r11, #0
+; CHECK-NEXT: movtlt r11, #65534
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s22, s22
-; CHECK-NEXT: it gt
+; CHECK-NEXT: vcmp.f32 s18, s18
+; CHECK-NEXT: vcvtt.f32.f16 s18, s19
+; CHECK-NEXT: ittt gt
+; CHECK-NEXT: movwgt r11, #65535
+; CHECK-NEXT: movtgt r11, #1
; CHECK-NEXT: movgt.w r10, #-1
+; CHECK-NEXT: vmov r0, s18
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s18
-; CHECK-NEXT: it vs
+; CHECK-NEXT: itt vs
; CHECK-NEXT: movvs.w r10, #0
+; CHECK-NEXT: movvs.w r11, #0
+; CHECK-NEXT: bl __aeabi_f2lz
+; CHECK-NEXT: vcvtb.f32.f16 s16, s16
+; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vmov r0, s16
+; CHECK-NEXT: mov r5, r1
+; CHECK-NEXT: vcmp.f32 s18, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: mvnlt r7, #7
-; CHECK-NEXT: vcmp.f32 s30, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s30
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r7, #7
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r7, #0
-; CHECK-NEXT: and r0, r7, #15
-; CHECK-NEXT: orr.w r0, r0, r10, lsl #4
-; CHECK-NEXT: vcvtt.f32.f16 s30, s17
-; CHECK-NEXT: str.w r0, [r11, #62]
-; CHECK-NEXT: vmov r0, s30
-; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vcmp.f32 s30, s18
-; CHECK-NEXT: str r2, [sp, #16] @ 4-byte Spill
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r3, [sp, #28] @ 4-byte Spill
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s30, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s30, s30
-; CHECK-NEXT: mov r4, r1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: vcmp.f32 s28, s18
-; CHECK-NEXT: mov r1, r0
-; CHECK-NEXT: str r0, [sp] @ 4-byte Spill
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
-; CHECK-NEXT: vcmp.f32 s28, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: mvnlt r0, #7
+; CHECK-NEXT: ittt lt
+; CHECK-NEXT: movlt r4, #0
+; CHECK-NEXT: movlt r5, #0
+; CHECK-NEXT: movtlt r5, #65534
+; CHECK-NEXT: vcmp.f32 s18, s22
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r0, #7
-; CHECK-NEXT: vcmp.f32 s28, s28
+; CHECK-NEXT: ittt gt
+; CHECK-NEXT: movwgt r5, #65535
+; CHECK-NEXT: movtgt r5, #1
+; CHECK-NEXT: movgt.w r4, #-1
+; CHECK-NEXT: vcmp.f32 s18, s18
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: and r0, r0, #15
-; CHECK-NEXT: vcvtt.f32.f16 s16, s16
-; CHECK-NEXT: orr.w r0, r0, r1, lsl #4
-; CHECK-NEXT: str.w r0, [r11, #37]
-; CHECK-NEXT: vmov r0, s16
-; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vcmp.f32 s16, s18
+; CHECK-NEXT: itt vs
+; CHECK-NEXT: movvs r4, #0
+; CHECK-NEXT: movvs r5, #0
+; CHECK-NEXT: bl __aeabi_f2lz
+; CHECK-NEXT: vcmp.f32 s16, s20
+; CHECK-NEXT: bfc r11, #18, #14
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
+; CHECK-NEXT: ittt lt
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movtlt r1, #65534
; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s16, s20
+; CHECK-NEXT: vcmp.f32 s16, s22
+; CHECK-NEXT: mov r2, r10
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: ittt gt
+; CHECK-NEXT: movwgt r1, #65535
+; CHECK-NEXT: movtgt r1, #1
; CHECK-NEXT: movgt.w r0, #-1
; CHECK-NEXT: vcmp.f32 s16, s16
+; CHECK-NEXT: lsrl r2, r11, #28
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: vcmp.f32 s26, s18
-; CHECK-NEXT: ldr r7, [sp, #12] @ 4-byte Reload
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: mvnlt r7, #7
-; CHECK-NEXT: vcmp.f32 s26, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r7, #7
-; CHECK-NEXT: vcmp.f32 s26, s26
+; CHECK-NEXT: str r0, [r7]
+; CHECK-NEXT: lsrs r0, r5, #10
+; CHECK-NEXT: bfc r5, #18, #14
+; CHECK-NEXT: bfc r9, #18, #14
+; CHECK-NEXT: lsll r4, r5, #22
+; CHECK-NEXT: bfc r6, #18, #14
+; CHECK-NEXT: orr.w r3, r11, r5
+; CHECK-NEXT: str.w r3, [r7, #45]
+; CHECK-NEXT: orrs r2, r4
+; CHECK-NEXT: str.w r2, [r7, #41]
+; CHECK-NEXT: strb.w r0, [r7, #49]
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: lsrl r0, r9, #14
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: orr.w r2, r9, r10, lsl #4
+; CHECK-NEXT: str.w r2, [r7, #37]
+; CHECK-NEXT: str.w r0, [r7, #33]
+; CHECK-NEXT: orr.w r0, r6, r8, lsl #18
+; CHECK-NEXT: str.w r0, [r7, #29]
+; CHECK-NEXT: ldr r5, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: ldr r3, [sp] @ 4-byte Reload
+; CHECK-NEXT: ldr r4, [sp, #12] @ 4-byte Reload
+; CHECK-NEXT: ldr r6, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: bfc r5, #18, #14
+; CHECK-NEXT: lsr.w r0, r3, #10
+; CHECK-NEXT: bfc r3, #18, #14
+; CHECK-NEXT: mov r2, r4
+; CHECK-NEXT: lsll r6, r3, #22
+; CHECK-NEXT: lsrl r2, r5, #28
+; CHECK-NEXT: orr.w r3, r3, r5
+; CHECK-NEXT: str r3, [r7, #20]
+; CHECK-NEXT: orr.w r2, r2, r6
+; CHECK-NEXT: str r2, [r7, #16]
+; CHECK-NEXT: strb r0, [r7, #24]
+; CHECK-NEXT: ldr r3, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT: ldr r6, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: bfc r3, #18, #14
+; CHECK-NEXT: mov r0, r6
+; CHECK-NEXT: lsrl r0, r3, #14
+; CHECK-NEXT: orr.w r2, r3, r4, lsl #4
+; CHECK-NEXT: strd r0, r2, [r7, #8]
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r7, #0
-; CHECK-NEXT: vcmp.f32 s24, s18
-; CHECK-NEXT: and r7, r7, #15
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, s20
-; CHECK-NEXT: orr.w r7, r7, r0, lsl #4
-; CHECK-NEXT: str.w r7, [r11, #12]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r9, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: b.w .LBB50_3
+; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: bfc r1, #18, #14
+; CHECK-NEXT: orr.w r0, r1, r6, lsl #18
+; CHECK-NEXT: str r0, [r7, #4]
+; CHECK-NEXT: add sp, #24
+; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-NEXT: add sp, #4
+; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI50_2:
-; CHECK-NEXT: .long 0x70ffffff @ float 6.33825262E+29
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.2:
-; CHECK-NEXT: .LCPI50_3:
-; CHECK-NEXT: .long 0xf1000000 @ float -6.338253E+29
-; CHECK-NEXT: .p2align 1
-; CHECK-NEXT: .LBB50_3:
-; CHECK-NEXT: vcmp.f32 s24, s24
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r9, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, s18
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs.w r9, #0
+; CHECK-NEXT: .LCPI48_0:
+; CHECK-NEXT: .long 0xd8000000 @ float -5.62949953E+14
+; CHECK-NEXT: .LCPI48_1:
+; CHECK-NEXT: .long 0x57ffffff @ float 5.6294992E+14
+ %x = call <8 x i50> @llvm.fptosi.sat.v8f16.v8i50(<8 x half> %f)
+ ret <8 x i50> %x
+}
+
+define arm_aapcs_vfpcc <8 x i64> @test_signed_v8f16_v8i64(<8 x half> %f) {
+; CHECK-LABEL: test_signed_v8f16_v8i64:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+; CHECK-NEXT: .pad #4
+; CHECK-NEXT: sub sp, #4
+; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-NEXT: vmov q4, q0
+; CHECK-NEXT: vcvtt.f32.f16 s24, s19
+; CHECK-NEXT: vmov r0, s24
+; CHECK-NEXT: bl __aeabi_f2lz
+; CHECK-NEXT: vcvtb.f32.f16 s26, s19
+; CHECK-NEXT: mov r9, r0
+; CHECK-NEXT: vmov r0, s26
+; CHECK-NEXT: vldr s30, .LCPI49_0
+; CHECK-NEXT: vldr s28, .LCPI49_1
+; CHECK-NEXT: mov r8, r1
+; CHECK-NEXT: vcmp.f32 s24, s30
+; CHECK-NEXT: vcvtt.f32.f16 s22, s18
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r8, #0
-; CHECK-NEXT: vcmp.f32 s24, s20
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt.w r8, #-2147483648
+; CHECK-NEXT: movlt.w r9, #0
+; CHECK-NEXT: vcmp.f32 s24, s28
+; CHECK-NEXT: vcvtt.f32.f16 s20, s16
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: lsrl r6, r9, #28
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r8, #-1
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: movgt.w r9, #-1
+; CHECK-NEXT: mvngt r8, #-2147483648
; CHECK-NEXT: vcmp.f32 s24, s24
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
+; CHECK-NEXT: vmov r4, s22
+; CHECK-NEXT: vmov r6, s20
+; CHECK-NEXT: itt vs
; CHECK-NEXT: movvs.w r8, #0
-; CHECK-NEXT: orr.w r7, r9, r8, lsl #4
-; CHECK-NEXT: str.w r7, [r11, #95]
-; CHECK-NEXT: str.w r6, [r11, #91]
-; CHECK-NEXT: vcmp.f32 s24, s18
-; CHECK-NEXT: ldr r7, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: movvs.w r9, #0
+; CHECK-NEXT: bl __aeabi_f2lz
+; CHECK-NEXT: mov r10, r0
+; CHECK-NEXT: vcmp.f32 s26, s30
+; CHECK-NEXT: mov r11, r1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: mvnlt r7, #7
-; CHECK-NEXT: vcmp.f32 s24, s20
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt.w r10, #0
+; CHECK-NEXT: movlt.w r11, #-2147483648
+; CHECK-NEXT: vcmp.f32 s26, s28
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r7, #7
-; CHECK-NEXT: vcmp.f32 s24, s24
+; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: mvngt r11, #-2147483648
+; CHECK-NEXT: movgt.w r10, #-1
+; CHECK-NEXT: vcmp.f32 s26, s26
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r7, #0
-; CHECK-NEXT: and r7, r7, #15
-; CHECK-NEXT: vcmp.f32 s22, s18
-; CHECK-NEXT: lsrl r8, r7, #28
+; CHECK-NEXT: itt vs
+; CHECK-NEXT: movvs.w r10, #0
+; CHECK-NEXT: movvs.w r11, #0
+; CHECK-NEXT: bl __aeabi_f2lz
+; CHECK-NEXT: mov r5, r0
+; CHECK-NEXT: vcmp.f32 s22, s30
+; CHECK-NEXT: mov r4, r1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: strb.w r8, [r11, #99]
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt.w r4, #-2147483648
; CHECK-NEXT: movlt r5, #0
-; CHECK-NEXT: vcmp.f32 s22, s20
+; CHECK-NEXT: vcmp.f32 s22, s28
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: mov r0, r6
+; CHECK-NEXT: itt gt
; CHECK-NEXT: movgt.w r5, #-1
+; CHECK-NEXT: mvngt r4, #-2147483648
; CHECK-NEXT: vcmp.f32 s22, s22
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
+; CHECK-NEXT: itt vs
+; CHECK-NEXT: movvs r4, #0
; CHECK-NEXT: movvs r5, #0
-; CHECK-NEXT: vcmp.f32 s22, s18
-; CHECK-NEXT: ldr r6, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: bl __aeabi_f2lz
+; CHECK-NEXT: vcvtb.f32.f16 s16, s16
+; CHECK-NEXT: mov r7, r0
+; CHECK-NEXT: vmov r0, s16
+; CHECK-NEXT: mov r6, r1
+; CHECK-NEXT: vcmp.f32 s20, s30
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r6, #0
-; CHECK-NEXT: vcmp.f32 s22, s20
-; CHECK-NEXT: lsrl r10, r5, #28
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt.w r6, #-2147483648
+; CHECK-NEXT: movlt r7, #0
+; CHECK-NEXT: vcmp.f32 s20, s28
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r6, #-1
-; CHECK-NEXT: vcmp.f32 s22, s22
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: movgt.w r7, #-1
+; CHECK-NEXT: mvngt r6, #-2147483648
+; CHECK-NEXT: vcmp.f32 s20, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
+; CHECK-NEXT: itt vs
; CHECK-NEXT: movvs r6, #0
-; CHECK-NEXT: orr.w r7, r5, r6, lsl #4
-; CHECK-NEXT: str.w r7, [r11, #70]
-; CHECK-NEXT: str.w r10, [r11, #66]
-; CHECK-NEXT: vcmp.f32 s22, s18
-; CHECK-NEXT: ldr r7, [sp, #20] @ 4-byte Reload
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: mvnlt r7, #7
-; CHECK-NEXT: vcmp.f32 s22, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r7, #7
-; CHECK-NEXT: vcmp.f32 s22, s22
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r7, #0
-; CHECK-NEXT: and r5, r7, #15
-; CHECK-NEXT: vcmp.f32 s30, s18
-; CHECK-NEXT: lsrl r6, r5, #28
+; CHECK-NEXT: bl __aeabi_f2lz
+; CHECK-NEXT: vcmp.f32 s16, s30
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: mov r5, r4
-; CHECK-NEXT: strb.w r6, [r11, #74]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r5, #0
-; CHECK-NEXT: vcmp.f32 s30, s20
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: movlt.w r1, #-2147483648
+; CHECK-NEXT: vcmp.f32 s16, s28
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r5, #-1
-; CHECK-NEXT: vcmp.f32 s30, s30
+; CHECK-NEXT: vcmp.f32 s16, s16
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: mvngt r1, #-2147483648
+; CHECK-NEXT: movgt.w r0, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r5, #0
-; CHECK-NEXT: ldr r4, [sp] @ 4-byte Reload
-; CHECK-NEXT: vcmp.f32 s30, s18
-; CHECK-NEXT: ldr r6, [sp, #16] @ 4-byte Reload
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r6, #0
-; CHECK-NEXT: vcmp.f32 s30, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: lsrl r4, r5, #28
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r6, #-1
-; CHECK-NEXT: vcmp.f32 s30, s30
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: movvs r0, #0
+; CHECK-NEXT: vcvtt.f32.f16 s16, s17
+; CHECK-NEXT: vmov q5[2], q5[0], r0, r7
+; CHECK-NEXT: vmov r0, s16
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r6, #0
-; CHECK-NEXT: orr.w r7, r5, r6, lsl #4
-; CHECK-NEXT: str.w r7, [r11, #45]
-; CHECK-NEXT: str.w r4, [r11, #41]
-; CHECK-NEXT: vcmp.f32 s30, s18
-; CHECK-NEXT: ldr r7, [sp, #28] @ 4-byte Reload
+; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: vmov q5[3], q5[1], r1, r6
+; CHECK-NEXT: bl __aeabi_f2lz
+; CHECK-NEXT: vcmp.f32 s16, s30
+; CHECK-NEXT: mov r7, r0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: mvnlt r7, #7
-; CHECK-NEXT: vcmp.f32 s30, s20
+; CHECK-NEXT: mov r6, r1
+; CHECK-NEXT: vcmp.f32 s16, s28
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt.w r6, #-2147483648
+; CHECK-NEXT: movlt r7, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r7, #7
-; CHECK-NEXT: vcmp.f32 s30, s30
+; CHECK-NEXT: vcmp.f32 s16, s16
+; CHECK-NEXT: vcvtb.f32.f16 s16, s17
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: movgt.w r7, #-1
+; CHECK-NEXT: mvngt r6, #-2147483648
+; CHECK-NEXT: vmov r0, s16
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
+; CHECK-NEXT: itt vs
+; CHECK-NEXT: movvs r6, #0
; CHECK-NEXT: movvs r7, #0
-; CHECK-NEXT: and r5, r7, #15
-; CHECK-NEXT: vcmp.f32 s16, s18
-; CHECK-NEXT: lsrl r6, r5, #28
+; CHECK-NEXT: bl __aeabi_f2lz
+; CHECK-NEXT: vcmp.f32 s16, s30
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: strb.w r6, [r11, #49]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: movlt.w r1, #-2147483648
+; CHECK-NEXT: vcmp.f32 s16, s28
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s16, s16
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: mvngt r1, #-2147483648
+; CHECK-NEXT: movgt.w r0, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s18
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: lsrl r0, r1, #28
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vcmp.f32 s16, s16
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: movvs r0, #0
+; CHECK-NEXT: vcvtb.f32.f16 s16, s18
+; CHECK-NEXT: vmov q6[2], q6[0], r0, r7
+; CHECK-NEXT: vmov r0, s16
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: orr.w r1, r1, r2, lsl #4
-; CHECK-NEXT: vcmp.f32 s16, s18
+; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: vmov q6[3], q6[1], r1, r6
+; CHECK-NEXT: bl __aeabi_f2lz
+; CHECK-NEXT: vcmp.f32 s16, s30
+; CHECK-NEXT: vmov q3[2], q3[0], r10, r9
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: strd r0, r1, [r11, #16]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: mvnlt r3, #7
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: movlt.w r1, #-2147483648
+; CHECK-NEXT: vcmp.f32 s16, s28
+; CHECK-NEXT: vmov q3[3], q3[1], r11, r8
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r3, #7
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: mvngt r1, #-2147483648
+; CHECK-NEXT: movgt.w r0, #-1
; CHECK-NEXT: vcmp.f32 s16, s16
+; CHECK-NEXT: vmov q0, q5
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r3, #0
-; CHECK-NEXT: and r1, r3, #15
-; CHECK-NEXT: lsrl r2, r1, #28
-; CHECK-NEXT: strb.w r2, [r11, #24]
-; CHECK-NEXT: add sp, #32
+; CHECK-NEXT: itt vs
+; CHECK-NEXT: movvs r0, #0
+; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: vmov q2[2], q2[0], r0, r5
+; CHECK-NEXT: vmov q1, q6
+; CHECK-NEXT: vmov q2[3], q2[1], r1, r4
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
-; CHECK-NEXT: @ %bb.4:
- %x = call <8 x i100> @llvm.fptosi.sat.v8f16.v8i100(<8 x half> %f)
- ret <8 x i100> %x
+; CHECK-NEXT: .p2align 2
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI49_0:
+; CHECK-NEXT: .long 0xdf000000 @ float -9.22337203E+18
+; CHECK-NEXT: .LCPI49_1:
+; CHECK-NEXT: .long 0x5effffff @ float 9.22337149E+18
+ %x = call <8 x i64> @llvm.fptosi.sat.v8f16.v8i64(<8 x half> %f)
+ ret <8 x i64> %x
}
-define arm_aapcs_vfpcc <8 x i128> @test_signed_v8f16_v8i128(<8 x half> %f) {
-; CHECK-LABEL: test_signed_v8f16_v8i128:
+define arm_aapcs_vfpcc <8 x i100> @test_signed_v8f16_v8i100(<8 x half> %f) {
+; CHECK-LABEL: test_signed_v8f16_v8i100:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}
-; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
+; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4
-; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
+; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
+; CHECK-NEXT: .pad #56
+; CHECK-NEXT: sub sp, #56
; CHECK-NEXT: vmov q4, q0
-; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vcvtt.f32.f16 s28, s19
-; CHECK-NEXT: vcvtb.f32.f16 s20, s16
-; CHECK-NEXT: vmov r0, s28
+; CHECK-NEXT: mov r10, r0
; CHECK-NEXT: vcvtt.f32.f16 s24, s16
-; CHECK-NEXT: vcvtb.f32.f16 s26, s17
-; CHECK-NEXT: vcvtb.f32.f16 s19, s19
-; CHECK-NEXT: vldr s22, .LCPI51_2
-; CHECK-NEXT: vmov r8, s20
-; CHECK-NEXT: vmov r9, s24
-; CHECK-NEXT: vcvtt.f32.f16 s30, s18
-; CHECK-NEXT: vmov r7, s26
-; CHECK-NEXT: vmov r6, s19
+; CHECK-NEXT: vmov r0, s24
; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vldr s16, .LCPI51_3
-; CHECK-NEXT: vmov r5, s30
-; CHECK-NEXT: vcvtb.f32.f16 s18, s18
-; CHECK-NEXT: vcmp.f32 s28, s16
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s22
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r3, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s28
-; CHECK-NEXT: it gt
-; CHECK-NEXT: mvngt r3, #-2147483648
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s16
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r3, #0
+; CHECK-NEXT: vcvtt.f32.f16 s26, s17
+; CHECK-NEXT: mov r7, r0
+; CHECK-NEXT: vmov r0, s26
+; CHECK-NEXT: vldr s22, .LCPI50_0
+; CHECK-NEXT: vldr s20, .LCPI50_1
+; CHECK-NEXT: vcmp.f32 s24, s22
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s22
-; CHECK-NEXT: str r3, [r4, #124]
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: mvnlt r3, #7
; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: movlt r7, #0
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: vcmp.f32 s24, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s28
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: movgt.w r7, #-1
; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: movgt r3, #7
+; CHECK-NEXT: vcmp.f32 s24, s24
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s16
+; CHECK-NEXT: it vs
+; CHECK-NEXT: movvs r3, #0
+; CHECK-NEXT: str r3, [sp, #52] @ 4-byte Spill
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r2, #0
+; CHECK-NEXT: str r2, [sp, #48] @ 4-byte Spill
+; CHECK-NEXT: it vs
+; CHECK-NEXT: movvs r7, #0
+; CHECK-NEXT: str r7, [sp, #40] @ 4-byte Spill
+; CHECK-NEXT: it vs
+; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: str r1, [sp, #44] @ 4-byte Spill
+; CHECK-NEXT: bl __fixsfti
+; CHECK-NEXT: vcmp.f32 s26, s22
+; CHECK-NEXT: vcvtt.f32.f16 s24, s18
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s22
-; CHECK-NEXT: str r2, [r4, #120]
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: mvnlt r3, #7
+; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: vcmp.f32 s26, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s28
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt.w r0, #-1
; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: movgt r3, #7
+; CHECK-NEXT: vcmp.f32 s26, s26
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s16
+; CHECK-NEXT: it vs
+; CHECK-NEXT: movvs r3, #0
+; CHECK-NEXT: str r3, [sp, #36] @ 4-byte Spill
+; CHECK-NEXT: it vs
+; CHECK-NEXT: movvs r2, #0
+; CHECK-NEXT: str r2, [sp, #32] @ 4-byte Spill
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: str r1, [sp, #28] @ 4-byte Spill
+; CHECK-NEXT: it vs
+; CHECK-NEXT: movvs r0, #0
+; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill
+; CHECK-NEXT: vmov r0, s24
+; CHECK-NEXT: bl __fixsfti
+; CHECK-NEXT: vcmp.f32 s24, s22
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #116]
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: mvnlt r3, #7
+; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s28, s22
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: vcmp.f32 s24, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: vcmp.f32 s24, s24
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt.w r1, #-1
; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s28, s28
+; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: movgt r3, #7
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs
+; CHECK-NEXT: movvs r3, #0
+; CHECK-NEXT: str r3, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT: it vs
+; CHECK-NEXT: movvs r2, #0
+; CHECK-NEXT: str r2, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str r0, [r4, #112]
-; CHECK-NEXT: mov r0, r6
+; CHECK-NEXT: vcvtb.f32.f16 s24, s17
+; CHECK-NEXT: str r0, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT: vmov r0, s24
+; CHECK-NEXT: it vs
+; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: str r1, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vcmp.f32 s19, s16
-; CHECK-NEXT: vcvtt.f32.f16 s28, s17
+; CHECK-NEXT: vcvtb.f32.f16 s18, s18
+; CHECK-NEXT: mov r5, r0
+; CHECK-NEXT: vmov r0, s18
+; CHECK-NEXT: mov r8, r1
+; CHECK-NEXT: vcmp.f32 s24, s22
+; CHECK-NEXT: mov r6, r2
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s22
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r3, #-2147483648
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: mvnlt r3, #7
+; CHECK-NEXT: movlt r5, #0
+; CHECK-NEXT: movlt.w r8, #0
+; CHECK-NEXT: movlt r6, #0
+; CHECK-NEXT: vcmp.f32 s24, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s19
-; CHECK-NEXT: it gt
-; CHECK-NEXT: mvngt r3, #-2147483648
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt.w r6, #-1
+; CHECK-NEXT: movgt.w r8, #-1
+; CHECK-NEXT: movgt.w r5, #-1
+; CHECK-NEXT: movgt r3, #7
+; CHECK-NEXT: vcmp.f32 s24, s24
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s16
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r3, #0
+; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: ittt vs
+; CHECK-NEXT: movvs r5, #0
+; CHECK-NEXT: movvs.w r8, #0
+; CHECK-NEXT: movvs r6, #0
+; CHECK-NEXT: bl __fixsfti
+; CHECK-NEXT: vcmp.f32 s18, s22
+; CHECK-NEXT: mov r7, r0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s22
-; CHECK-NEXT: str r3, [r4, #108]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: mov r11, r1
+; CHECK-NEXT: mov r4, r2
+; CHECK-NEXT: vcmp.f32 s18, s20
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: mvnlt r3, #7
+; CHECK-NEXT: movlt r7, #0
+; CHECK-NEXT: movlt.w r11, #0
+; CHECK-NEXT: movlt r4, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s19
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: vcmp.f32 s18, s18
+; CHECK-NEXT: vcvtb.f32.f16 s18, s19
+; CHECK-NEXT: vmov r0, s18
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt.w r4, #-1
+; CHECK-NEXT: movgt.w r11, #-1
+; CHECK-NEXT: movgt.w r7, #-1
+; CHECK-NEXT: movgt r3, #7
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s16
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r2, #0
+; CHECK-NEXT: movvs r3, #0
+; CHECK-NEXT: str r3, [sp] @ 4-byte Spill
+; CHECK-NEXT: ittt vs
+; CHECK-NEXT: movvs r7, #0
+; CHECK-NEXT: movvs.w r11, #0
+; CHECK-NEXT: movvs r4, #0
+; CHECK-NEXT: bl __fixsfti
+; CHECK-NEXT: vcmp.f32 s18, s22
+; CHECK-NEXT: mov r9, r3
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s22
-; CHECK-NEXT: str r2, [r4, #104]
-; CHECK-NEXT: it lt
+; CHECK-NEXT: vcmp.f32 s18, s20
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: mvnlt r9, #7
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s19
-; CHECK-NEXT: it gt
+; CHECK-NEXT: vcmp.f32 s18, s18
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt.w r9, #7
+; CHECK-NEXT: movgt.w r0, #-1
; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: movgt.w r2, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s16
+; CHECK-NEXT: it vs
+; CHECK-NEXT: movvs r2, #0
+; CHECK-NEXT: str.w r2, [r10, #83]
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #100]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s19, s22
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s19, s19
+; CHECK-NEXT: str.w r1, [r10, #79]
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str r0, [r4, #96]
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: vmov r6, s18
+; CHECK-NEXT: vcvtt.f32.f16 s18, s19
+; CHECK-NEXT: str.w r0, [r10, #75]
+; CHECK-NEXT: vmov r0, s18
+; CHECK-NEXT: str.w r4, [r10, #58]
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: str.w r11, [r10, #54]
+; CHECK-NEXT: str.w r7, [r10, #50]
+; CHECK-NEXT: str.w r6, [r10, #33]
+; CHECK-NEXT: str.w r8, [r10, #29]
+; CHECK-NEXT: str.w r5, [r10, #25]
+; CHECK-NEXT: it vs
+; CHECK-NEXT: movvs.w r9, #0
; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vcmp.f32 s30, s16
+; CHECK-NEXT: vcvtb.f32.f16 s16, s16
+; CHECK-NEXT: mov r5, r0
+; CHECK-NEXT: vmov r0, s16
+; CHECK-NEXT: mov r7, r1
+; CHECK-NEXT: vcmp.f32 s18, s22
+; CHECK-NEXT: mov r6, r2
+; CHECK-NEXT: mov r4, r3
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s22
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r3, #-2147483648
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: mvnlt r4, #7
+; CHECK-NEXT: movlt r6, #0
+; CHECK-NEXT: movlt r7, #0
+; CHECK-NEXT: movlt r5, #0
+; CHECK-NEXT: vcmp.f32 s18, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s30
-; CHECK-NEXT: it gt
-; CHECK-NEXT: mvngt r3, #-2147483648
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt.w r5, #-1
+; CHECK-NEXT: movgt.w r7, #-1
+; CHECK-NEXT: movgt.w r6, #-1
+; CHECK-NEXT: movgt r4, #7
+; CHECK-NEXT: vcmp.f32 s18, s18
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s16
-; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r3, #0
+; CHECK-NEXT: itttt vs
+; CHECK-NEXT: movvs r4, #0
+; CHECK-NEXT: movvs r6, #0
+; CHECK-NEXT: movvs r7, #0
+; CHECK-NEXT: movvs r5, #0
+; CHECK-NEXT: bl __fixsfti
+; CHECK-NEXT: vcmp.f32 s16, s22
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s22
-; CHECK-NEXT: str r3, [r4, #92]
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itttt lt
; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: mvnlt r3, #7
+; CHECK-NEXT: vcmp.f32 s16, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s30
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt r3, #7
+; CHECK-NEXT: movgt.w r0, #-1
+; CHECK-NEXT: movgt.w r1, #-1
; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: vcmp.f32 s16, s16
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s16
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s22
-; CHECK-NEXT: str r2, [r4, #88]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s30
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s16
+; CHECK-NEXT: str.w r2, [r10, #8]
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #84]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s30, s22
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s30, s30
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: str.w r1, [r10, #4]
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str r0, [r4, #80]
-; CHECK-NEXT: mov r0, r6
+; CHECK-NEXT: str.w r0, [r10]
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: lsrl r0, r7, #28
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: orr.w r1, r7, r6, lsl #4
+; CHECK-NEXT: str.w r1, [r10, #95]
+; CHECK-NEXT: and r1, r4, #15
+; CHECK-NEXT: str.w r0, [r10, #91]
+; CHECK-NEXT: and r0, r9, #15
+; CHECK-NEXT: lsrl r6, r1, #28
+; CHECK-NEXT: strb.w r6, [r10, #99]
+; CHECK-NEXT: orr.w r0, r0, r5, lsl #4
+; CHECK-NEXT: str.w r0, [r10, #87]
+; CHECK-NEXT: ldr r7, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
+; CHECK-NEXT: ldr r2, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: lsrl r0, r1, #28
+; CHECK-NEXT: orr.w r1, r1, r2, lsl #4
+; CHECK-NEXT: str.w r1, [r10, #70]
+; CHECK-NEXT: str.w r0, [r10, #66]
+; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: and r1, r0, #15
+; CHECK-NEXT: lsrl r2, r1, #28
+; CHECK-NEXT: strb.w r2, [r10, #74]
+; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
+; CHECK-NEXT: and r0, r0, #15
+; CHECK-NEXT: orr.w r0, r0, r7, lsl #4
+; CHECK-NEXT: str.w r0, [r10, #62]
+; CHECK-NEXT: ldr r7, [sp, #24] @ 4-byte Reload
+; CHECK-NEXT: ldr r1, [sp, #28] @ 4-byte Reload
+; CHECK-NEXT: ldr r2, [sp, #32] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: lsrl r0, r1, #28
+; CHECK-NEXT: orr.w r1, r1, r2, lsl #4
+; CHECK-NEXT: str.w r1, [r10, #45]
+; CHECK-NEXT: str.w r0, [r10, #41]
+; CHECK-NEXT: ldr r0, [sp, #36] @ 4-byte Reload
+; CHECK-NEXT: and r1, r0, #15
+; CHECK-NEXT: lsrl r2, r1, #28
+; CHECK-NEXT: strb.w r2, [r10, #49]
+; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: and r0, r0, #15
+; CHECK-NEXT: orr.w r0, r0, r7, lsl #4
+; CHECK-NEXT: str.w r0, [r10, #37]
+; CHECK-NEXT: ldr r7, [sp, #40] @ 4-byte Reload
+; CHECK-NEXT: ldr r1, [sp, #44] @ 4-byte Reload
+; CHECK-NEXT: ldr r2, [sp, #48] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: lsrl r0, r1, #28
+; CHECK-NEXT: orr.w r1, r1, r2, lsl #4
+; CHECK-NEXT: strd r0, r1, [r10, #16]
+; CHECK-NEXT: ldr r0, [sp, #52] @ 4-byte Reload
+; CHECK-NEXT: and r1, r0, #15
+; CHECK-NEXT: lsrl r2, r1, #28
+; CHECK-NEXT: strb.w r2, [r10, #24]
+; CHECK-NEXT: it vs
+; CHECK-NEXT: movvs r3, #0
+; CHECK-NEXT: and r0, r3, #15
+; CHECK-NEXT: orr.w r0, r0, r7, lsl #4
+; CHECK-NEXT: str.w r0, [r10, #12]
+; CHECK-NEXT: add sp, #56
+; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
+; CHECK-NEXT: add sp, #4
+; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
+; CHECK-NEXT: .p2align 2
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI50_0:
+; CHECK-NEXT: .long 0xf1000000 @ float -6.338253E+29
+; CHECK-NEXT: .LCPI50_1:
+; CHECK-NEXT: .long 0x70ffffff @ float 6.33825262E+29
+ %x = call <8 x i100> @llvm.fptosi.sat.v8f16.v8i100(<8 x half> %f)
+ ret <8 x i100> %x
+}
+
+define arm_aapcs_vfpcc <8 x i128> @test_signed_v8f16_v8i128(<8 x half> %f) {
+; CHECK-LABEL: test_signed_v8f16_v8i128:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: .save {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, lr}
+; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-NEXT: vmov q4, q0
+; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vcvtt.f32.f16 s26, s19
+; CHECK-NEXT: vcvtb.f32.f16 s28, s19
+; CHECK-NEXT: vmov r0, s26
+; CHECK-NEXT: vcvtb.f32.f16 s24, s17
+; CHECK-NEXT: vldr s20, .LCPI51_0
; CHECK-NEXT: vmov r5, s28
+; CHECK-NEXT: vmov r8, s24
+; CHECK-NEXT: vcvtt.f32.f16 s30, s18
; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vcmp.f32 s18, s16
+; CHECK-NEXT: vldr s22, .LCPI51_1
+; CHECK-NEXT: add.w r12, r4, #112
+; CHECK-NEXT: vmov r6, s30
+; CHECK-NEXT: vcmp.f32 s26, s22
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s22
-; CHECK-NEXT: it lt
+; CHECK-NEXT: vcmp.f32 s26, s20
+; CHECK-NEXT: itttt lt
; CHECK-NEXT: movlt.w r3, #-2147483648
+; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s18
-; CHECK-NEXT: it gt
+; CHECK-NEXT: vcmp.f32 s26, s26
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt.w r0, #-1
+; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: movgt.w r2, #-1
; CHECK-NEXT: mvngt r3, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s16
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s22
-; CHECK-NEXT: str r3, [r4, #76]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s18
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s16
-; CHECK-NEXT: it vs
+; CHECK-NEXT: ittt vs
; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s22
-; CHECK-NEXT: str r2, [r4, #72]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s18
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s16
-; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #68]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s18, s22
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s18, s18
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str r0, [r4, #64]
+; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: vcvtb.f32.f16 s26, s18
; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vcmp.f32 s28, s16
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s28, s22
-; CHECK-NEXT: it lt
+; CHECK-NEXT: add.w r12, r4, #96
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vcmp.f32 s28, s20
+; CHECK-NEXT: itttt lt
; CHECK-NEXT: movlt.w r3, #-2147483648
+; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s28, s28
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt.w r0, #-1
+; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: movgt.w r2, #-1
; CHECK-NEXT: mvngt r3, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s16
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s22
-; CHECK-NEXT: str r3, [r4, #60]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s28
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s16
-; CHECK-NEXT: it vs
+; CHECK-NEXT: ittt vs
; CHECK-NEXT: movvs r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s22
-; CHECK-NEXT: str r2, [r4, #56]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s28
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s16
-; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: movvs r0, #0
+; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
+; CHECK-NEXT: mov r0, r6
+; CHECK-NEXT: vmov r7, s26
+; CHECK-NEXT: vcvtt.f32.f16 s28, s17
+; CHECK-NEXT: bl __fixsfti
+; CHECK-NEXT: vcmp.f32 s30, s22
+; CHECK-NEXT: add.w r12, r4, #80
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #52]
-; CHECK-NEXT: it lt
+; CHECK-NEXT: vcmp.f32 s30, s20
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt.w r3, #-2147483648
+; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: movlt r1, #0
; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s28, s22
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: vcmp.f32 s30, s30
+; CHECK-NEXT: itttt gt
; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s28, s28
+; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: mvngt r3, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs
+; CHECK-NEXT: movvs r3, #0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: ittt vs
+; CHECK-NEXT: movvs r2, #0
+; CHECK-NEXT: movvs r1, #0
; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str r0, [r4, #48]
+; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: vmov r5, s28
+; CHECK-NEXT: vcvtt.f32.f16 s18, s16
; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vcmp.f32 s26, s16
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s26, s22
-; CHECK-NEXT: it lt
+; CHECK-NEXT: add.w r12, r4, #64
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vcmp.f32 s26, s20
+; CHECK-NEXT: itttt lt
; CHECK-NEXT: movlt.w r3, #-2147483648
+; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s26, s26
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt.w r0, #-1
+; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: movgt.w r2, #-1
; CHECK-NEXT: mvngt r3, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s16
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r3, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s22
-; CHECK-NEXT: str r3, [r4, #44]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s26
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s16
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s22
-; CHECK-NEXT: str r2, [r4, #40]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s26
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s16
-; CHECK-NEXT: b.w .LBB51_3
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI51_2:
-; CHECK-NEXT: .long 0x7effffff @ float 1.70141173E+38
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.2:
-; CHECK-NEXT: .LCPI51_3:
-; CHECK-NEXT: .long 0xff000000 @ float -1.70141183E+38
-; CHECK-NEXT: .p2align 1
-; CHECK-NEXT: .LBB51_3:
-; CHECK-NEXT: it vs
+; CHECK-NEXT: itt vs
; CHECK-NEXT: movvs r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #36]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s26, s22
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s26, s26
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str r0, [r4, #32]
-; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: vcvtb.f32.f16 s16, s16
+; CHECK-NEXT: vmov r6, s18
; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vcmp.f32 s24, s16
+; CHECK-NEXT: vcmp.f32 s28, s22
+; CHECK-NEXT: add.w r12, r4, #48
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, s22
-; CHECK-NEXT: it lt
+; CHECK-NEXT: vcmp.f32 s28, s20
+; CHECK-NEXT: itttt lt
; CHECK-NEXT: movlt.w r3, #-2147483648
+; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, s24
-; CHECK-NEXT: it gt
+; CHECK-NEXT: vcmp.f32 s28, s28
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt.w r0, #-1
+; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: movgt.w r2, #-1
; CHECK-NEXT: mvngt r3, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, s16
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r3, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, s22
-; CHECK-NEXT: str r3, [r4, #28]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, s24
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, s16
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: itt vs
+; CHECK-NEXT: movvs r1, #0
+; CHECK-NEXT: movvs r0, #0
+; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
+; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: vmov r7, s16
+; CHECK-NEXT: bl __fixsfti
; CHECK-NEXT: vcmp.f32 s24, s22
-; CHECK-NEXT: str r2, [r4, #24]
-; CHECK-NEXT: it lt
+; CHECK-NEXT: add.w r12, r4, #32
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vcmp.f32 s24, s20
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt.w r3, #-2147483648
+; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s24, s24
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt.w r0, #-1
; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: mvngt r3, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, s16
-; CHECK-NEXT: it vs
+; CHECK-NEXT: ittt vs
+; CHECK-NEXT: movvs r3, #0
+; CHECK-NEXT: movvs r2, #0
; CHECK-NEXT: movvs r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #20]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s24, s22
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s24, s24
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str r0, [r4, #16]
-; CHECK-NEXT: mov r0, r8
+; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
+; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: vcmp.f32 s20, s16
+; CHECK-NEXT: vcmp.f32 s18, s22
+; CHECK-NEXT: add.w r12, r4, #16
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s20, s22
-; CHECK-NEXT: it lt
+; CHECK-NEXT: vcmp.f32 s18, s20
+; CHECK-NEXT: itttt lt
; CHECK-NEXT: movlt.w r3, #-2147483648
+; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s20, s20
-; CHECK-NEXT: it gt
+; CHECK-NEXT: vcmp.f32 s18, s18
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt.w r0, #-1
+; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: movgt.w r2, #-1
; CHECK-NEXT: mvngt r3, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s20, s16
-; CHECK-NEXT: it vs
+; CHECK-NEXT: ittt vs
; CHECK-NEXT: movvs r3, #0
+; CHECK-NEXT: movvs r2, #0
+; CHECK-NEXT: movvs r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s20, s22
-; CHECK-NEXT: str r3, [r4, #12]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s20, s20
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s20, s16
; CHECK-NEXT: it vs
-; CHECK-NEXT: movvs r2, #0
+; CHECK-NEXT: movvs r0, #0
+; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: bl __fixsfti
+; CHECK-NEXT: vcmp.f32 s16, s22
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s20, s22
-; CHECK-NEXT: str r2, [r4, #8]
-; CHECK-NEXT: it lt
+; CHECK-NEXT: vcmp.f32 s16, s20
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt.w r3, #-2147483648
+; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s20, s20
-; CHECK-NEXT: it gt
+; CHECK-NEXT: vcmp.f32 s16, s16
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt.w r0, #-1
; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: mvngt r3, #-2147483648
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s20, s16
-; CHECK-NEXT: it vs
+; CHECK-NEXT: ittt vs
+; CHECK-NEXT: movvs r3, #0
+; CHECK-NEXT: movvs r2, #0
; CHECK-NEXT: movvs r1, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #4]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s20, s22
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s20, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it vs
; CHECK-NEXT: movvs r0, #0
-; CHECK-NEXT: str r0, [r4]
+; CHECK-NEXT: stm r4!, {r0, r1, r2, r3}
; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: add sp, #4
-; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
-; CHECK-NEXT: @ %bb.4:
+; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, pc}
+; CHECK-NEXT: .p2align 2
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI51_0:
+; CHECK-NEXT: .long 0x7effffff @ float 1.70141173E+38
+; CHECK-NEXT: .LCPI51_1:
+; CHECK-NEXT: .long 0xff000000 @ float -1.70141183E+38
%x = call <8 x i128> @llvm.fptosi.sat.v8f16.v8i128(<8 x half> %f)
ret <8 x i128> %x
}
diff --git a/llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll b/llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
index 5ab184a066e497..13609bd1903f2d 100644
--- a/llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
@@ -39,40 +39,28 @@ define arm_aapcs_vfpcc <2 x i32> @test_unsigned_v2f32_v2i32(<2 x float> %f) {
; CHECK-NEXT: vmov r0, s16
; CHECK-NEXT: vldr s18, .LCPI1_0
; CHECK-NEXT: vcmp.f32 s17, #0
+; CHECK-NEXT: mov r4, r1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
; CHECK-NEXT: movlt r5, #0
+; CHECK-NEXT: movlt r4, #0
; CHECK-NEXT: vcmp.f32 s17, s18
-; CHECK-NEXT: mov r4, r1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: movgt r4, #0
; CHECK-NEXT: movgt.w r5, #-1
; CHECK-NEXT: bl __aeabi_f2ulz
; CHECK-NEXT: vcmp.f32 s16, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s18
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s18
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r4, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r4, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r0, #0
; CHECK-NEXT: vcmp.f32 s16, s18
-; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: movgt.w r0, #-1
; CHECK-NEXT: movgt r1, #0
+; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
; CHECK-NEXT: vmov q0[3], q0[1], r1, r4
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: pop {r4, r5, r7, pc}
@@ -1059,38 +1047,26 @@ define arm_aapcs_vfpcc <2 x i32> @test_unsigned_v2f16_v2i32(<2 x half> %f) {
; CHECK-NEXT: vcmp.f32 s18, #0
; CHECK-NEXT: mov r4, r1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
; CHECK-NEXT: movlt r5, #0
+; CHECK-NEXT: movlt r4, #0
; CHECK-NEXT: vcmp.f32 s18, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: movgt r4, #0
; CHECK-NEXT: movgt.w r5, #-1
; CHECK-NEXT: bl __aeabi_f2ulz
; CHECK-NEXT: vcmp.f32 s16, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r4, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r4, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r0, #0
; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: movgt.w r0, #-1
; CHECK-NEXT: movgt r1, #0
+; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
; CHECK-NEXT: vmov q0[3], q0[1], r1, r4
; CHECK-NEXT: vpop {d8, d9, d10}
; CHECK-NEXT: pop {r4, r5, r7, pc}
@@ -1504,112 +1480,91 @@ define arm_aapcs_vfpcc <4 x i50> @test_unsigned_v4f32_v4i50(<4 x float> %f) {
; CHECK-NEXT: .vsave {d8, d9, d10}
; CHECK-NEXT: vpush {d8, d9, d10}
; CHECK-NEXT: vmov q4, q0
-; CHECK-NEXT: mov r8, r0
-; CHECK-NEXT: vmov r0, s16
-; CHECK-NEXT: bl __aeabi_f2ulz
-; CHECK-NEXT: mov r6, r0
+; CHECK-NEXT: mov r9, r0
; CHECK-NEXT: vmov r0, s18
-; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: mov r9, r1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vmov r4, s19
-; CHECK-NEXT: vldr s20, .LCPI28_0
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r6, #0
; CHECK-NEXT: bl __aeabi_f2ulz
+; CHECK-NEXT: mov r8, r0
+; CHECK-NEXT: vmov r0, s19
+; CHECK-NEXT: vldr s20, .LCPI28_0
; CHECK-NEXT: vcmp.f32 s18, #0
-; CHECK-NEXT: mov r5, r1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: mov r10, r0
-; CHECK-NEXT: mov r0, r4
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r5, #0
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt gt
-; CHECK-NEXT: movwgt r5, #65535
-; CHECK-NEXT: movtgt r5, #3
-; CHECK-NEXT: bl __aeabi_f2ulz
-; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vmov r0, s17
-; CHECK-NEXT: vcmp.f32 s19, #0
; CHECK-NEXT: mov r7, r1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt.w r8, #0
; CHECK-NEXT: movlt r7, #0
+; CHECK-NEXT: vcmp.f32 s18, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: itt gt
+; CHECK-NEXT: vmov r5, s16
+; CHECK-NEXT: ittt gt
; CHECK-NEXT: movwgt r7, #65535
; CHECK-NEXT: movtgt r7, #3
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: movgt.w r8, #-1
+; CHECK-NEXT: bl __aeabi_f2ulz
+; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: vcmp.f32 s19, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r6, #-1
+; CHECK-NEXT: mov r10, r1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: str.w r6, [r8]
-; CHECK-NEXT: it lt
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt.w r10, #0
; CHECK-NEXT: movlt r4, #0
+; CHECK-NEXT: vcmp.f32 s19, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, #0
-; CHECK-NEXT: mov r1, r7
-; CHECK-NEXT: it gt
+; CHECK-NEXT: ittt gt
+; CHECK-NEXT: movwgt r10, #65535
+; CHECK-NEXT: movtgt r10, #3
; CHECK-NEXT: movgt.w r4, #-1
+; CHECK-NEXT: bl __aeabi_f2ulz
+; CHECK-NEXT: mov r5, r1
+; CHECK-NEXT: vcmp.f32 s16, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r10, #0
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: bfc r1, #18, #14
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: movlt r5, #0
+; CHECK-NEXT: vcmp.f32 s16, s20
+; CHECK-NEXT: mov r1, r10
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r10, #-1
-; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: bfc r5, #18, #14
-; CHECK-NEXT: mov r6, r10
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: movgt.w r0, #-1
+; CHECK-NEXT: str.w r0, [r9]
+; CHECK-NEXT: vmov r0, s17
+; CHECK-NEXT: bfc r1, #18, #14
+; CHECK-NEXT: bfc r7, #18, #14
+; CHECK-NEXT: mov r6, r8
; CHECK-NEXT: lsll r4, r1, #22
-; CHECK-NEXT: lsrl r6, r5, #28
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r9, #0
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: orrs r1, r5
+; CHECK-NEXT: lsrl r6, r7, #28
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: itt gt
-; CHECK-NEXT: movwgt r9, #65535
-; CHECK-NEXT: movtgt r9, #3
-; CHECK-NEXT: str.w r1, [r8, #20]
+; CHECK-NEXT: movwgt r5, #65535
+; CHECK-NEXT: movtgt r5, #3
+; CHECK-NEXT: orrs r1, r7
+; CHECK-NEXT: str.w r1, [r9, #20]
; CHECK-NEXT: bl __aeabi_f2ulz
; CHECK-NEXT: vcmp.f32 s17, #0
; CHECK-NEXT: orr.w r2, r6, r4
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt r0, #0
; CHECK-NEXT: movlt r1, #0
; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: bfc r9, #18, #14
+; CHECK-NEXT: bfc r5, #18, #14
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: itt gt
; CHECK-NEXT: movwgt r1, #65535
; CHECK-NEXT: movtgt r1, #3
-; CHECK-NEXT: str.w r2, [r8, #16]
-; CHECK-NEXT: lsrs r2, r7, #10
-; CHECK-NEXT: vcmp.f32 s17, #0
-; CHECK-NEXT: strb.w r2, [r8, #24]
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: bfc r1, #18, #14
+; CHECK-NEXT: str.w r2, [r9, #16]
+; CHECK-NEXT: lsr.w r2, r10, #10
+; CHECK-NEXT: strb.w r2, [r9, #24]
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1
; CHECK-NEXT: mov r2, r0
-; CHECK-NEXT: orr.w r0, r9, r0, lsl #18
+; CHECK-NEXT: bfc r1, #18, #14
+; CHECK-NEXT: orr.w r0, r5, r0, lsl #18
; CHECK-NEXT: lsrl r2, r1, #14
-; CHECK-NEXT: orr.w r1, r1, r10, lsl #4
-; CHECK-NEXT: strd r2, r1, [r8, #8]
-; CHECK-NEXT: str.w r0, [r8, #4]
+; CHECK-NEXT: orr.w r1, r1, r8, lsl #4
+; CHECK-NEXT: strd r2, r1, [r9, #8]
+; CHECK-NEXT: str.w r0, [r9, #4]
; CHECK-NEXT: vpop {d8, d9, d10}
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, pc}
; CHECK-NEXT: .p2align 2
@@ -1636,85 +1591,61 @@ define arm_aapcs_vfpcc <4 x i64> @test_unsigned_v4f32_v4i64(<4 x float> %f) {
; CHECK-NEXT: vmov r0, s18
; CHECK-NEXT: vldr s20, .LCPI29_0
; CHECK-NEXT: vcmp.f32 s19, #0
+; CHECK-NEXT: mov r10, r1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
; CHECK-NEXT: movlt.w r11, #0
+; CHECK-NEXT: movlt.w r10, #0
; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: mov r10, r1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vmov r9, s17
; CHECK-NEXT: vmov r8, s16
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: movgt.w r10, #-1
; CHECK-NEXT: movgt.w r11, #-1
; CHECK-NEXT: bl __aeabi_f2ulz
-; CHECK-NEXT: vcmp.f32 s18, #0
; CHECK-NEXT: mov r7, r0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r7, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r7, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r10, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: mov r6, r1
; CHECK-NEXT: vcmp.f32 s18, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r10, #-1
+; CHECK-NEXT: mov r6, r1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: mov r0, r9
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
; CHECK-NEXT: movlt r6, #0
+; CHECK-NEXT: movlt r7, #0
; CHECK-NEXT: vcmp.f32 s18, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: movgt.w r7, #-1
; CHECK-NEXT: movgt.w r6, #-1
; CHECK-NEXT: bl __aeabi_f2ulz
; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: vcmp.f32 s17, #0
+; CHECK-NEXT: mov r4, r1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: mov r0, r8
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
; CHECK-NEXT: movlt r5, #0
+; CHECK-NEXT: movlt r4, #0
; CHECK-NEXT: vcmp.f32 s17, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: mov r4, r1
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: movgt.w r4, #-1
; CHECK-NEXT: movgt.w r5, #-1
; CHECK-NEXT: bl __aeabi_f2ulz
; CHECK-NEXT: vcmp.f32 s16, #0
; CHECK-NEXT: vmov q1[2], q1[0], r7, r11
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r4, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r4, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r0, #0
; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
+; CHECK-NEXT: vmov q1[3], q1[1], r6, r10
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: movgt.w r0, #-1
; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: vmov q0[2], q0[0], r0, r5
; CHECK-NEXT: vmov q0[3], q0[1], r1, r4
-; CHECK-NEXT: vmov q1[3], q1[1], r6, r10
; CHECK-NEXT: vpop {d8, d9, d10}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
@@ -1735,179 +1666,125 @@ define arm_aapcs_vfpcc <4 x i100> @test_unsigned_v4f32_v4i100(<4 x float> %f) {
; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: .vsave {d8, d9, d10}
; CHECK-NEXT: vpush {d8, d9, d10}
+; CHECK-NEXT: .pad #8
+; CHECK-NEXT: sub sp, #8
; CHECK-NEXT: vmov q4, q0
-; CHECK-NEXT: mov r8, r0
-; CHECK-NEXT: vmov r0, s18
+; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vmov r0, s17
; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: mov r9, r3
-; CHECK-NEXT: vmov r3, s16
+; CHECK-NEXT: mov r5, r0
+; CHECK-NEXT: vmov r0, s18
; CHECK-NEXT: vldr s20, .LCPI30_0
+; CHECK-NEXT: vcmp.f32 s17, #0
+; CHECK-NEXT: mov r7, r1
+; CHECK-NEXT: mov r6, r2
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt r5, #0
+; CHECK-NEXT: movlt r7, #0
+; CHECK-NEXT: movlt r6, #0
+; CHECK-NEXT: movlt r3, #0
+; CHECK-NEXT: vcmp.f32 s17, s20
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: it gt
+; CHECK-NEXT: movgt r3, #15
+; CHECK-NEXT: str r3, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: ittt gt
+; CHECK-NEXT: movgt.w r6, #-1
+; CHECK-NEXT: movgt.w r7, #-1
+; CHECK-NEXT: movgt.w r5, #-1
+; CHECK-NEXT: str r5, [sp] @ 4-byte Spill
+; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: vcmp.f32 s18, #0
+; CHECK-NEXT: mov r10, r3
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt.w r10, #0
+; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: movlt r1, #0
; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: vcmp.f32 s18, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, #0
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: str.w r2, [r8, #33]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, #0
+; CHECK-NEXT: str.w r2, [r4, #33]
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str.w r1, [r8, #29]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s18, s20
+; CHECK-NEXT: str.w r1, [r4, #29]
+; CHECK-NEXT: vmov r1, s19
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: str.w r0, [r8, #25]
-; CHECK-NEXT: vmov r7, s17
-; CHECK-NEXT: vmov r4, s19
-; CHECK-NEXT: mov r0, r3
-; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: mov r10, r3
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, #0
+; CHECK-NEXT: str.w r0, [r4, #25]
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: movgt.w r10, #15
+; CHECK-NEXT: mov r0, r1
+; CHECK-NEXT: bl __fixunssfti
+; CHECK-NEXT: mov r5, r0
+; CHECK-NEXT: vmov r0, s16
+; CHECK-NEXT: vcmp.f32 s19, #0
+; CHECK-NEXT: mov r9, r1
+; CHECK-NEXT: mov r8, r2
+; CHECK-NEXT: mov r11, r3
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: str.w r2, [r8, #8]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt.w r9, #0
+; CHECK-NEXT: movlt r5, #0
+; CHECK-NEXT: movlt.w r8, #0
+; CHECK-NEXT: movlt.w r11, #0
+; CHECK-NEXT: vcmp.f32 s19, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt.w r11, #15
+; CHECK-NEXT: movgt.w r8, #-1
+; CHECK-NEXT: movgt.w r5, #-1
+; CHECK-NEXT: movgt.w r9, #-1
+; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r1, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str.w r1, [r8, #4]
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt r3, #0
; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: vcmp.f32 s16, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: str.w r0, [r8]
-; CHECK-NEXT: mov r0, r4
-; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: vcmp.f32 s19, #0
-; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r4, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r4, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r9, #0
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: mov r5, r1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r9, #15
-; CHECK-NEXT: and r0, r9, #15
-; CHECK-NEXT: mov r6, r2
-; CHECK-NEXT: orr.w r0, r0, r4, lsl #4
-; CHECK-NEXT: str.w r0, [r8, #37]
-; CHECK-NEXT: mov r0, r7
-; CHECK-NEXT: mov r11, r3
-; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: vcmp.f32 s17, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r10, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r10, #15
-; CHECK-NEXT: and r7, r10, #15
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: orr.w r7, r7, r0, lsl #4
-; CHECK-NEXT: str.w r7, [r8, #12]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r5, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r5, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r6, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: lsrl r4, r5, #28
-; CHECK-NEXT: vcmp.f32 s19, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r6, #-1
-; CHECK-NEXT: orr.w r7, r5, r6, lsl #4
-; CHECK-NEXT: str.w r7, [r8, #45]
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str.w r4, [r8, #41]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r11, #0
-; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r11, #15
-; CHECK-NEXT: and r5, r11, #15
-; CHECK-NEXT: vcmp.f32 s17, #0
-; CHECK-NEXT: lsrl r6, r5, #28
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: strb.w r6, [r8, #49]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: str r2, [r4, #8]
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vcmp.f32 s17, #0
-; CHECK-NEXT: lsrl r0, r1, #28
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: str r1, [r4, #4]
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: orr.w r1, r1, r2, lsl #4
-; CHECK-NEXT: vcmp.f32 s17, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: strd r0, r1, [r8, #16]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r3, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: movgt.w r0, #-1
+; CHECK-NEXT: str r0, [r4]
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: lsrl r0, r9, #28
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: orr.w r1, r9, r8, lsl #4
+; CHECK-NEXT: str.w r1, [r4, #45]
+; CHECK-NEXT: and r1, r11, #15
+; CHECK-NEXT: str.w r0, [r4, #41]
+; CHECK-NEXT: and r0, r10, #15
+; CHECK-NEXT: lsrl r8, r1, #28
+; CHECK-NEXT: strb.w r8, [r4, #49]
+; CHECK-NEXT: orr.w r0, r0, r5, lsl #4
+; CHECK-NEXT: str.w r0, [r4, #37]
+; CHECK-NEXT: ldr r2, [sp] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r2
+; CHECK-NEXT: lsrl r0, r7, #28
+; CHECK-NEXT: orr.w r1, r7, r6, lsl #4
+; CHECK-NEXT: strd r0, r1, [r4, #16]
+; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: and r1, r0, #15
+; CHECK-NEXT: lsrl r6, r1, #28
+; CHECK-NEXT: strb r6, [r4, #24]
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt r3, #15
-; CHECK-NEXT: and r1, r3, #15
-; CHECK-NEXT: lsrl r2, r1, #28
-; CHECK-NEXT: strb.w r2, [r8, #24]
+; CHECK-NEXT: and r0, r3, #15
+; CHECK-NEXT: orr.w r0, r0, r2, lsl #4
+; CHECK-NEXT: str r0, [r4, #12]
+; CHECK-NEXT: add sp, #8
; CHECK-NEXT: vpop {d8, d9, d10}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
@@ -1932,160 +1809,87 @@ define arm_aapcs_vfpcc <4 x i128> @test_unsigned_v4f32_v4i128(<4 x float> %f) {
; CHECK-NEXT: mov r4, r0
; CHECK-NEXT: vmov r0, s19
; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: vmov r5, s18
+; CHECK-NEXT: mov r5, r0
+; CHECK-NEXT: vmov r0, s18
; CHECK-NEXT: vldr s20, .LCPI31_0
; CHECK-NEXT: vcmp.f32 s19, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt r5, #0
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: movlt r3, #0
+; CHECK-NEXT: vcmp.f32 s19, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, #0
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r3, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: str r3, [r4, #60]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, #0
-; CHECK-NEXT: it gt
+; CHECK-NEXT: ittt gt
; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: str r2, [r4, #56]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s19, #0
-; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #52]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s19, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: str r0, [r4, #48]
-; CHECK-NEXT: vmov r7, s16
+; CHECK-NEXT: movgt.w r5, #-1
+; CHECK-NEXT: strd r5, r1, [r4, #48]
; CHECK-NEXT: vmov r6, s17
-; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: vmov r7, s16
+; CHECK-NEXT: strd r2, r3, [r4, #56]
; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: vcmp.f32 s18, #0
+; CHECK-NEXT: add.w r12, r4, #32
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: movlt r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, #0
-; CHECK-NEXT: it gt
+; CHECK-NEXT: ittt gt
; CHECK-NEXT: movgt.w r3, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: str r3, [r4, #44]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, #0
-; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: str r2, [r4, #40]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, #0
-; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #36]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: str r0, [r4, #32]
+; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: vcmp.f32 s17, #0
+; CHECK-NEXT: add.w r12, r4, #16
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: movlt r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, #0
-; CHECK-NEXT: it gt
+; CHECK-NEXT: ittt gt
; CHECK-NEXT: movgt.w r3, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: str r3, [r4, #28]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, #0
-; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: str r2, [r4, #24]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, #0
-; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #20]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s17, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: str r0, [r4, #16]
+; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
; CHECK-NEXT: mov r0, r7
; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: vcmp.f32 s16, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: movlt r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: it gt
+; CHECK-NEXT: ittt gt
; CHECK-NEXT: movgt.w r3, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: str r3, [r4, #12]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: str r2, [r4, #8]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #4]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: str r0, [r4]
+; CHECK-NEXT: stm r4!, {r0, r1, r2, r3}
; CHECK-NEXT: vpop {d8, d9, d10}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
@@ -3762,232 +3566,198 @@ define arm_aapcs_vfpcc <8 x i50> @test_unsigned_v8f16_v8i50(<8 x half> %f) {
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4
-; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14}
-; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14}
-; CHECK-NEXT: .pad #8
-; CHECK-NEXT: sub sp, #8
+; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13}
+; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13}
+; CHECK-NEXT: .pad #24
+; CHECK-NEXT: sub sp, #24
; CHECK-NEXT: vmov q4, q0
-; CHECK-NEXT: mov r10, r0
+; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vcvtb.f32.f16 s22, s17
+; CHECK-NEXT: vmov r0, s22
+; CHECK-NEXT: bl __aeabi_f2ulz
; CHECK-NEXT: vcvtb.f32.f16 s24, s18
+; CHECK-NEXT: mov r2, r0
; CHECK-NEXT: vmov r0, s24
+; CHECK-NEXT: vcvtt.f32.f16 s20, s18
+; CHECK-NEXT: vldr s18, .LCPI48_0
+; CHECK-NEXT: vcmp.f32 s22, #0
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: vcvtt.f32.f16 s26, s17
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: vcmp.f32 s22, s18
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: movwgt r1, #65535
+; CHECK-NEXT: movtgt r1, #3
+; CHECK-NEXT: str r1, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT: it gt
+; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: vmov r5, s26
+; CHECK-NEXT: str r2, [sp, #20] @ 4-byte Spill
+; CHECK-NEXT: vmov r6, s20
; CHECK-NEXT: bl __aeabi_f2ulz
-; CHECK-NEXT: vcvtt.f32.f16 s28, s19
; CHECK-NEXT: mov r7, r0
-; CHECK-NEXT: vmov r0, s28
-; CHECK-NEXT: vcvtb.f32.f16 s22, s16
-; CHECK-NEXT: vcvtb.f32.f16 s26, s19
; CHECK-NEXT: vcmp.f32 s24, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: mov r9, r1
-; CHECK-NEXT: vmov r5, s22
-; CHECK-NEXT: vldr s20, .LCPI48_0
-; CHECK-NEXT: vmov r11, s26
-; CHECK-NEXT: it lt
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt r1, #0
; CHECK-NEXT: movlt r7, #0
-; CHECK-NEXT: bl __aeabi_f2ulz
-; CHECK-NEXT: vcmp.f32 s28, #0
-; CHECK-NEXT: mov r4, r1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s20
-; CHECK-NEXT: mov r6, r0
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r4, #0
+; CHECK-NEXT: vcmp.f32 s24, s18
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: vcmp.f32 s24, s20
; CHECK-NEXT: itt gt
-; CHECK-NEXT: movwgt r4, #65535
-; CHECK-NEXT: movtgt r4, #3
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: movwgt r1, #65535
+; CHECK-NEXT: movtgt r1, #3
+; CHECK-NEXT: str r1, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r7, #-1
-; CHECK-NEXT: str.w r7, [r10, #25]
; CHECK-NEXT: bl __aeabi_f2ulz
-; CHECK-NEXT: vcmp.f32 s22, #0
-; CHECK-NEXT: str r1, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: vcmp.f32 s26, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s22, s20
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt r1, #0
; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: vcmp.f32 s26, s18
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, #0
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: movwgt r1, #65535
+; CHECK-NEXT: movtgt r1, #3
+; CHECK-NEXT: str r1, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT: str.w r7, [r4, #25]
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: mov r7, r4
-; CHECK-NEXT: str.w r0, [r10]
+; CHECK-NEXT: str r0, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: mov r0, r6
+; CHECK-NEXT: bl __aeabi_f2ulz
+; CHECK-NEXT: vcmp.f32 s20, #0
+; CHECK-NEXT: mov r6, r0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
+; CHECK-NEXT: vcmp.f32 s20, s18
+; CHECK-NEXT: vcvtb.f32.f16 s20, s19
+; CHECK-NEXT: mov r7, r1
+; CHECK-NEXT: vmov r0, s20
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt r7, #0
; CHECK-NEXT: movlt r6, #0
-; CHECK-NEXT: vcmp.f32 s28, s20
-; CHECK-NEXT: mov r0, r11
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: ittt gt
; CHECK-NEXT: movgt.w r6, #-1
-; CHECK-NEXT: bfc r7, #18, #14
-; CHECK-NEXT: lsll r6, r7, #22
+; CHECK-NEXT: movwgt r7, #65535
+; CHECK-NEXT: movtgt r7, #3
; CHECK-NEXT: bl __aeabi_f2ulz
-; CHECK-NEXT: vcmp.f32 s26, #0
-; CHECK-NEXT: mov r5, r0
+; CHECK-NEXT: vcmp.f32 s20, #0
+; CHECK-NEXT: mov r9, r0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r5, #0
+; CHECK-NEXT: vcmp.f32 s20, s18
+; CHECK-NEXT: vcvtt.f32.f16 s20, s19
+; CHECK-NEXT: mov r11, r1
+; CHECK-NEXT: vmov r0, s20
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt.w r11, #0
+; CHECK-NEXT: movlt.w r9, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r5, #-1
+; CHECK-NEXT: ittt gt
+; CHECK-NEXT: movgt.w r9, #-1
+; CHECK-NEXT: movwgt r11, #65535
+; CHECK-NEXT: movtgt r11, #3
+; CHECK-NEXT: bl __aeabi_f2ulz
+; CHECK-NEXT: vcmp.f32 s20, #0
+; CHECK-NEXT: mov r10, r0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt gt
-; CHECK-NEXT: movwgt r1, #65535
-; CHECK-NEXT: movtgt r1, #3
-; CHECK-NEXT: mov r2, r5
-; CHECK-NEXT: bfc r1, #18, #14
-; CHECK-NEXT: vcvtt.f32.f16 s26, s18
-; CHECK-NEXT: lsrl r2, r1, #28
-; CHECK-NEXT: orr.w r0, r1, r7
-; CHECK-NEXT: str.w r0, [r10, #45]
-; CHECK-NEXT: vmov r0, s26
-; CHECK-NEXT: orrs r6, r2
-; CHECK-NEXT: bl __aeabi_f2ulz
-; CHECK-NEXT: vcmp.f32 s26, #0
-; CHECK-NEXT: mov r7, r0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vcmp.f32 s26, s20
-; CHECK-NEXT: vcvtb.f32.f16 s18, s17
-; CHECK-NEXT: lsrs r0, r4, #10
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt gt
-; CHECK-NEXT: movwgt r1, #65535
-; CHECK-NEXT: movtgt r1, #3
-; CHECK-NEXT: str.w r6, [r10, #41]
-; CHECK-NEXT: strb.w r0, [r10, #49]
-; CHECK-NEXT: vmov r0, s18
-; CHECK-NEXT: vcmp.f32 s26, #0
-; CHECK-NEXT: bfc r1, #18, #14
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r7, #0
-; CHECK-NEXT: vcmp.f32 s26, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r7, #-1
-; CHECK-NEXT: mov r4, r7
-; CHECK-NEXT: lsrl r4, r1, #14
-; CHECK-NEXT: orr.w r6, r1, r5, lsl #4
-; CHECK-NEXT: bl __aeabi_f2ulz
-; CHECK-NEXT: vcvtt.f32.f16 s26, s17
-; CHECK-NEXT: mov r11, r0
-; CHECK-NEXT: vmov r0, s26
+; CHECK-NEXT: vcmp.f32 s20, s18
+; CHECK-NEXT: vcvtb.f32.f16 s20, s16
; CHECK-NEXT: mov r5, r1
-; CHECK-NEXT: vcmp.f32 s18, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
+; CHECK-NEXT: vmov r0, s20
+; CHECK-NEXT: itt lt
; CHECK-NEXT: movlt r5, #0
-; CHECK-NEXT: vcmp.f32 s18, s20
+; CHECK-NEXT: movlt.w r10, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt gt
+; CHECK-NEXT: ittt gt
+; CHECK-NEXT: movgt.w r10, #-1
; CHECK-NEXT: movwgt r5, #65535
; CHECK-NEXT: movtgt r5, #3
-; CHECK-NEXT: str.w r6, [r10, #37]
-; CHECK-NEXT: str.w r4, [r10, #33]
; CHECK-NEXT: bl __aeabi_f2ulz
-; CHECK-NEXT: vcmp.f32 s26, #0
-; CHECK-NEXT: mov r6, r1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r6, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, #0
-; CHECK-NEXT: itt gt
-; CHECK-NEXT: movwgt r6, #65535
-; CHECK-NEXT: movtgt r6, #3
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r9, #0
-; CHECK-NEXT: vcmp.f32 s24, s20
-; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: itt gt
-; CHECK-NEXT: movwgt r9, #65535
-; CHECK-NEXT: movtgt r9, #3
-; CHECK-NEXT: bfc r9, #18, #14
-; CHECK-NEXT: vcvtt.f32.f16 s16, s16
-; CHECK-NEXT: orr.w r0, r9, r7, lsl #18
-; CHECK-NEXT: str.w r0, [r10, #29]
-; CHECK-NEXT: vmov r0, s16
-; CHECK-NEXT: mov r1, r6
-; CHECK-NEXT: vcmp.f32 s26, #0
-; CHECK-NEXT: bfc r1, #18, #14
+; CHECK-NEXT: vcmp.f32 s20, #0
+; CHECK-NEXT: mov r8, r1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r4, #0
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt.w r8, #0
+; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: vcmp.f32 s20, s18
+; CHECK-NEXT: bfc r11, #18, #14
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, #0
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r4, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r11, #0
-; CHECK-NEXT: vcmp.f32 s18, s20
+; CHECK-NEXT: movgt.w r0, #-1
+; CHECK-NEXT: mov r2, r9
+; CHECK-NEXT: str r0, [r4]
+; CHECK-NEXT: lsrs r0, r5, #10
; CHECK-NEXT: bfc r5, #18, #14
+; CHECK-NEXT: lsll r10, r5, #22
+; CHECK-NEXT: lsrl r2, r11, #28
+; CHECK-NEXT: orr.w r1, r11, r5
+; CHECK-NEXT: str.w r1, [r4, #45]
+; CHECK-NEXT: orr.w r1, r2, r10
+; CHECK-NEXT: str.w r1, [r4, #41]
+; CHECK-NEXT: strb.w r0, [r4, #49]
+; CHECK-NEXT: bfc r7, #18, #14
+; CHECK-NEXT: mov r0, r6
+; CHECK-NEXT: vcvtt.f32.f16 s16, s16
+; CHECK-NEXT: lsrl r0, r7, #14
+; CHECK-NEXT: mov r5, r4
+; CHECK-NEXT: orr.w r1, r7, r9, lsl #4
+; CHECK-NEXT: str.w r1, [r4, #37]
+; CHECK-NEXT: str.w r0, [r4, #33]
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r11, #-1
-; CHECK-NEXT: mov r8, r11
-; CHECK-NEXT: vcmp.f32 s22, #0
-; CHECK-NEXT: ldr r7, [sp, #4] @ 4-byte Reload
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
+; CHECK-NEXT: bfc r0, #18, #14
+; CHECK-NEXT: orr.w r0, r0, r6, lsl #18
+; CHECK-NEXT: str.w r0, [r4, #29]
+; CHECK-NEXT: vmov r0, s16
+; CHECK-NEXT: ldr r7, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: ldr r3, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT: ldr.w r9, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: mov r1, r7
+; CHECK-NEXT: ldr r4, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: bfc r1, #18, #14
+; CHECK-NEXT: bfc r3, #18, #14
+; CHECK-NEXT: mov r6, r9
; CHECK-NEXT: lsll r4, r1, #22
-; CHECK-NEXT: lsrl r8, r5, #28
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r7, #0
-; CHECK-NEXT: vcmp.f32 s22, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: lsrl r6, r3, #28
; CHECK-NEXT: itt gt
-; CHECK-NEXT: movwgt r7, #65535
-; CHECK-NEXT: movtgt r7, #3
-; CHECK-NEXT: orrs r1, r5
-; CHECK-NEXT: str.w r1, [r10, #20]
+; CHECK-NEXT: movwgt r8, #65535
+; CHECK-NEXT: movtgt r8, #3
+; CHECK-NEXT: orrs r1, r3
+; CHECK-NEXT: str r1, [r5, #20]
; CHECK-NEXT: bl __aeabi_f2ulz
; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: orr.w r2, r8, r4
+; CHECK-NEXT: orr.w r2, r6, r4
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt r0, #0
; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: bfc r7, #18, #14
+; CHECK-NEXT: vcmp.f32 s16, s18
+; CHECK-NEXT: bfc r8, #18, #14
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: itt gt
; CHECK-NEXT: movwgt r1, #65535
; CHECK-NEXT: movtgt r1, #3
-; CHECK-NEXT: str.w r2, [r10, #16]
-; CHECK-NEXT: lsrs r2, r6, #10
-; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: strb.w r2, [r10, #24]
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: bfc r1, #18, #14
+; CHECK-NEXT: str r2, [r5, #16]
+; CHECK-NEXT: lsrs r2, r7, #10
+; CHECK-NEXT: strb r2, [r5, #24]
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1
; CHECK-NEXT: mov r2, r0
-; CHECK-NEXT: orr.w r0, r7, r0, lsl #18
+; CHECK-NEXT: bfc r1, #18, #14
+; CHECK-NEXT: orr.w r0, r8, r0, lsl #18
; CHECK-NEXT: lsrl r2, r1, #14
-; CHECK-NEXT: orr.w r1, r1, r11, lsl #4
-; CHECK-NEXT: strd r2, r1, [r10, #8]
-; CHECK-NEXT: str.w r0, [r10, #4]
-; CHECK-NEXT: add sp, #8
-; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14}
+; CHECK-NEXT: orr.w r1, r1, r9, lsl #4
+; CHECK-NEXT: strd r2, r1, [r5, #8]
+; CHECK-NEXT: str r0, [r5, #4]
+; CHECK-NEXT: add sp, #24
+; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
; CHECK-NEXT: .p2align 2
@@ -4005,8 +3775,8 @@ define arm_aapcs_vfpcc <8 x i64> @test_unsigned_v8f16_v8i64(<8 x half> %f) {
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4
-; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14}
+; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14}
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: vcvtt.f32.f16 s20, s19
; CHECK-NEXT: vmov r0, s20
@@ -4016,178 +3786,128 @@ define arm_aapcs_vfpcc <8 x i64> @test_unsigned_v8f16_v8i64(<8 x half> %f) {
; CHECK-NEXT: vmov r0, s22
; CHECK-NEXT: vldr s28, .LCPI49_0
; CHECK-NEXT: vcmp.f32 s20, #0
-; CHECK-NEXT: vcvtt.f32.f16 s24, s16
+; CHECK-NEXT: mov r8, r1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcvtb.f32.f16 s16, s16
-; CHECK-NEXT: it lt
+; CHECK-NEXT: vcvtt.f32.f16 s24, s18
+; CHECK-NEXT: vcvtt.f32.f16 s26, s16
+; CHECK-NEXT: itt lt
; CHECK-NEXT: movlt.w r9, #0
+; CHECK-NEXT: movlt.w r8, #0
; CHECK-NEXT: vcmp.f32 s20, s28
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: mov r8, r1
-; CHECK-NEXT: vmov r5, s24
-; CHECK-NEXT: it gt
+; CHECK-NEXT: vmov r4, s24
+; CHECK-NEXT: vmov r6, s26
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: movgt.w r8, #-1
; CHECK-NEXT: movgt.w r9, #-1
-; CHECK-NEXT: vmov r4, s16
; CHECK-NEXT: bl __aeabi_f2ulz
+; CHECK-NEXT: mov r10, r0
; CHECK-NEXT: vcmp.f32 s22, #0
-; CHECK-NEXT: mov r11, r0
+; CHECK-NEXT: mov r11, r1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s22, s28
-; CHECK-NEXT: it lt
+; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: itt lt
; CHECK-NEXT: movlt.w r11, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s20, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r11, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s20, s28
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r8, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: mov r10, r1
-; CHECK-NEXT: vcmp.f32 s22, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r8, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: it lt
; CHECK-NEXT: movlt.w r10, #0
; CHECK-NEXT: vcmp.f32 s22, s28
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itt gt
; CHECK-NEXT: movgt.w r10, #-1
+; CHECK-NEXT: movgt.w r11, #-1
; CHECK-NEXT: bl __aeabi_f2ulz
-; CHECK-NEXT: mov r6, r0
+; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: vcmp.f32 s24, #0
+; CHECK-NEXT: mov r4, r1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: mov r0, r4
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r6, #0
+; CHECK-NEXT: mov r0, r6
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt r5, #0
+; CHECK-NEXT: movlt r4, #0
; CHECK-NEXT: vcmp.f32 s24, s28
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: mov r5, r1
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r6, #-1
-; CHECK-NEXT: bl __aeabi_f2ulz
-; CHECK-NEXT: vcvtt.f32.f16 s30, s17
-; CHECK-NEXT: mov r7, r1
-; CHECK-NEXT: vmov r1, s30
-; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s16, s28
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vmov q5[2], q5[0], r0, r6
-; CHECK-NEXT: mov r0, r1
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: movgt.w r4, #-1
+; CHECK-NEXT: movgt.w r5, #-1
; CHECK-NEXT: bl __aeabi_f2ulz
-; CHECK-NEXT: vcmp.f32 s30, #0
-; CHECK-NEXT: mov r6, r0
+; CHECK-NEXT: vcvtb.f32.f16 s16, s16
+; CHECK-NEXT: mov r7, r0
+; CHECK-NEXT: vmov r0, s16
+; CHECK-NEXT: mov r6, r1
+; CHECK-NEXT: vcmp.f32 s26, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s28
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt r7, #0
; CHECK-NEXT: movlt r6, #0
+; CHECK-NEXT: vcmp.f32 s26, s28
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, #0
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itt gt
; CHECK-NEXT: movgt.w r6, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, s28
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r5, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r5, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s28
-; CHECK-NEXT: vcvtb.f32.f16 s16, s17
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r7, #0
-; CHECK-NEXT: vmov r0, s16
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r7, #-1
-; CHECK-NEXT: mov r4, r1
-; CHECK-NEXT: vmov q5[3], q5[1], r7, r5
; CHECK-NEXT: bl __aeabi_f2ulz
-; CHECK-NEXT: vcvtt.f32.f16 s17, s18
-; CHECK-NEXT: mov r7, r1
-; CHECK-NEXT: vmov r1, s17
; CHECK-NEXT: vcmp.f32 s16, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
; CHECK-NEXT: vcmp.f32 s16, s28
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vmov q6[2], q6[0], r0, r6
-; CHECK-NEXT: mov r0, r1
-; CHECK-NEXT: bl __aeabi_f2ulz
-; CHECK-NEXT: vcmp.f32 s17, #0
-; CHECK-NEXT: mov r6, r0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s28
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r6, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, #0
+; CHECK-NEXT: vcvtt.f32.f16 s16, s17
+; CHECK-NEXT: vmov q5[2], q5[0], r0, r7
+; CHECK-NEXT: vmov r0, s16
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r6, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s28
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r4, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: vmov q5[3], q5[1], r1, r6
+; CHECK-NEXT: bl __aeabi_f2ulz
; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r4, #-1
+; CHECK-NEXT: mov r7, r0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s16, s28
-; CHECK-NEXT: vcvtb.f32.f16 s16, s18
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r7, #0
+; CHECK-NEXT: vcvtb.f32.f16 s16, s17
+; CHECK-NEXT: mov r6, r1
; CHECK-NEXT: vmov r0, s16
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt r7, #0
+; CHECK-NEXT: movlt r6, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: movgt.w r6, #-1
; CHECK-NEXT: movgt.w r7, #-1
-; CHECK-NEXT: mov r5, r1
-; CHECK-NEXT: vmov q6[3], q6[1], r7, r4
; CHECK-NEXT: bl __aeabi_f2ulz
; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: vmov q3[2], q3[0], r11, r9
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s16, s28
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
+; CHECK-NEXT: movlt r1, #0
; CHECK-NEXT: movlt r0, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, #0
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s17, s28
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r5, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, #0
+; CHECK-NEXT: vcvtb.f32.f16 s16, s18
+; CHECK-NEXT: vmov q6[2], q6[0], r0, r7
+; CHECK-NEXT: vmov r0, s16
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r5, #-1
+; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: vmov q6[3], q6[1], r1, r6
+; CHECK-NEXT: bl __aeabi_f2ulz
+; CHECK-NEXT: vcmp.f32 s16, #0
+; CHECK-NEXT: vmov q3[2], q3[0], r10, r9
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itt lt
; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r0, #0
; CHECK-NEXT: vcmp.f32 s16, s28
-; CHECK-NEXT: vmov q2[2], q2[0], r0, r6
+; CHECK-NEXT: vmov q3[3], q3[1], r11, r8
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itt gt
+; CHECK-NEXT: movgt.w r0, #-1
; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmov q2[3], q2[1], r1, r5
-; CHECK-NEXT: vmov q3[3], q3[1], r10, r8
+; CHECK-NEXT: vmov q2[2], q2[0], r0, r5
; CHECK-NEXT: vmov q0, q5
+; CHECK-NEXT: vmov q2[3], q2[1], r1, r4
; CHECK-NEXT: vmov q1, q6
-; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
; CHECK-NEXT: .p2align 2
@@ -4205,385 +3925,272 @@ define arm_aapcs_vfpcc <8 x i100> @test_unsigned_v8f16_v8i100(<8 x half> %f) {
; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4
-; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: .pad #32
-; CHECK-NEXT: sub sp, #32
+; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12}
+; CHECK-NEXT: vpush {d8, d9, d10, d11, d12}
+; CHECK-NEXT: .pad #56
+; CHECK-NEXT: sub sp, #56
; CHECK-NEXT: vmov q4, q0
-; CHECK-NEXT: mov r8, r0
-; CHECK-NEXT: vcvtb.f32.f16 s30, s19
-; CHECK-NEXT: vcvtb.f32.f16 s28, s18
-; CHECK-NEXT: vmov r0, s30
-; CHECK-NEXT: vcvtt.f32.f16 s22, s19
-; CHECK-NEXT: vcvtb.f32.f16 s24, s16
-; CHECK-NEXT: vcvtb.f32.f16 s26, s17
-; CHECK-NEXT: vldr s20, .LCPI50_1
-; CHECK-NEXT: vmov r4, s22
-; CHECK-NEXT: vmov r7, s28
-; CHECK-NEXT: vcvtt.f32.f16 s18, s18
-; CHECK-NEXT: vmov r9, s24
-; CHECK-NEXT: vmov r6, s26
+; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: vcvtt.f32.f16 s22, s16
+; CHECK-NEXT: vmov r0, s22
; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: vcmp.f32 s30, #0
-; CHECK-NEXT: mov r5, r3
+; CHECK-NEXT: vcvtt.f32.f16 s24, s17
+; CHECK-NEXT: mov r7, r0
+; CHECK-NEXT: vmov r0, s24
+; CHECK-NEXT: vldr s20, .LCPI50_0
+; CHECK-NEXT: vcmp.f32 s22, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s20
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt r7, #0
+; CHECK-NEXT: movlt r1, #0
; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: movlt r3, #0
+; CHECK-NEXT: vcmp.f32 s22, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, #0
+; CHECK-NEXT: it gt
+; CHECK-NEXT: movgt r3, #15
+; CHECK-NEXT: str r3, [sp, #52] @ 4-byte Spill
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s20
-; CHECK-NEXT: str.w r2, [r8, #83]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, #0
+; CHECK-NEXT: str r2, [sp, #48] @ 4-byte Spill
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str.w r1, [r8, #79]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s30, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: str r1, [sp, #44] @ 4-byte Spill
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: str.w r0, [r8, #75]
-; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: movgt.w r7, #-1
+; CHECK-NEXT: str r7, [sp, #40] @ 4-byte Spill
; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: vcmp.f32 s28, #0
-; CHECK-NEXT: mov r7, r3
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: vcmp.f32 s24, #0
+; CHECK-NEXT: vcvtt.f32.f16 s22, s18
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s20
-; CHECK-NEXT: str.w r2, [r8, #58]
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itttt lt
; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str.w r1, [r8, #54]
-; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s28, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: str.w r0, [r8, #50]
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: vcmp.f32 s26, #0
-; CHECK-NEXT: str r3, [sp, #24] @ 4-byte Spill
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s20
-; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: movlt r3, #0
+; CHECK-NEXT: vcmp.f32 s24, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, #0
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s20
-; CHECK-NEXT: str.w r2, [r8, #33]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, #0
+; CHECK-NEXT: movgt r3, #15
+; CHECK-NEXT: str r3, [sp, #36] @ 4-byte Spill
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str.w r1, [r8, #29]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s26, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: str r2, [sp, #32] @ 4-byte Spill
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: str.w r0, [r8, #25]
-; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: str r0, [sp, #24] @ 4-byte Spill
+; CHECK-NEXT: vmov r0, s22
+; CHECK-NEXT: it gt
+; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: str r1, [sp, #28] @ 4-byte Spill
; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: vcmp.f32 s24, #0
-; CHECK-NEXT: str r3, [sp, #12] @ 4-byte Spill
+; CHECK-NEXT: vcmp.f32 s22, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, s20
-; CHECK-NEXT: it lt
+; CHECK-NEXT: vcmp.f32 s22, s20
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: movlt r1, #0
; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: movlt r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, #0
+; CHECK-NEXT: it gt
+; CHECK-NEXT: movgt r3, #15
+; CHECK-NEXT: str r3, [sp, #20] @ 4-byte Spill
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, s20
-; CHECK-NEXT: str.w r2, [r8, #8]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, #0
+; CHECK-NEXT: str r2, [sp, #16] @ 4-byte Spill
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str.w r1, [r8, #4]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s24, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: str r1, [sp, #12] @ 4-byte Spill
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: str.w r0, [r8]
-; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: vcvtb.f32.f16 s22, s17
+; CHECK-NEXT: str r0, [sp, #4] @ 4-byte Spill
+; CHECK-NEXT: vmov r0, s22
; CHECK-NEXT: bl __fixunssfti
+; CHECK-NEXT: vcvtb.f32.f16 s18, s18
+; CHECK-NEXT: mov r9, r0
+; CHECK-NEXT: vmov r0, s18
+; CHECK-NEXT: mov r8, r1
; CHECK-NEXT: vcmp.f32 s22, #0
-; CHECK-NEXT: mov r6, r0
+; CHECK-NEXT: mov r6, r2
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s22, s20
-; CHECK-NEXT: str r3, [sp, #8] @ 4-byte Spill
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itttt lt
; CHECK-NEXT: movlt r6, #0
+; CHECK-NEXT: movlt.w r8, #0
+; CHECK-NEXT: movlt.w r9, #0
+; CHECK-NEXT: movlt r3, #0
+; CHECK-NEXT: vcmp.f32 s22, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, #0
; CHECK-NEXT: it gt
+; CHECK-NEXT: movgt r3, #15
+; CHECK-NEXT: str r3, [sp, #8] @ 4-byte Spill
+; CHECK-NEXT: ittt gt
+; CHECK-NEXT: movgt.w r9, #-1
+; CHECK-NEXT: movgt.w r8, #-1
; CHECK-NEXT: movgt.w r6, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r5, #0
-; CHECK-NEXT: vcmp.f32 s30, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r5, #15
-; CHECK-NEXT: and r0, r5, #15
-; CHECK-NEXT: mov r9, r1
-; CHECK-NEXT: orr.w r1, r0, r6, lsl #4
-; CHECK-NEXT: vmov r0, s18
-; CHECK-NEXT: mov r4, r2
-; CHECK-NEXT: str.w r1, [r8, #87]
; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: vcmp.f32 s18, #0
-; CHECK-NEXT: mov r10, r0
+; CHECK-NEXT: mov r5, r0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: str r2, [sp, #4] @ 4-byte Spill
-; CHECK-NEXT: mov r5, r1
-; CHECK-NEXT: str r3, [sp, #20] @ 4-byte Spill
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r10, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r10, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s20
-; CHECK-NEXT: it lt
+; CHECK-NEXT: vcvtb.f32.f16 s18, s19
+; CHECK-NEXT: mov r11, r1
+; CHECK-NEXT: vmov r0, s18
+; CHECK-NEXT: mov r7, r2
+; CHECK-NEXT: itttt lt
; CHECK-NEXT: movlt r7, #0
+; CHECK-NEXT: movlt.w r11, #0
+; CHECK-NEXT: movlt r5, #0
+; CHECK-NEXT: movlt r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r7, #15
-; CHECK-NEXT: and r0, r7, #15
-; CHECK-NEXT: vcvtt.f32.f16 s28, s17
-; CHECK-NEXT: orr.w r0, r0, r10, lsl #4
-; CHECK-NEXT: str.w r0, [r8, #62]
-; CHECK-NEXT: vmov r0, s28
+; CHECK-NEXT: movgt r3, #15
+; CHECK-NEXT: str r3, [sp] @ 4-byte Spill
+; CHECK-NEXT: ittt gt
+; CHECK-NEXT: movgt.w r5, #-1
+; CHECK-NEXT: movgt.w r11, #-1
+; CHECK-NEXT: movgt.w r7, #-1
; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: vcmp.f32 s28, #0
-; CHECK-NEXT: str r2, [sp, #16] @ 4-byte Spill
+; CHECK-NEXT: vcmp.f32 s18, #0
+; CHECK-NEXT: mov r10, r3
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r3, [sp, #28] @ 4-byte Spill
-; CHECK-NEXT: it lt
+; CHECK-NEXT: vcmp.f32 s18, s20
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt.w r10, #0
; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s28, s20
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: mov r11, r1
-; CHECK-NEXT: vcmp.f32 s26, #0
-; CHECK-NEXT: mov r1, r0
-; CHECK-NEXT: str r0, [sp] @ 4-byte Spill
-; CHECK-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s26, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: str.w r2, [r4, #83]
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r0, #15
-; CHECK-NEXT: and r0, r0, #15
-; CHECK-NEXT: vcvtt.f32.f16 s16, s16
-; CHECK-NEXT: orr.w r0, r0, r1, lsl #4
-; CHECK-NEXT: str.w r0, [r8, #37]
-; CHECK-NEXT: vmov r0, s16
-; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s16, s20
+; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: str.w r1, [r4, #79]
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: vcmp.f32 s24, #0
-; CHECK-NEXT: ldr r7, [sp, #12] @ 4-byte Reload
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r7, #0
-; CHECK-NEXT: vcmp.f32 s24, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r7, #15
-; CHECK-NEXT: and r7, r7, #15
-; CHECK-NEXT: vcmp.f32 s22, #0
-; CHECK-NEXT: orr.w r7, r7, r0, lsl #4
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str.w r7, [r8, #12]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r9, #0
-; CHECK-NEXT: vcmp.f32 s22, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r9, #-1
-; CHECK-NEXT: vcmp.f32 s22, #0
-; CHECK-NEXT: lsrl r6, r9, #28
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r4, #0
-; CHECK-NEXT: vcmp.f32 s22, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r4, #-1
-; CHECK-NEXT: orr.w r7, r9, r4, lsl #4
-; CHECK-NEXT: str.w r7, [r8, #95]
-; CHECK-NEXT: str.w r6, [r8, #91]
-; CHECK-NEXT: vcmp.f32 s22, #0
-; CHECK-NEXT: ldr r7, [sp, #8] @ 4-byte Reload
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r7, #0
-; CHECK-NEXT: vcmp.f32 s22, s20
+; CHECK-NEXT: vcvtt.f32.f16 s18, s19
+; CHECK-NEXT: str.w r0, [r4, #75]
+; CHECK-NEXT: vmov r0, s18
+; CHECK-NEXT: str.w r7, [r4, #58]
+; CHECK-NEXT: str.w r11, [r4, #54]
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: str.w r5, [r4, #50]
+; CHECK-NEXT: str.w r6, [r4, #33]
+; CHECK-NEXT: str.w r8, [r4, #29]
+; CHECK-NEXT: str.w r9, [r4, #25]
; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r7, #15
-; CHECK-NEXT: and r7, r7, #15
+; CHECK-NEXT: movgt.w r10, #15
+; CHECK-NEXT: bl __fixunssfti
+; CHECK-NEXT: vcvtb.f32.f16 s16, s16
+; CHECK-NEXT: mov r5, r0
+; CHECK-NEXT: vmov r0, s16
+; CHECK-NEXT: mov r7, r1
; CHECK-NEXT: vcmp.f32 s18, #0
-; CHECK-NEXT: lsrl r4, r7, #28
+; CHECK-NEXT: mov r6, r2
+; CHECK-NEXT: mov r8, r3
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: strb.w r4, [r8, #99]
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt r7, #0
; CHECK-NEXT: movlt r5, #0
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r5, #-1
-; CHECK-NEXT: vcmp.f32 s18, #0
-; CHECK-NEXT: ldr r6, [sp, #4] @ 4-byte Reload
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: lsrl r10, r5, #28
-; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r6, #0
+; CHECK-NEXT: movlt.w r8, #0
; CHECK-NEXT: vcmp.f32 s18, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r6, #-1
-; CHECK-NEXT: orr.w r7, r5, r6, lsl #4
-; CHECK-NEXT: str.w r7, [r8, #70]
-; CHECK-NEXT: str.w r10, [r8, #66]
-; CHECK-NEXT: vcmp.f32 s18, #0
-; CHECK-NEXT: ldr r7, [sp, #20] @ 4-byte Reload
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r7, #0
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r7, #15
-; CHECK-NEXT: and r5, r7, #15
-; CHECK-NEXT: vcmp.f32 s28, #0
-; CHECK-NEXT: lsrl r6, r5, #28
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: strb.w r6, [r8, #74]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt.w r11, #0
-; CHECK-NEXT: vcmp.f32 s28, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r11, #-1
-; CHECK-NEXT: ldr r4, [sp] @ 4-byte Reload
-; CHECK-NEXT: vcmp.f32 s28, #0
-; CHECK-NEXT: ldr r6, [sp, #16] @ 4-byte Reload
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: lsrl r4, r11, #28
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r6, #0
-; CHECK-NEXT: vcmp.f32 s28, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: b.w .LBB50_2
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI50_1:
-; CHECK-NEXT: .long 0x717fffff @ float 1.26765052E+30
-; CHECK-NEXT: .p2align 1
-; CHECK-NEXT: .LBB50_2:
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itttt gt
+; CHECK-NEXT: movgt.w r8, #15
; CHECK-NEXT: movgt.w r6, #-1
-; CHECK-NEXT: orr.w r7, r11, r6, lsl #4
-; CHECK-NEXT: str.w r7, [r8, #45]
-; CHECK-NEXT: str.w r4, [r8, #41]
-; CHECK-NEXT: vcmp.f32 s28, #0
-; CHECK-NEXT: ldr r7, [sp, #28] @ 4-byte Reload
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r7, #0
-; CHECK-NEXT: vcmp.f32 s28, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt r7, #15
-; CHECK-NEXT: and r5, r7, #15
+; CHECK-NEXT: movgt.w r5, #-1
+; CHECK-NEXT: movgt.w r7, #-1
+; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: lsrl r6, r5, #28
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: strb.w r6, [r8, #49]
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt r3, #0
+; CHECK-NEXT: movlt r0, #0
; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: lsrl r0, r1, #28
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: vcmp.f32 s16, s20
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: orr.w r1, r1, r2, lsl #4
-; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: strd r0, r1, [r8, #16]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r3, #0
+; CHECK-NEXT: str r2, [r4, #8]
+; CHECK-NEXT: it gt
+; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: str r1, [r4, #4]
+; CHECK-NEXT: it gt
+; CHECK-NEXT: movgt.w r0, #-1
+; CHECK-NEXT: str r0, [r4]
+; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: lsrl r0, r7, #28
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: orr.w r1, r7, r6, lsl #4
+; CHECK-NEXT: str.w r1, [r4, #95]
+; CHECK-NEXT: and r1, r8, #15
+; CHECK-NEXT: str.w r0, [r4, #91]
+; CHECK-NEXT: and r0, r10, #15
+; CHECK-NEXT: lsrl r6, r1, #28
+; CHECK-NEXT: strb.w r6, [r4, #99]
+; CHECK-NEXT: orr.w r0, r0, r5, lsl #4
+; CHECK-NEXT: str.w r0, [r4, #87]
+; CHECK-NEXT: ldr r7, [sp, #4] @ 4-byte Reload
+; CHECK-NEXT: ldr r1, [sp, #12] @ 4-byte Reload
+; CHECK-NEXT: ldr r2, [sp, #16] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: lsrl r0, r1, #28
+; CHECK-NEXT: orr.w r1, r1, r2, lsl #4
+; CHECK-NEXT: str.w r1, [r4, #70]
+; CHECK-NEXT: str.w r0, [r4, #66]
+; CHECK-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
+; CHECK-NEXT: and r1, r0, #15
+; CHECK-NEXT: lsrl r2, r1, #28
+; CHECK-NEXT: strb.w r2, [r4, #74]
+; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
+; CHECK-NEXT: and r0, r0, #15
+; CHECK-NEXT: orr.w r0, r0, r7, lsl #4
+; CHECK-NEXT: str.w r0, [r4, #62]
+; CHECK-NEXT: ldr r7, [sp, #24] @ 4-byte Reload
+; CHECK-NEXT: ldr r1, [sp, #28] @ 4-byte Reload
+; CHECK-NEXT: ldr r2, [sp, #32] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: lsrl r0, r1, #28
+; CHECK-NEXT: orr.w r1, r1, r2, lsl #4
+; CHECK-NEXT: str.w r1, [r4, #45]
+; CHECK-NEXT: str.w r0, [r4, #41]
+; CHECK-NEXT: ldr r0, [sp, #36] @ 4-byte Reload
+; CHECK-NEXT: and r1, r0, #15
+; CHECK-NEXT: lsrl r2, r1, #28
+; CHECK-NEXT: strb.w r2, [r4, #49]
+; CHECK-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
+; CHECK-NEXT: and r0, r0, #15
+; CHECK-NEXT: orr.w r0, r0, r7, lsl #4
+; CHECK-NEXT: str.w r0, [r4, #37]
+; CHECK-NEXT: ldr r7, [sp, #40] @ 4-byte Reload
+; CHECK-NEXT: ldr r1, [sp, #44] @ 4-byte Reload
+; CHECK-NEXT: ldr r2, [sp, #48] @ 4-byte Reload
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: lsrl r0, r1, #28
+; CHECK-NEXT: orr.w r1, r1, r2, lsl #4
+; CHECK-NEXT: strd r0, r1, [r4, #16]
+; CHECK-NEXT: ldr r0, [sp, #52] @ 4-byte Reload
+; CHECK-NEXT: and r1, r0, #15
+; CHECK-NEXT: lsrl r2, r1, #28
+; CHECK-NEXT: strb r2, [r4, #24]
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt r3, #15
-; CHECK-NEXT: and r1, r3, #15
-; CHECK-NEXT: lsrl r2, r1, #28
-; CHECK-NEXT: strb.w r2, [r8, #24]
-; CHECK-NEXT: add sp, #32
-; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-NEXT: and r0, r3, #15
+; CHECK-NEXT: orr.w r0, r0, r7, lsl #4
+; CHECK-NEXT: str r0, [r4, #12]
+; CHECK-NEXT: add sp, #56
+; CHECK-NEXT: vpop {d8, d9, d10, d11, d12}
; CHECK-NEXT: add sp, #4
; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}
-; CHECK-NEXT: @ %bb.3:
+; CHECK-NEXT: .p2align 2
+; CHECK-NEXT: @ %bb.1:
+; CHECK-NEXT: .LCPI50_0:
+; CHECK-NEXT: .long 0x717fffff @ float 1.26765052E+30
%x = call <8 x i100> @llvm.fptoui.sat.v8f16.v8i100(<8 x half> %f)
ret <8 x i100> %x
}
@@ -4591,337 +4198,195 @@ define arm_aapcs_vfpcc <8 x i100> @test_unsigned_v8f16_v8i100(<8 x half> %f) {
define arm_aapcs_vfpcc <8 x i128> @test_unsigned_v8f16_v8i128(<8 x half> %f) {
; CHECK-LABEL: test_unsigned_v8f16_v8i128:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r6, r7, r8, r9, lr}
-; CHECK-NEXT: push.w {r4, r5, r6, r7, r8, r9, lr}
+; CHECK-NEXT: .save {r4, r5, r6, r7, lr}
+; CHECK-NEXT: push {r4, r5, r6, r7, lr}
; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4
-; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14, d15}
-; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-NEXT: .vsave {d8, d9, d10, d11, d12, d13, d14}
+; CHECK-NEXT: vpush {d8, d9, d10, d11, d12, d13, d14}
; CHECK-NEXT: vmov q4, q0
; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: vcvtt.f32.f16 s26, s19
-; CHECK-NEXT: vcvtb.f32.f16 s22, s16
-; CHECK-NEXT: vmov r0, s26
-; CHECK-NEXT: vcvtt.f32.f16 s16, s16
-; CHECK-NEXT: vcvtb.f32.f16 s24, s17
-; CHECK-NEXT: vcvtb.f32.f16 s30, s19
-; CHECK-NEXT: vldr s20, .LCPI51_0
-; CHECK-NEXT: vmov r8, s22
-; CHECK-NEXT: vmov r9, s16
-; CHECK-NEXT: vcvtt.f32.f16 s28, s18
-; CHECK-NEXT: vmov r7, s24
-; CHECK-NEXT: vmov r6, s30
+; CHECK-NEXT: vcvtt.f32.f16 s22, s19
+; CHECK-NEXT: vmov r0, s22
; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: vcmp.f32 s26, #0
-; CHECK-NEXT: vcvtb.f32.f16 s18, s18
+; CHECK-NEXT: vcvtb.f32.f16 s28, s19
+; CHECK-NEXT: mov r6, r0
+; CHECK-NEXT: vmov r0, s28
+; CHECK-NEXT: vldr s20, .LCPI51_0
+; CHECK-NEXT: vcmp.f32 s22, #0
+; CHECK-NEXT: vcvtt.f32.f16 s24, s18
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s20
-; CHECK-NEXT: it lt
+; CHECK-NEXT: vcmp.f32 s22, s20
+; CHECK-NEXT: vcvtb.f32.f16 s26, s18
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt r6, #0
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: movlt r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, #0
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r3, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s20
-; CHECK-NEXT: str r3, [r4, #124]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, #0
-; CHECK-NEXT: it gt
+; CHECK-NEXT: ittt gt
; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s20
-; CHECK-NEXT: str r2, [r4, #120]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, #0
-; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #116]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s26, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: str r0, [r4, #112]
-; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: vmov r5, s28
+; CHECK-NEXT: movgt.w r6, #-1
+; CHECK-NEXT: strd r6, r1, [r4, #112]
+; CHECK-NEXT: vmov r7, s24
+; CHECK-NEXT: vmov r5, s26
+; CHECK-NEXT: vcvtt.f32.f16 s18, s17
+; CHECK-NEXT: strd r2, r3, [r4, #120]
; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: vcmp.f32 s30, #0
-; CHECK-NEXT: vcvtt.f32.f16 s26, s17
+; CHECK-NEXT: vcmp.f32 s28, #0
+; CHECK-NEXT: add.w r12, r4, #96
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s20
-; CHECK-NEXT: it lt
+; CHECK-NEXT: vcmp.f32 s28, s20
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: movlt r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, #0
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r3, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s20
-; CHECK-NEXT: str r3, [r4, #108]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, #0
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r2, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, s20
-; CHECK-NEXT: str r2, [r4, #104]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s30, #0
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itt gt
; CHECK-NEXT: movgt.w r1, #-1
+; CHECK-NEXT: movgt.w r0, #-1
+; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: vmov r6, s18
+; CHECK-NEXT: vcvtb.f32.f16 s22, s17
+; CHECK-NEXT: bl __fixunssfti
+; CHECK-NEXT: vcmp.f32 s24, #0
+; CHECK-NEXT: add.w r12, r4, #80
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #100]
-; CHECK-NEXT: it lt
+; CHECK-NEXT: vcmp.f32 s24, s20
+; CHECK-NEXT: itttt lt
; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s30, s20
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r2, #0
+; CHECK-NEXT: movlt r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt
+; CHECK-NEXT: movgt.w r3, #-1
+; CHECK-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-NEXT: ittt gt
+; CHECK-NEXT: movgt.w r2, #-1
+; CHECK-NEXT: movgt.w r1, #-1
; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: str r0, [r4, #96]
+; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
; CHECK-NEXT: mov r0, r5
-; CHECK-NEXT: vmov r6, s18
+; CHECK-NEXT: vcvtt.f32.f16 s24, s16
+; CHECK-NEXT: vmov r7, s22
; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: vcmp.f32 s28, #0
+; CHECK-NEXT: vcmp.f32 s26, #0
+; CHECK-NEXT: add.w r12, r4, #64
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s20
-; CHECK-NEXT: it lt
+; CHECK-NEXT: vcmp.f32 s26, s20
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: movlt r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, #0
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r3, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s20
-; CHECK-NEXT: str r3, [r4, #92]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, #0
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r2, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, s20
-; CHECK-NEXT: str r2, [r4, #88]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s28, #0
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itt gt
; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #84]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s28, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: str r0, [r4, #80]
+; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
; CHECK-NEXT: mov r0, r6
-; CHECK-NEXT: vmov r5, s26
+; CHECK-NEXT: vmov r5, s24
+; CHECK-NEXT: vcvtb.f32.f16 s16, s16
; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: vcmp.f32 s18, #0
+; CHECK-NEXT: add.w r12, r4, #48
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: movlt r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, #0
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r3, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: str r3, [r4, #76]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, #0
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r2, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: str r2, [r4, #72]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s18, #0
-; CHECK-NEXT: it gt
+; CHECK-NEXT: itt gt
; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #68]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s18, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: str r0, [r4, #64]
-; CHECK-NEXT: mov r0, r5
+; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
+; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: vmov r6, s16
; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: vcmp.f32 s26, #0
+; CHECK-NEXT: vcmp.f32 s22, #0
+; CHECK-NEXT: add.w r12, r4, #32
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s20
-; CHECK-NEXT: it lt
+; CHECK-NEXT: vcmp.f32 s22, s20
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: movlt r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, #0
-; CHECK-NEXT: it gt
+; CHECK-NEXT: ittt gt
; CHECK-NEXT: movgt.w r3, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s20
-; CHECK-NEXT: str r3, [r4, #60]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, #0
-; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, s20
-; CHECK-NEXT: str r2, [r4, #56]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s26, #0
-; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #52]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s26, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: str r0, [r4, #48]
-; CHECK-NEXT: mov r0, r7
+; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
+; CHECK-NEXT: mov r0, r5
; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: vcmp.f32 s24, #0
+; CHECK-NEXT: add.w r12, r4, #16
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s24, s20
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itttt lt
+; CHECK-NEXT: movlt r0, #0
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: movlt r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, #0
-; CHECK-NEXT: it gt
+; CHECK-NEXT: ittt gt
; CHECK-NEXT: movgt.w r3, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, s20
-; CHECK-NEXT: str r3, [r4, #44]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, #0
-; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, s20
-; CHECK-NEXT: str r2, [r4, #40]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s24, #0
-; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #36]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s24, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: str r0, [r4, #32]
-; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: stm.w r12, {r0, r1, r2, r3}
+; CHECK-NEXT: mov r0, r6
; CHECK-NEXT: bl __fixunssfti
; CHECK-NEXT: vcmp.f32 s16, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r3, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r3, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: str r3, [r4, #28]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: str r2, [r4, #24]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s16, #0
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r1, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #20]
-; CHECK-NEXT: it lt
+; CHECK-NEXT: itttt lt
; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s16, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: it gt
-; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: str r0, [r4, #16]
-; CHECK-NEXT: mov r0, r8
-; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: vcmp.f32 s22, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s22, s20
-; CHECK-NEXT: it lt
+; CHECK-NEXT: movlt r1, #0
+; CHECK-NEXT: movlt r2, #0
; CHECK-NEXT: movlt r3, #0
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s22, #0
-; CHECK-NEXT: it gt
+; CHECK-NEXT: ittt gt
; CHECK-NEXT: movgt.w r3, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s22, s20
-; CHECK-NEXT: str r3, [r4, #12]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r2, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s22, #0
-; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r2, #-1
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s22, s20
-; CHECK-NEXT: str r2, [r4, #8]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r1, #0
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: vcmp.f32 s22, #0
-; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r1, #-1
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-NEXT: str r1, [r4, #4]
-; CHECK-NEXT: it lt
-; CHECK-NEXT: movlt r0, #0
-; CHECK-NEXT: vcmp.f32 s22, s20
-; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: it gt
; CHECK-NEXT: movgt.w r0, #-1
-; CHECK-NEXT: str r0, [r4]
-; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
+; CHECK-NEXT: stm r4!, {r0, r1, r2, r3}
+; CHECK-NEXT: vpop {d8, d9, d10, d11, d12, d13, d14}
; CHECK-NEXT: add sp, #4
-; CHECK-NEXT: pop.w {r4, r5, r6, r7, r8, r9, pc}
+; CHECK-NEXT: pop {r4, r5, r6, r7, pc}
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI51_0:
diff --git a/llvm/test/CodeGen/Thumb2/mve-pred-ext.ll b/llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
index 117469f3bd788b..101b49fea488a8 100644
--- a/llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-pred-ext.ll
@@ -300,27 +300,27 @@ define arm_aapcs_vfpcc <8 x i16> @zext_v8i1_v8f32(<8 x half> %src1, <8 x half> %
; CHECK-MVE-NEXT: vcmp.f16 s10, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vmovx.f16 s10, s2
-; CHECK-MVE-NEXT: vcmp.f16 s10, s8
-; CHECK-MVE-NEXT: vmovx.f16 s8, s5
-; CHECK-MVE-NEXT: vmovx.f16 s10, s1
; CHECK-MVE-NEXT: csetm r12, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s3, s7
+; CHECK-MVE-NEXT: vcmp.f16 s10, s8
; CHECK-MVE-NEXT: csetm lr, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s10, s8
+; CHECK-MVE-NEXT: vcmp.f16 s2, s6
+; CHECK-MVE-NEXT: vmovx.f16 s2, s5
+; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: csetm r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s2, s6
+; CHECK-MVE-NEXT: vcmp.f16 s6, s2
; CHECK-MVE-NEXT: vmovx.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s6, s0
; CHECK-MVE-NEXT: csetm r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s6, s2
+; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: csetm r0, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f16 s1, s5
+; CHECK-MVE-NEXT: vcmp.f16 s6, s2
; CHECK-MVE-NEXT: csetm r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
@@ -329,12 +329,12 @@ define arm_aapcs_vfpcc <8 x i16> @zext_v8i1_v8f32(<8 x half> %src1, <8 x half> %
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: csetm r5, ne
; CHECK-MVE-NEXT: vmov.16 q1[0], r5
-; CHECK-MVE-NEXT: vmov.16 q1[1], r1
-; CHECK-MVE-NEXT: vmov.16 q1[2], r4
-; CHECK-MVE-NEXT: vmov.16 q1[3], r3
-; CHECK-MVE-NEXT: vmov.16 q1[4], r0
-; CHECK-MVE-NEXT: vmov.16 q1[5], lr
-; CHECK-MVE-NEXT: vmov.16 q1[6], r2
+; CHECK-MVE-NEXT: vmov.16 q1[1], r4
+; CHECK-MVE-NEXT: vmov.16 q1[2], r1
+; CHECK-MVE-NEXT: vmov.16 q1[3], r0
+; CHECK-MVE-NEXT: vmov.16 q1[4], r3
+; CHECK-MVE-NEXT: vmov.16 q1[5], r2
+; CHECK-MVE-NEXT: vmov.16 q1[6], lr
; CHECK-MVE-NEXT: vmov.16 q1[7], r12
; CHECK-MVE-NEXT: vand q0, q1, q0
; CHECK-MVE-NEXT: pop {r4, r5, r7, pc}
diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpf.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
index baf0076277e50c..6f2539e3cad9aa 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vcmpf.ll
@@ -43,10 +43,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, s5
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: csinc r0, r0, zr, le
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, s7
@@ -230,10 +228,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, s5
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, s7
@@ -271,17 +267,17 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_une_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s3, s7
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s2, s6
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -1090,53 +1086,53 @@ entry:
define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %src2, <8 x half> %a, <8 x half> %b) {
; CHECK-MVE-LABEL: vcmp_une_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: .vsave {d8, d9, d10, d11}
-; CHECK-MVE-NEXT: vpush {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: .vsave {d8, d9}
+; CHECK-MVE-NEXT: vpush {d8, d9}
; CHECK-MVE-NEXT: vmovx.f16 s16, s4
; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16
-; CHECK-MVE-NEXT: vmovx.f16 s20, s8
+; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s22, s12
+; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s5
-; CHECK-MVE-NEXT: vseleq.f16 s16, s22, s20
+; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
; CHECK-MVE-NEXT: vmovx.f16 s8, s1
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
-; CHECK-MVE-NEXT: vins.f16 s0, s16
+; CHECK-MVE-NEXT: vmovx.f16 s4, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vcmp.f16 s1, s5
-; CHECK-MVE-NEXT: vmovx.f16 s12, s9
-; CHECK-MVE-NEXT: vmovx.f16 s16, s13
-; CHECK-MVE-NEXT: vmovx.f16 s8, s2
-; CHECK-MVE-NEXT: vmovx.f16 s5, s14
-; CHECK-MVE-NEXT: vseleq.f16 s4, s16, s12
+; CHECK-MVE-NEXT: vins.f16 s0, s16
+; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s12, s10
+; CHECK-MVE-NEXT: vmovx.f16 s8, s2
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vcmp.f16 s8, s4
-; CHECK-MVE-NEXT: vmovx.f16 s8, s11
+; CHECK-MVE-NEXT: vmovx.f16 s4, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
-; CHECK-MVE-NEXT: vseleq.f16 s4, s5, s12
+; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
-; CHECK-MVE-NEXT: vmovx.f16 s10, s15
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
+; CHECK-MVE-NEXT: vmovx.f16 s4, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vmovx.f16 s6, s15
; CHECK-MVE-NEXT: vcmp.f16 s3, s7
-; CHECK-MVE-NEXT: vseleq.f16 s4, s10, s8
+; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s4
-; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
+; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr
;
; CHECK-MVEFP-LABEL: vcmp_une_v8f16:
diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
index fe82255bff6c8c..d42c393743f4f3 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll
@@ -46,10 +46,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, float %src2
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, s4
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: csinc r0, r0, zr, le
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, s4
@@ -248,10 +246,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, float %src2
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, s4
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, s4
@@ -292,17 +288,17 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_une_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s3, s4
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s2, s4
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s0, s4
+; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -1105,42 +1101,42 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, half %src2, <
; CHECK-MVE-LABEL: vcmp_une_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s8
+; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s7, s12
+; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, s4
-; CHECK-MVE-NEXT: vseleq.f16 s6, s7, s5
+; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
-; CHECK-MVE-NEXT: vmovx.f16 s8, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
-; CHECK-MVE-NEXT: vmovx.f16 s12, s13
+; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s1, s4
-; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
+; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: vmovx.f16 s12, s14
+; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
+; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, s4
-; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
+; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s11
+; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
-; CHECK-MVE-NEXT: vmovx.f16 s10, s15
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s6, s4
+; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, s4
-; CHECK-MVE-NEXT: vseleq.f16 s6, s10, s8
+; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6
@@ -1659,10 +1655,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_one_v4f32(<4 x float> %src, float %sr
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s1
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: csinc r0, r0, zr, le
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s3
@@ -1861,10 +1855,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ueq_v4f32(<4 x float> %src, float %sr
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s1
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s3
@@ -1905,17 +1897,17 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_une_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_une_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s4, s3
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s2
-; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, s1
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vcmp.f32 s4, s3
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s4, s0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
; CHECK-MVE-NEXT: bx lr
;
@@ -2718,42 +2710,42 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, half %src2,
; CHECK-MVE-LABEL: vcmp_r_une_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s6, s0
-; CHECK-MVE-NEXT: vmovx.f16 s5, s8
+; CHECK-MVE-NEXT: vmovx.f16 s5, s12
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s7, s12
+; CHECK-MVE-NEXT: vmovx.f16 s6, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s0
-; CHECK-MVE-NEXT: vseleq.f16 s6, s7, s5
+; CHECK-MVE-NEXT: vseleq.f16 s6, s5, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vseleq.f16 s0, s12, s8
-; CHECK-MVE-NEXT: vmovx.f16 s8, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s13
; CHECK-MVE-NEXT: vins.f16 s0, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
-; CHECK-MVE-NEXT: vmovx.f16 s12, s13
+; CHECK-MVE-NEXT: vmovx.f16 s6, s9
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s1
-; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
+; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s10
-; CHECK-MVE-NEXT: vmovx.f16 s12, s14
+; CHECK-MVE-NEXT: vmovx.f16 s8, s14
; CHECK-MVE-NEXT: vseleq.f16 s1, s13, s9
; CHECK-MVE-NEXT: vins.f16 s1, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s2
-; CHECK-MVE-NEXT: vseleq.f16 s6, s12, s8
+; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s11
+; CHECK-MVE-NEXT: vmovx.f16 s8, s15
; CHECK-MVE-NEXT: vseleq.f16 s2, s14, s10
-; CHECK-MVE-NEXT: vmovx.f16 s10, s15
; CHECK-MVE-NEXT: vins.f16 s2, s6
; CHECK-MVE-NEXT: vmovx.f16 s6, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, s6
+; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s4, s3
-; CHECK-MVE-NEXT: vseleq.f16 s6, s10, s8
+; CHECK-MVE-NEXT: vseleq.f16 s6, s8, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vseleq.f16 s3, s15, s11
; CHECK-MVE-NEXT: vins.f16 s3, s6
diff --git a/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll b/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
index 16689f1e7ecd17..718657839d38db 100644
--- a/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll
@@ -43,10 +43,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_one_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: csinc r0, r0, zr, le
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
@@ -230,10 +228,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_ueq_v4f32(<4 x float> %src, <4 x float>
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
@@ -271,17 +267,17 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_une_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_une_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -1042,42 +1038,42 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_une_v8f16(<8 x half> %src, <8 x half> %a
; CHECK-MVE-LABEL: vcmp_une_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0
-; CHECK-MVE-NEXT: vmovx.f16 s14, s4
+; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0
-; CHECK-MVE-NEXT: vmovx.f16 s13, s8
+; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s14
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vins.f16 s0, s12
+; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s5
-; CHECK-MVE-NEXT: vmovx.f16 s12, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s8
+; CHECK-MVE-NEXT: vins.f16 s0, s12
+; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s6
-; CHECK-MVE-NEXT: vmovx.f16 s12, s10
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
+; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s8
+; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s11
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s7
+; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
+; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s6
+; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4
@@ -1572,10 +1568,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_one_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r0, mi
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: csinc r0, r0, zr, le
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
@@ -1759,10 +1753,8 @@ define arm_aapcs_vfpcc <4 x float> @vcmp_r_ueq_v4f32(<4 x float> %src, <4 x floa
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s1, #0
-; CHECK-MVE-NEXT: cset r0, eq
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: cset r0, eq
; CHECK-MVE-NEXT: csinc r0, r0, zr, vc
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s3, #0
@@ -1800,17 +1792,17 @@ entry:
define arm_aapcs_vfpcc <4 x float> @vcmp_r_une_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_r_une_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry
-; CHECK-MVE-NEXT: vcmp.f32 s3, #0
-; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s2, #0
-; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
+; CHECK-MVE-NEXT: vcmp.f32 s0, #0
+; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
+; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
; CHECK-MVE-NEXT: bx lr
;
@@ -2571,42 +2563,42 @@ define arm_aapcs_vfpcc <8 x half> @vcmp_r_une_v8f16(<8 x half> %src, <8 x half>
; CHECK-MVE-LABEL: vcmp_r_une_v8f16:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vmovx.f16 s12, s0
-; CHECK-MVE-NEXT: vmovx.f16 s14, s4
+; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, #0
-; CHECK-MVE-NEXT: vmovx.f16 s13, s8
+; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s0, #0
-; CHECK-MVE-NEXT: vseleq.f16 s12, s13, s14
+; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vseleq.f16 s0, s8, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s1
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
-; CHECK-MVE-NEXT: vins.f16 s0, s12
+; CHECK-MVE-NEXT: vmovx.f16 s4, s5
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s5
-; CHECK-MVE-NEXT: vmovx.f16 s12, s9
+; CHECK-MVE-NEXT: vmovx.f16 s8, s9
; CHECK-MVE-NEXT: vcmp.f16 s1, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s8
+; CHECK-MVE-NEXT: vins.f16 s0, s12
+; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s6
-; CHECK-MVE-NEXT: vmovx.f16 s12, s10
+; CHECK-MVE-NEXT: vmovx.f16 s8, s10
; CHECK-MVE-NEXT: vseleq.f16 s1, s9, s5
; CHECK-MVE-NEXT: vins.f16 s1, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s2
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
+; CHECK-MVE-NEXT: vmovx.f16 s4, s6
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s2, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s12, s8
+; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
-; CHECK-MVE-NEXT: vmovx.f16 s8, s11
; CHECK-MVE-NEXT: vseleq.f16 s2, s10, s6
-; CHECK-MVE-NEXT: vmovx.f16 s6, s7
+; CHECK-MVE-NEXT: vmovx.f16 s6, s11
; CHECK-MVE-NEXT: vins.f16 s2, s4
; CHECK-MVE-NEXT: vmovx.f16 s4, s3
; CHECK-MVE-NEXT: vcmp.f16 s4, #0
+; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f16 s3, #0
-; CHECK-MVE-NEXT: vseleq.f16 s4, s8, s6
+; CHECK-MVE-NEXT: vseleq.f16 s4, s6, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vseleq.f16 s3, s11, s7
; CHECK-MVE-NEXT: vins.f16 s3, s4
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