[llvm] 18be88e - [NVPTX][NFC] Regenerate some tests checks (#116605)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 18 10:35:48 PST 2024
Author: Fraser Cormack
Date: 2024-11-18T18:35:44Z
New Revision: 18be88e20abd9046217d79954c0477ee01ddd2f3
URL: https://github.com/llvm/llvm-project/commit/18be88e20abd9046217d79954c0477ee01ddd2f3
DIFF: https://github.com/llvm/llvm-project/commit/18be88e20abd9046217d79954c0477ee01ddd2f3.diff
LOG: [NVPTX][NFC] Regenerate some tests checks (#116605)
Use update_llc_test_checks.py to automate the test checks in some files
I was observing changes in locally.
Added:
Modified:
llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
llvm/test/CodeGen/NVPTX/i8x2-instructions.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll b/llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
index a53c90ac6db8b6..3e54aaf5580729 100644
--- a/llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
+++ b/llvm/test/CodeGen/NVPTX/bf16x2-instructions-approx.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -march=nvptx64 -mcpu=sm_80 -mattr=+ptx71 --enable-unsafe-fp-math | FileCheck --check-prefixes=CHECK %s
; RUN: %if ptxas-11.8 %{ llc < %s -march=nvptx64 -mcpu=sm_80 -mattr=+ptx71 --enable-unsafe-fp-math | %ptxas-verify -arch=sm_80 %}
@@ -6,36 +7,48 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
declare <2 x bfloat> @llvm.sin.f16(<2 x bfloat> %a) #0
declare <2 x bfloat> @llvm.cos.f16(<2 x bfloat> %a) #0
-; CHECK-LABEL: test_sin(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_sin_param_0];
-; CHECK: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-DAG: cvt.f32.bf16 [[AF0:%f[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.f32.bf16 [[AF1:%f[0-9]+]], [[A1]];
-; CHECK-DAG: sin.approx.f32 [[RF0:%f[0-9]+]], [[AF0]];
-; CHECK-DAG: sin.approx.f32 [[RF1:%f[0-9]+]], [[AF1]];
-; CHECK-DAG: cvt.rn.bf16.f32 [[R0:%rs[0-9]+]], [[RF0]];
-; CHECK-DAG: cvt.rn.bf16.f32 [[R1:%rs[0-9]+]], [[RF1]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x bfloat> @test_sin(<2 x bfloat> %a) #0 #1 {
+; CHECK-LABEL: test_sin(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-NEXT: .reg .f32 %f<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_sin_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.f32.bf16 %f1, %rs2;
+; CHECK-NEXT: sin.approx.f32 %f2, %f1;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs3, %f2;
+; CHECK-NEXT: cvt.f32.bf16 %f3, %rs1;
+; CHECK-NEXT: sin.approx.f32 %f4, %f3;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs4, %f4;
+; CHECK-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%r = call <2 x bfloat> @llvm.sin.f16(<2 x bfloat> %a)
ret <2 x bfloat> %r
}
-; CHECK-LABEL: test_cos(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_cos_param_0];
-; CHECK: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-DAG: cvt.f32.bf16 [[AF0:%f[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.f32.bf16 [[AF1:%f[0-9]+]], [[A1]];
-; CHECK-DAG: cos.approx.f32 [[RF0:%f[0-9]+]], [[AF0]];
-; CHECK-DAG: cos.approx.f32 [[RF1:%f[0-9]+]], [[AF1]];
-; CHECK-DAG: cvt.rn.bf16.f32 [[R0:%rs[0-9]+]], [[RF0]];
-; CHECK-DAG: cvt.rn.bf16.f32 [[R1:%rs[0-9]+]], [[RF1]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x bfloat> @test_cos(<2 x bfloat> %a) #0 #1 {
+; CHECK-LABEL: test_cos(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-NEXT: .reg .f32 %f<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_cos_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.f32.bf16 %f1, %rs2;
+; CHECK-NEXT: cos.approx.f32 %f2, %f1;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs3, %f2;
+; CHECK-NEXT: cvt.f32.bf16 %f3, %rs1;
+; CHECK-NEXT: cos.approx.f32 %f4, %f3;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs4, %f4;
+; CHECK-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%r = call <2 x bfloat> @llvm.cos.f16(<2 x bfloat> %a)
ret <2 x bfloat> %r
}
diff --git a/llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll b/llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
index 925ae4245a4c20..e545d4c1177915 100644
--- a/llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -march=nvptx64 -mcpu=sm_80 -mattr=+ptx71 | FileCheck --check-prefixes=CHECK,SM80 %s
; RUN: llc < %s -march=nvptx64 -mcpu=sm_90 -mattr=+ptx78 | FileCheck --check-prefixes=CHECK,SM90 %s
; RUN: %if ptxas-11.8 %{ llc < %s -march=nvptx64 -mcpu=sm_80 -mattr=+ptx71 | %ptxas-verify -arch=sm_80 %}
@@ -5,163 +6,231 @@
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
-; CHECK-LABEL: test_ret_const(
-; CHECK: mov.b32 [[T:%r[0-9+]]], 1073758080;
-; CHECK: st.param.b32 [func_retval0], [[T]];
-; CHECK-NEXT: ret;
-
define <2 x bfloat> @test_ret_const() #0 {
+; CHECK-LABEL: test_ret_const(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: mov.b32 %r1, 1073758080;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
ret <2 x bfloat> <bfloat 1.0, bfloat 2.0>
}
; Check that we can lower fadd with immediate arguments.
-; CHECK-LABEL: test_fadd_imm_0(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fadd_imm_0_param_0];
-;
-; SM90-DAG: mov.b32 [[I:%r[0-9+]]], 1073758080;
-; SM90-DAG: add.rn.bf16x2 [[R:%r[0-9]+]], [[A]], [[I]];
-;
-; SM80-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; SM80-DAG: cvt.f32.bf16 [[FA0:%f[0-9]+]], [[A0]]
-; SM80-DAG: cvt.f32.bf16 [[FA1:%f[0-9]+]], [[A1]]
-; SM80-DAG: add.rn.f32 [[FR0:%f[0-9]+]], [[FA0]], 0f3F800000;
-; SM80-DAG: add.rn.f32 [[FR1:%f[0-9]+]], [[FA1]], 0f40000000;
-; SM80-DAG: cvt.rn.bf16.f32 [[R0:%rs[0-9]+]], [[FR0]]
-; SM80-DAG: cvt.rn.bf16.f32 [[R1:%rs[0-9]+]], [[FR1]]
-; SM80-DAG: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-;
-; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];
-; CHECK-NEXT: ret;
-
define <2 x bfloat> @test_fadd_imm_0(<2 x bfloat> %a) #0 {
+; SM80-LABEL: test_fadd_imm_0(
+; SM80: {
+; SM80-NEXT: .reg .b16 %rs<5>;
+; SM80-NEXT: .reg .b32 %r<3>;
+; SM80-NEXT: .reg .f32 %f<5>;
+; SM80-EMPTY:
+; SM80-NEXT: // %bb.0:
+; SM80-NEXT: ld.param.b32 %r1, [test_fadd_imm_0_param_0];
+; SM80-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; SM80-NEXT: cvt.f32.bf16 %f1, %rs2;
+; SM80-NEXT: add.rn.f32 %f2, %f1, 0f40000000;
+; SM80-NEXT: cvt.rn.bf16.f32 %rs3, %f2;
+; SM80-NEXT: cvt.f32.bf16 %f3, %rs1;
+; SM80-NEXT: add.rn.f32 %f4, %f3, 0f3F800000;
+; SM80-NEXT: cvt.rn.bf16.f32 %rs4, %f4;
+; SM80-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; SM80-NEXT: st.param.b32 [func_retval0], %r2;
+; SM80-NEXT: ret;
+;
+; SM90-LABEL: test_fadd_imm_0(
+; SM90: {
+; SM90-NEXT: .reg .b32 %r<4>;
+; SM90-EMPTY:
+; SM90-NEXT: // %bb.0:
+; SM90-NEXT: ld.param.b32 %r1, [test_fadd_imm_0_param_0];
+; SM90-NEXT: mov.b32 %r2, 1073758080;
+; SM90-NEXT: add.rn.bf16x2 %r3, %r1, %r2;
+; SM90-NEXT: st.param.b32 [func_retval0], %r3;
+; SM90-NEXT: ret;
%r = fadd <2 x bfloat> <bfloat 1.0, bfloat 2.0>, %a
ret <2 x bfloat> %r
}
-; CHECK-LABEL: test_fadd_imm_1(
-; CHECK: ld.param.b16 [[A:%rs[0-9]+]], [test_fadd_imm_1_param_0];
-; SM90: mov.b16 [[B:%rs[0-9]+]], 0x3F80;
-; SM90: add.rn.bf16 [[R:%rs[0-9]+]], [[A]], [[B]];
-
-; SM80-DAG: cvt.f32.bf16 [[FA:%f[0-9]+]], [[A]];
-; SM80: add.rn.f32 [[FR:%f[0-9]+]], [[FA]], 0f3F800000;
-; SM80: cvt.rn.bf16.f32 [[R:%rs[0-9]+]], [[FR]];
-
-; CHECK: st.param.b16 [func_retval0], [[R]];
-; CHECK-NEXT: ret;
-
define bfloat @test_fadd_imm_1(bfloat %a) #0 {
+; SM80-LABEL: test_fadd_imm_1(
+; SM80: {
+; SM80-NEXT: .reg .b16 %rs<3>;
+; SM80-NEXT: .reg .f32 %f<3>;
+; SM80-EMPTY:
+; SM80-NEXT: // %bb.0:
+; SM80-NEXT: ld.param.b16 %rs1, [test_fadd_imm_1_param_0];
+; SM80-NEXT: cvt.f32.bf16 %f1, %rs1;
+; SM80-NEXT: add.rn.f32 %f2, %f1, 0f3F800000;
+; SM80-NEXT: cvt.rn.bf16.f32 %rs2, %f2;
+; SM80-NEXT: st.param.b16 [func_retval0], %rs2;
+; SM80-NEXT: ret;
+;
+; SM90-LABEL: test_fadd_imm_1(
+; SM90: {
+; SM90-NEXT: .reg .b16 %rs<4>;
+; SM90-EMPTY:
+; SM90-NEXT: // %bb.0:
+; SM90-NEXT: ld.param.b16 %rs1, [test_fadd_imm_1_param_0];
+; SM90-NEXT: mov.b16 %rs2, 0x3F80;
+; SM90-NEXT: add.rn.bf16 %rs3, %rs1, %rs2;
+; SM90-NEXT: st.param.b16 [func_retval0], %rs3;
+; SM90-NEXT: ret;
%r = fadd bfloat %a, 1.0
ret bfloat %r
}
-; CHECK-LABEL: test_fsubx2(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fsubx2_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fsubx2_param_1];
-; SM90: sub.rn.bf16x2 [[R:%r[0-9]+]], [[A]], [[B]];
-
-; SM80-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]];
-; SM80-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]];
-; SM80-DAG: cvt.f32.bf16 [[FA1:%f[0-9]+]], [[A1]];
-; SM80-DAG: cvt.f32.bf16 [[FA0:%f[0-9]+]], [[A0]];
-; SM80-DAG: cvt.f32.bf16 [[FB0:%f[0-9]+]], [[B0]];
-; SM80-DAG: cvt.f32.bf16 [[FB1:%f[0-9]+]], [[B1]];
-; SM80-DAG: sub.rn.f32 [[FR0:%f[0-9]+]], [[FA0]], [[FB0]];
-; SM80-DAG: sub.rn.f32 [[FR1:%f[0-9]+]], [[FA1]], [[FB1]];
-; SM80-DAG: cvt.rn.bf16.f32 [[R0:%rs[0-9]+]], [[FR0]];
-; SM80-DAG: cvt.rn.bf16.f32 [[R1:%rs[0-9]+]], [[FR1]];
-; SM80: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]};
-
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
-
define <2 x bfloat> @test_fsubx2(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
+; SM80-LABEL: test_fsubx2(
+; SM80: {
+; SM80-NEXT: .reg .b16 %rs<7>;
+; SM80-NEXT: .reg .b32 %r<4>;
+; SM80-NEXT: .reg .f32 %f<7>;
+; SM80-EMPTY:
+; SM80-NEXT: // %bb.0:
+; SM80-NEXT: ld.param.b32 %r1, [test_fsubx2_param_0];
+; SM80-NEXT: ld.param.b32 %r2, [test_fsubx2_param_1];
+; SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; SM80-NEXT: cvt.f32.bf16 %f1, %rs2;
+; SM80-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; SM80-NEXT: cvt.f32.bf16 %f2, %rs4;
+; SM80-NEXT: sub.rn.f32 %f3, %f2, %f1;
+; SM80-NEXT: cvt.rn.bf16.f32 %rs5, %f3;
+; SM80-NEXT: cvt.f32.bf16 %f4, %rs1;
+; SM80-NEXT: cvt.f32.bf16 %f5, %rs3;
+; SM80-NEXT: sub.rn.f32 %f6, %f5, %f4;
+; SM80-NEXT: cvt.rn.bf16.f32 %rs6, %f6;
+; SM80-NEXT: mov.b32 %r3, {%rs6, %rs5};
+; SM80-NEXT: st.param.b32 [func_retval0], %r3;
+; SM80-NEXT: ret;
+;
+; SM90-LABEL: test_fsubx2(
+; SM90: {
+; SM90-NEXT: .reg .b32 %r<4>;
+; SM90-EMPTY:
+; SM90-NEXT: // %bb.0:
+; SM90-NEXT: ld.param.b32 %r1, [test_fsubx2_param_1];
+; SM90-NEXT: ld.param.b32 %r2, [test_fsubx2_param_0];
+; SM90-NEXT: sub.rn.bf16x2 %r3, %r2, %r1;
+; SM90-NEXT: st.param.b32 [func_retval0], %r3;
+; SM90-NEXT: ret;
%r = fsub <2 x bfloat> %a, %b
ret <2 x bfloat> %r
}
-; CHECK-LABEL: test_fmulx2(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fmulx2_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fmulx2_param_1];
-; SM90: mul.rn.bf16x2 [[R:%r[0-9]+]], [[A]], [[B]];
-
-; SM80-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]];
-; SM80-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]];
-; SM80-DAG: cvt.f32.bf16 [[FA1:%f[0-9]+]], [[A1]];
-; SM80-DAG: cvt.f32.bf16 [[FA0:%f[0-9]+]], [[A0]];
-; SM80-DAG: cvt.f32.bf16 [[FB0:%f[0-9]+]], [[B0]];
-; SM80-DAG: cvt.f32.bf16 [[FB1:%f[0-9]+]], [[B1]];
-; SM80-DAG: mul.rn.f32 [[FR0:%f[0-9]+]], [[FA0]], [[FB0]];
-; SM80-DAG: mul.rn.f32 [[FR1:%f[0-9]+]], [[FA1]], [[FB1]];
-; SM80-DAG: cvt.rn.bf16.f32 [[R0:%rs[0-9]+]], [[FR0]];
-; SM80-DAG: cvt.rn.bf16.f32 [[R1:%rs[0-9]+]], [[FR1]];
-; SM80: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]};
-
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
-
define <2 x bfloat> @test_fmulx2(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
+; SM80-LABEL: test_fmulx2(
+; SM80: {
+; SM80-NEXT: .reg .b16 %rs<7>;
+; SM80-NEXT: .reg .b32 %r<4>;
+; SM80-NEXT: .reg .f32 %f<7>;
+; SM80-EMPTY:
+; SM80-NEXT: // %bb.0:
+; SM80-NEXT: ld.param.b32 %r1, [test_fmulx2_param_0];
+; SM80-NEXT: ld.param.b32 %r2, [test_fmulx2_param_1];
+; SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; SM80-NEXT: cvt.f32.bf16 %f1, %rs2;
+; SM80-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; SM80-NEXT: cvt.f32.bf16 %f2, %rs4;
+; SM80-NEXT: mul.rn.f32 %f3, %f2, %f1;
+; SM80-NEXT: cvt.rn.bf16.f32 %rs5, %f3;
+; SM80-NEXT: cvt.f32.bf16 %f4, %rs1;
+; SM80-NEXT: cvt.f32.bf16 %f5, %rs3;
+; SM80-NEXT: mul.rn.f32 %f6, %f5, %f4;
+; SM80-NEXT: cvt.rn.bf16.f32 %rs6, %f6;
+; SM80-NEXT: mov.b32 %r3, {%rs6, %rs5};
+; SM80-NEXT: st.param.b32 [func_retval0], %r3;
+; SM80-NEXT: ret;
+;
+; SM90-LABEL: test_fmulx2(
+; SM90: {
+; SM90-NEXT: .reg .b32 %r<4>;
+; SM90-EMPTY:
+; SM90-NEXT: // %bb.0:
+; SM90-NEXT: ld.param.b32 %r1, [test_fmulx2_param_1];
+; SM90-NEXT: ld.param.b32 %r2, [test_fmulx2_param_0];
+; SM90-NEXT: mul.rn.bf16x2 %r3, %r2, %r1;
+; SM90-NEXT: st.param.b32 [func_retval0], %r3;
+; SM90-NEXT: ret;
%r = fmul <2 x bfloat> %a, %b
ret <2 x bfloat> %r
}
-; CHECK-LABEL: test_fdiv(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fdiv_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fdiv_param_1];
-; CHECK-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-DAG: cvt.f32.bf16 [[FA0:%f[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.f32.bf16 [[FA1:%f[0-9]+]], [[A1]];
-; CHECK-DAG: cvt.f32.bf16 [[FB0:%f[0-9]+]], [[B0]];
-; CHECK-DAG: cvt.f32.bf16 [[FB1:%f[0-9]+]], [[B1]];
-; CHECK-DAG: div.rn.f32 [[FR0:%f[0-9]+]], [[FA0]], [[FB0]];
-; CHECK-DAG: div.rn.f32 [[FR1:%f[0-9]+]], [[FA1]], [[FB1]];
-; CHECK-DAG: cvt.rn.bf16.f32 [[R0:%rs[0-9]+]], [[FR0]];
-; CHECK-DAG: cvt.rn.bf16.f32 [[R1:%rs[0-9]+]], [[FR1]];
-; CHECK-NEXT: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];
-; CHECK-NEXT: ret;
-
define <2 x bfloat> @test_fdiv(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
+; CHECK-LABEL: test_fdiv(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<7>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-NEXT: .reg .f32 %f<7>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_fdiv_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [test_fdiv_param_1];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NEXT: cvt.f32.bf16 %f1, %rs2;
+; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NEXT: cvt.f32.bf16 %f2, %rs4;
+; CHECK-NEXT: div.rn.f32 %f3, %f2, %f1;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs5, %f3;
+; CHECK-NEXT: cvt.f32.bf16 %f4, %rs1;
+; CHECK-NEXT: cvt.f32.bf16 %f5, %rs3;
+; CHECK-NEXT: div.rn.f32 %f6, %f5, %f4;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs6, %f6;
+; CHECK-NEXT: mov.b32 %r3, {%rs6, %rs5};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%r = fdiv <2 x bfloat> %a, %b
ret <2 x bfloat> %r
}
-; CHECK-LABEL: test_fneg(
-; CHECK-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_fneg_param_0];
-
-; CHECK-DAG: xor.b32 [[IHH0:%r[0-9]+]], [[A]], -2147450880;
-; CHECK-NEXT: st.param.b32 [func_retval0], [[IHH0]];
-; CHECK-NEXT: ret;
define <2 x bfloat> @test_fneg(<2 x bfloat> %a) #0 {
+; CHECK-LABEL: test_fneg(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.u32 %r1, [test_fneg_param_0];
+; CHECK-NEXT: xor.b32 %r2, %r1, -2147450880;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%r = fneg <2 x bfloat> %a
ret <2 x bfloat> %r
}
-; CHECK-LABEL: .func test_ldst_v2bf16(
-; CHECK-DAG: ld.param.u64 %[[A:rd[0-9]+]], [test_ldst_v2bf16_param_0];
-; CHECK-DAG: ld.param.u64 %[[B:rd[0-9]+]], [test_ldst_v2bf16_param_1];
-; CHECK-DAG: ld.b32 [[E:%r[0-9]+]], [%[[A]]]
-; CHECK-DAG: st.b32 [%[[B]]], [[E]];
-; CHECK: ret;
define void @test_ldst_v2bf16(ptr %a, ptr %b) {
+; CHECK-LABEL: test_ldst_v2bf16(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.u64 %rd1, [test_ldst_v2bf16_param_0];
+; CHECK-NEXT: ld.b32 %r1, [%rd1];
+; CHECK-NEXT: ld.param.u64 %rd2, [test_ldst_v2bf16_param_1];
+; CHECK-NEXT: st.b32 [%rd2], %r1;
+; CHECK-NEXT: ret;
%t1 = load <2 x bfloat>, ptr %a
store <2 x bfloat> %t1, ptr %b, align 16
ret void
}
-; CHECK-LABEL: .func test_ldst_v3bf16(
-; CHECK-DAG: ld.param.u64 %[[A:rd[0-9]+]], [test_ldst_v3bf16_param_0];
-; CHECK-DAG: ld.param.u64 %[[B:rd[0-9]+]], [test_ldst_v3bf16_param_1];
-; -- v3 is inconvenient to capture as it's lowered as ld.b64 + fair
-; number of bitshifting instructions that may change at llvm's whim.
-; So we only verify that we only issue correct number of writes using
-; correct offset, but not the values we write.
-; CHECK-DAG: ld.u64
-; CHECK-DAG: st.u32 [%[[B]]],
-; CHECK-DAG: st.b16 [%[[B]]+4],
-; CHECK: ret;
define void @test_ldst_v3bf16(ptr %a, ptr %b) {
+; CHECK-LABEL: test_ldst_v3bf16(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-NEXT: .reg .b64 %rd<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.u64 %rd1, [test_ldst_v3bf16_param_0];
+; CHECK-NEXT: ld.u64 %rd2, [%rd1];
+; CHECK-NEXT: { .reg .b32 tmp; mov.b64 {tmp, %r1}, %rd2; }
+; CHECK-NEXT: ld.param.u64 %rd3, [test_ldst_v3bf16_param_1];
+; CHECK-NEXT: st.u32 [%rd3], %rd2;
+; CHECK-NEXT: { .reg .b16 tmp; mov.b32 {%rs1, tmp}, %r1; }
+; CHECK-NEXT: st.b16 [%rd3+4], %rs1;
+; CHECK-NEXT: ret;
%t1 = load <3 x bfloat>, ptr %a
store <3 x bfloat> %t1, ptr %b, align 16
ret void
@@ -169,161 +238,241 @@ define void @test_ldst_v3bf16(ptr %a, ptr %b) {
declare <2 x bfloat> @test_callee(<2 x bfloat> %a, <2 x bfloat> %b) #0
-; CHECK-LABEL: test_call(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_call_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_call_param_1];
-; CHECK: {
-; CHECK-DAG: .param .align 4 .b8 param0[4];
-; CHECK-DAG: .param .align 4 .b8 param1[4];
-; CHECK-DAG: st.param.b32 [param0], [[A]];
-; CHECK-DAG: st.param.b32 [param1], [[B]];
-; CHECK-DAG: .param .align 4 .b8 retval0[4];
-; CHECK: call.uni (retval0),
-; CHECK-NEXT: test_callee,
-; CHECK: );
-; CHECK-NEXT: ld.param.b32 [[R:%r[0-9]+]], [retval0];
-; CHECK-NEXT: }
-; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];
-; CHECK-NEXT: ret;
-
define <2 x bfloat> @test_call(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
+; CHECK-LABEL: test_call(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_call_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [test_call_param_1];
+; CHECK-NEXT: { // callseq 0, 0
+; CHECK-NEXT: .param .align 4 .b8 param0[4];
+; CHECK-NEXT: st.param.b32 [param0], %r1;
+; CHECK-NEXT: .param .align 4 .b8 param1[4];
+; CHECK-NEXT: st.param.b32 [param1], %r2;
+; CHECK-NEXT: .param .align 4 .b8 retval0[4];
+; CHECK-NEXT: call.uni (retval0),
+; CHECK-NEXT: test_callee,
+; CHECK-NEXT: (
+; CHECK-NEXT: param0,
+; CHECK-NEXT: param1
+; CHECK-NEXT: );
+; CHECK-NEXT: ld.param.b32 %r3, [retval0];
+; CHECK-NEXT: } // callseq 0
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%r = call <2 x bfloat> @test_callee(<2 x bfloat> %a, <2 x bfloat> %b)
ret <2 x bfloat> %r
}
-; CHECK-LABEL: test_select(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_select_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_select_param_1];
-; CHECK-DAG: ld.param.u8 [[C:%rs[0-9]+]], [test_select_param_2]
-; CHECK-DAG: setp.eq.b16 [[PRED:%p[0-9]+]], %rs{{.*}}, 1;
-; CHECK-NEXT: selp.b32 [[R:%r[0-9]+]], [[A]], [[B]], [[PRED]];
-; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];
-; CHECK-NEXT: ret;
-
define <2 x bfloat> @test_select(<2 x bfloat> %a, <2 x bfloat> %b, i1 zeroext %c) #0 {
+; CHECK-LABEL: test_select(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.u8 %rs1, [test_select_param_2];
+; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
+; CHECK-NEXT: setp.eq.b16 %p1, %rs2, 1;
+; CHECK-NEXT: ld.param.b32 %r1, [test_select_param_1];
+; CHECK-NEXT: ld.param.b32 %r2, [test_select_param_0];
+; CHECK-NEXT: selp.b32 %r3, %r2, %r1, %p1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%r = select i1 %c, <2 x bfloat> %a, <2 x bfloat> %b
ret <2 x bfloat> %r
}
-; CHECK-LABEL: test_select_cc(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_select_cc_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_select_cc_param_1];
-; CHECK-DAG: ld.param.b32 [[C:%r[0-9]+]], [test_select_cc_param_2];
-; CHECK-DAG: ld.param.b32 [[D:%r[0-9]+]], [test_select_cc_param_3];
-;
-; SM90: setp.neu.bf16x2 [[P0:%p[0-9]+]]|[[P1:%p[0-9]+]], [[C]], [[D]]
-;
-; SM80-DAG: mov.b32 {[[C0:%rs[0-9]+]], [[C1:%rs[0-9]+]]}, [[C]]
-; SM80-DAG: mov.b32 {[[D0:%rs[0-9]+]], [[D1:%rs[0-9]+]]}, [[D]]
-; SM80-DAG: cvt.f32.bf16 [[DF0:%f[0-9]+]], [[D0]];
-; SM80-DAG: cvt.f32.bf16 [[CF0:%f[0-9]+]], [[C0]];
-; SM80-DAG: cvt.f32.bf16 [[DF1:%f[0-9]+]], [[D1]];
-; SM80-DAG: cvt.f32.bf16 [[CF1:%f[0-9]+]], [[C1]];
-; SM80-DAG: setp.neu.f32 [[P0:%p[0-9]+]], [[CF0]], [[DF0]]
-; SM80-DAG: setp.neu.f32 [[P1:%p[0-9]+]], [[CF1]], [[DF1]]
-;
-; CHECK-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-DAG: selp.b16 [[R0:%rs[0-9]+]], [[A0]], [[B0]], [[P0]];
-; CHECK-DAG: selp.b16 [[R1:%rs[0-9]+]], [[A1]], [[B1]], [[P1]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];
-; CHECK-NEXT: ret;
-
define <2 x bfloat> @test_select_cc(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c, <2 x bfloat> %d) #0 {
+; SM80-LABEL: test_select_cc(
+; SM80: {
+; SM80-NEXT: .reg .pred %p<3>;
+; SM80-NEXT: .reg .b16 %rs<11>;
+; SM80-NEXT: .reg .b32 %r<6>;
+; SM80-NEXT: .reg .f32 %f<5>;
+; SM80-EMPTY:
+; SM80-NEXT: // %bb.0:
+; SM80-NEXT: ld.param.b32 %r1, [test_select_cc_param_0];
+; SM80-NEXT: ld.param.b32 %r2, [test_select_cc_param_1];
+; SM80-NEXT: ld.param.b32 %r3, [test_select_cc_param_2];
+; SM80-NEXT: ld.param.b32 %r4, [test_select_cc_param_3];
+; SM80-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; SM80-NEXT: cvt.f32.bf16 %f1, %rs1;
+; SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; SM80-NEXT: cvt.f32.bf16 %f2, %rs3;
+; SM80-NEXT: setp.neu.f32 %p1, %f2, %f1;
+; SM80-NEXT: cvt.f32.bf16 %f3, %rs2;
+; SM80-NEXT: cvt.f32.bf16 %f4, %rs4;
+; SM80-NEXT: setp.neu.f32 %p2, %f4, %f3;
+; SM80-NEXT: mov.b32 {%rs5, %rs6}, %r2;
+; SM80-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; SM80-NEXT: selp.b16 %rs9, %rs8, %rs6, %p2;
+; SM80-NEXT: selp.b16 %rs10, %rs7, %rs5, %p1;
+; SM80-NEXT: mov.b32 %r5, {%rs10, %rs9};
+; SM80-NEXT: st.param.b32 [func_retval0], %r5;
+; SM80-NEXT: ret;
+;
+; SM90-LABEL: test_select_cc(
+; SM90: {
+; SM90-NEXT: .reg .pred %p<3>;
+; SM90-NEXT: .reg .b16 %rs<7>;
+; SM90-NEXT: .reg .b32 %r<6>;
+; SM90-EMPTY:
+; SM90-NEXT: // %bb.0:
+; SM90-NEXT: ld.param.b32 %r1, [test_select_cc_param_0];
+; SM90-NEXT: ld.param.b32 %r2, [test_select_cc_param_1];
+; SM90-NEXT: ld.param.b32 %r3, [test_select_cc_param_3];
+; SM90-NEXT: ld.param.b32 %r4, [test_select_cc_param_2];
+; SM90-NEXT: setp.neu.bf16x2 %p1|%p2, %r4, %r3;
+; SM90-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; SM90-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; SM90-NEXT: selp.b16 %rs5, %rs4, %rs2, %p2;
+; SM90-NEXT: selp.b16 %rs6, %rs3, %rs1, %p1;
+; SM90-NEXT: mov.b32 %r5, {%rs6, %rs5};
+; SM90-NEXT: st.param.b32 [func_retval0], %r5;
+; SM90-NEXT: ret;
%cc = fcmp une <2 x bfloat> %c, %d
%r = select <2 x i1> %cc, <2 x bfloat> %a, <2 x bfloat> %b
ret <2 x bfloat> %r
}
-
-; CHECK-LABEL: test_select_cc_f32_bf16(
-; CHECK-DAG: ld.param.v2.f32 {[[A0:%f[0-9]+]], [[A1:%f[0-9]+]]}, [test_select_cc_f32_bf16_param_0];
-; CHECK-DAG: ld.param.b32 [[C:%r[0-9]+]], [test_select_cc_f32_bf16_param_2];
-; CHECK-DAG: ld.param.b32 [[D:%r[0-9]+]], [test_select_cc_f32_bf16_param_3];
-; SM90: setp.neu.bf16x2 [[P0:%p[0-9]+]]|[[P1:%p[0-9]+]], [[C]], [[D]]
-; CHECK-DAG: ld.param.v2.f32 {[[B0:%f[0-9]+]], [[B1:%f[0-9]+]]}, [test_select_cc_f32_bf16_param_1];
-
-; SM80-DAG: mov.b32 {[[C0:%rs[0-9]+]], [[C1:%rs[0-9]+]]}, [[C]]
-; SM80-DAG: mov.b32 {[[D0:%rs[0-9]+]], [[D1:%rs[0-9]+]]}, [[D]]
-; SM80-DAG: cvt.f32.bf16 [[DF0:%f[0-9]+]], [[D0]];
-; SM80-DAG: cvt.f32.bf16 [[CF0:%f[0-9]+]], [[C0]];
-; SM80-DAG: cvt.f32.bf16 [[DF1:%f[0-9]+]], [[D1]];
-; SM80-DAG: cvt.f32.bf16 [[CF1:%f[0-9]+]], [[C1]];
-; SM80-DAG: setp.neu.f32 [[P0:%p[0-9]+]], [[CF0]], [[DF0]]
-; SM80-DAG: setp.neu.f32 [[P1:%p[0-9]+]], [[CF1]], [[DF1]]
-;
-; CHECK-DAG: selp.f32 [[R0:%f[0-9]+]], [[A0]], [[B0]], [[P0]];
-; CHECK-DAG: selp.f32 [[R1:%f[0-9]+]], [[A1]], [[B1]], [[P1]];
-; CHECK-NEXT: st.param.v2.f32 [func_retval0], {[[R0]], [[R1]]};
-; CHECK-NEXT: ret;
define <2 x float> @test_select_cc_f32_bf16(<2 x float> %a, <2 x float> %b,
+; SM80-LABEL: test_select_cc_f32_bf16(
+; SM80: {
+; SM80-NEXT: .reg .pred %p<3>;
+; SM80-NEXT: .reg .b16 %rs<5>;
+; SM80-NEXT: .reg .b32 %r<3>;
+; SM80-NEXT: .reg .f32 %f<11>;
+; SM80-EMPTY:
+; SM80-NEXT: // %bb.0:
+; SM80-NEXT: ld.param.v2.f32 {%f1, %f2}, [test_select_cc_f32_bf16_param_0];
+; SM80-NEXT: ld.param.b32 %r1, [test_select_cc_f32_bf16_param_2];
+; SM80-NEXT: ld.param.b32 %r2, [test_select_cc_f32_bf16_param_3];
+; SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; SM80-NEXT: cvt.f32.bf16 %f3, %rs1;
+; SM80-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; SM80-NEXT: cvt.f32.bf16 %f4, %rs3;
+; SM80-NEXT: setp.neu.f32 %p1, %f4, %f3;
+; SM80-NEXT: cvt.f32.bf16 %f5, %rs2;
+; SM80-NEXT: cvt.f32.bf16 %f6, %rs4;
+; SM80-NEXT: setp.neu.f32 %p2, %f6, %f5;
+; SM80-NEXT: ld.param.v2.f32 {%f7, %f8}, [test_select_cc_f32_bf16_param_1];
+; SM80-NEXT: selp.f32 %f9, %f2, %f8, %p2;
+; SM80-NEXT: selp.f32 %f10, %f1, %f7, %p1;
+; SM80-NEXT: st.param.v2.f32 [func_retval0], {%f10, %f9};
+; SM80-NEXT: ret;
+;
+; SM90-LABEL: test_select_cc_f32_bf16(
+; SM90: {
+; SM90-NEXT: .reg .pred %p<3>;
+; SM90-NEXT: .reg .b32 %r<3>;
+; SM90-NEXT: .reg .f32 %f<7>;
+; SM90-EMPTY:
+; SM90-NEXT: // %bb.0:
+; SM90-NEXT: ld.param.v2.f32 {%f1, %f2}, [test_select_cc_f32_bf16_param_0];
+; SM90-NEXT: ld.param.b32 %r1, [test_select_cc_f32_bf16_param_3];
+; SM90-NEXT: ld.param.b32 %r2, [test_select_cc_f32_bf16_param_2];
+; SM90-NEXT: setp.neu.bf16x2 %p1|%p2, %r2, %r1;
+; SM90-NEXT: ld.param.v2.f32 {%f3, %f4}, [test_select_cc_f32_bf16_param_1];
+; SM90-NEXT: selp.f32 %f5, %f2, %f4, %p2;
+; SM90-NEXT: selp.f32 %f6, %f1, %f3, %p1;
+; SM90-NEXT: st.param.v2.f32 [func_retval0], {%f6, %f5};
+; SM90-NEXT: ret;
<2 x bfloat> %c, <2 x bfloat> %d) #0 {
%cc = fcmp une <2 x bfloat> %c, %d
%r = select <2 x i1> %cc, <2 x float> %a, <2 x float> %b
ret <2 x float> %r
}
-; CHECK-LABEL: test_select_cc_bf16_f32(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_select_cc_bf16_f32_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_select_cc_bf16_f32_param_1];
-; CHECK-DAG: ld.param.v2.f32 {[[C0:%f[0-9]+]], [[C1:%f[0-9]+]]}, [test_select_cc_bf16_f32_param_2];
-; CHECK-DAG: ld.param.v2.f32 {[[D0:%f[0-9]+]], [[D1:%f[0-9]+]]}, [test_select_cc_bf16_f32_param_3];
-; CHECK-DAG: setp.neu.f32 [[P0:%p[0-9]+]], [[C0]], [[D0]]
-; CHECK-DAG: setp.neu.f32 [[P1:%p[0-9]+]], [[C1]], [[D1]]
-; CHECK-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-DAG: selp.b16 [[R0:%rs[0-9]+]], [[A0]], [[B0]], [[P0]];
-; CHECK-DAG: selp.b16 [[R1:%rs[0-9]+]], [[A1]], [[B1]], [[P1]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];
-; CHECK-NEXT: ret;
define <2 x bfloat> @test_select_cc_bf16_f32(<2 x bfloat> %a, <2 x bfloat> %b,
+; CHECK-LABEL: test_select_cc_bf16_f32(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<7>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-NEXT: .reg .f32 %f<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_select_cc_bf16_f32_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [test_select_cc_bf16_f32_param_1];
+; CHECK-NEXT: ld.param.v2.f32 {%f1, %f2}, [test_select_cc_bf16_f32_param_2];
+; CHECK-NEXT: ld.param.v2.f32 {%f3, %f4}, [test_select_cc_bf16_f32_param_3];
+; CHECK-NEXT: setp.neu.f32 %p1, %f1, %f3;
+; CHECK-NEXT: setp.neu.f32 %p2, %f2, %f4;
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NEXT: selp.b16 %rs5, %rs4, %rs2, %p2;
+; CHECK-NEXT: selp.b16 %rs6, %rs3, %rs1, %p1;
+; CHECK-NEXT: mov.b32 %r3, {%rs6, %rs5};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
<2 x float> %c, <2 x float> %d) #0 {
%cc = fcmp une <2 x float> %c, %d
%r = select <2 x i1> %cc, <2 x bfloat> %a, <2 x bfloat> %b
ret <2 x bfloat> %r
}
-; CHECK-LABEL: test_fptrunc_2xfloat(
-; CHECK: ld.param.v2.f32 {[[A0:%f[0-9]+]], [[A1:%f[0-9]+]]}, [test_fptrunc_2xfloat_param_0];
-; CHECK-DAG: cvt.rn.bf16.f32 [[R0:%rs[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.rn.bf16.f32 [[R1:%rs[0-9]+]], [[A1]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x bfloat> @test_fptrunc_2xfloat(<2 x float> %a) #0 {
+; CHECK-LABEL: test_fptrunc_2xfloat(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .f32 %f<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.v2.f32 {%f1, %f2}, [test_fptrunc_2xfloat_param_0];
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs1, %f2;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs2, %f1;
+; CHECK-NEXT: mov.b32 %r1, {%rs2, %rs1};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
%r = fptrunc <2 x float> %a to <2 x bfloat>
ret <2 x bfloat> %r
}
-; CHECK-LABEL: test_fpext_2xfloat(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_fpext_2xfloat_param_0];
-; CHECK: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-DAG: cvt.f32.bf16 [[R0:%f[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.f32.bf16 [[R1:%f[0-9]+]], [[A1]];
-; CHECK-NEXT: st.param.v2.f32 [func_retval0], {[[R0]], [[R1]]};
-; CHECK: ret;
define <2 x float> @test_fpext_2xfloat(<2 x bfloat> %a) #0 {
+; CHECK-LABEL: test_fpext_2xfloat(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .f32 %f<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_fpext_2xfloat_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.f32.bf16 %f1, %rs2;
+; CHECK-NEXT: cvt.f32.bf16 %f2, %rs1;
+; CHECK-NEXT: st.param.v2.f32 [func_retval0], {%f2, %f1};
+; CHECK-NEXT: ret;
%r = fpext <2 x bfloat> %a to <2 x float>
ret <2 x float> %r
}
-; CHECK-LABEL: test_bitcast_2xbf16_to_2xi16(
-; CHECK: ld.param.u32 [[A:%r[0-9]+]], [test_bitcast_2xbf16_to_2xi16_param_0];
-; CHECK: st.param.b32 [func_retval0], [[A]]
-; CHECK: ret;
define <2 x i16> @test_bitcast_2xbf16_to_2xi16(<2 x bfloat> %a) #0 {
+; CHECK-LABEL: test_bitcast_2xbf16_to_2xi16(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.u32 %r1, [test_bitcast_2xbf16_to_2xi16_param_0];
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
%r = bitcast <2 x bfloat> %a to <2 x i16>
ret <2 x i16> %r
}
-
-; CHECK-LABEL: test_bitcast_2xi16_to_2xbf16(
-; CHECK: ld.param.b32 [[R]], [test_bitcast_2xi16_to_2xbf16_param_0];
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x bfloat> @test_bitcast_2xi16_to_2xbf16(<2 x i16> %a) #0 {
+; CHECK-LABEL: test_bitcast_2xi16_to_2xbf16(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_bitcast_2xi16_to_2xbf16_param_0];
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
%r = bitcast <2 x i16> %a to <2 x bfloat>
ret <2 x bfloat> %r
}
@@ -351,184 +500,374 @@ declare <2 x bfloat> @llvm.nearbyint.f16(<2 x bfloat> %a) #0
declare <2 x bfloat> @llvm.round.f16(<2 x bfloat> %a) #0
declare <2 x bfloat> @llvm.fmuladd.f16(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0
-
-; CHECK-LABEL: test_sqrt(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_sqrt_param_0];
-; CHECK: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-DAG: cvt.f32.bf16 [[AF0:%f[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.f32.bf16 [[AF1:%f[0-9]+]], [[A1]];
-; CHECK-DAG: sqrt.rn.f32 [[RF0:%f[0-9]+]], [[AF0]];
-; CHECK-DAG: sqrt.rn.f32 [[RF1:%f[0-9]+]], [[AF1]];
-; CHECK-DAG: cvt.rn.bf16.f32 [[R0:%rs[0-9]+]], [[RF0]];
-; CHECK-DAG: cvt.rn.bf16.f32 [[R1:%rs[0-9]+]], [[RF1]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x bfloat> @test_sqrt(<2 x bfloat> %a) #0 {
+; CHECK-LABEL: test_sqrt(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-NEXT: .reg .f32 %f<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_sqrt_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.f32.bf16 %f1, %rs2;
+; CHECK-NEXT: sqrt.rn.f32 %f2, %f1;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs3, %f2;
+; CHECK-NEXT: cvt.f32.bf16 %f3, %rs1;
+; CHECK-NEXT: sqrt.rn.f32 %f4, %f3;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs4, %f4;
+; CHECK-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%r = call <2 x bfloat> @llvm.sqrt.f16(<2 x bfloat> %a)
ret <2 x bfloat> %r
}
-; CHECK-LABEL: test_fmuladd(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fmuladd_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fmuladd_param_1];
-; CHECK-DAG: ld.param.b32 [[C:%r[0-9]+]], [test_fmuladd_param_2];
-;
-; CHECK: fma.rn.bf16x2 [[RA:%r[0-9]+]], [[A]], [[B]], [[C]];
-; CHECK-NEXT: st.param.b32 [func_retval0], [[RA]];
-; CHECK: ret;
define <2 x bfloat> @test_fmuladd(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c) #0 {
+; CHECK-LABEL: test_fmuladd(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_fmuladd_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [test_fmuladd_param_1];
+; CHECK-NEXT: ld.param.b32 %r3, [test_fmuladd_param_0];
+; CHECK-NEXT: fma.rn.bf16x2 %r4, %r3, %r2, %r1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: ret;
%r = call <2 x bfloat> @llvm.fmuladd.f16(<2 x bfloat> %a, <2 x bfloat> %b, <2 x bfloat> %c)
ret <2 x bfloat> %r
}
-; CHECK-LABEL: test_fabs(
-; CHECK: ld.param.u32 [[A:%r[0-9]+]], [test_fabs_param_0];
-; CHECK: and.b32 [[R:%r[0-9]+]], [[A]], 2147450879;
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x bfloat> @test_fabs(<2 x bfloat> %a) #0 {
+; CHECK-LABEL: test_fabs(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.u32 %r1, [test_fabs_param_0];
+; CHECK-NEXT: and.b32 %r2, %r1, 2147450879;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%r = call <2 x bfloat> @llvm.fabs.f16(<2 x bfloat> %a)
ret <2 x bfloat> %r
}
-; CHECK-LABEL: test_fabs_add(
-; CHECK: abs.bf16x2
-; CHECK: ret;
define <2 x bfloat> @test_fabs_add(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
+; SM80-LABEL: test_fabs_add(
+; SM80: {
+; SM80-NEXT: .reg .b16 %rs<11>;
+; SM80-NEXT: .reg .b32 %r<6>;
+; SM80-NEXT: .reg .f32 %f<11>;
+; SM80-EMPTY:
+; SM80-NEXT: // %bb.0:
+; SM80-NEXT: ld.param.b32 %r1, [test_fabs_add_param_1];
+; SM80-NEXT: ld.param.b32 %r2, [test_fabs_add_param_0];
+; SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; SM80-NEXT: cvt.f32.bf16 %f1, %rs2;
+; SM80-NEXT: add.rn.f32 %f2, %f1, %f1;
+; SM80-NEXT: cvt.rn.bf16.f32 %rs3, %f2;
+; SM80-NEXT: cvt.f32.bf16 %f3, %rs1;
+; SM80-NEXT: add.rn.f32 %f4, %f3, %f3;
+; SM80-NEXT: cvt.rn.bf16.f32 %rs4, %f4;
+; SM80-NEXT: mov.b32 %r3, {%rs4, %rs3};
+; SM80-NEXT: abs.bf16x2 %r4, %r3;
+; SM80-NEXT: mov.b32 {%rs5, %rs6}, %r4;
+; SM80-NEXT: cvt.f32.bf16 %f5, %rs6;
+; SM80-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; SM80-NEXT: cvt.f32.bf16 %f6, %rs8;
+; SM80-NEXT: add.rn.f32 %f7, %f5, %f6;
+; SM80-NEXT: cvt.rn.bf16.f32 %rs9, %f7;
+; SM80-NEXT: cvt.f32.bf16 %f8, %rs5;
+; SM80-NEXT: cvt.f32.bf16 %f9, %rs7;
+; SM80-NEXT: add.rn.f32 %f10, %f8, %f9;
+; SM80-NEXT: cvt.rn.bf16.f32 %rs10, %f10;
+; SM80-NEXT: mov.b32 %r5, {%rs10, %rs9};
+; SM80-NEXT: st.param.b32 [func_retval0], %r5;
+; SM80-NEXT: ret;
+;
+; SM90-LABEL: test_fabs_add(
+; SM90: {
+; SM90-NEXT: .reg .b32 %r<6>;
+; SM90-EMPTY:
+; SM90-NEXT: // %bb.0:
+; SM90-NEXT: ld.param.b32 %r1, [test_fabs_add_param_1];
+; SM90-NEXT: ld.param.b32 %r2, [test_fabs_add_param_0];
+; SM90-NEXT: add.rn.bf16x2 %r3, %r2, %r2;
+; SM90-NEXT: abs.bf16x2 %r4, %r3;
+; SM90-NEXT: add.rn.bf16x2 %r5, %r4, %r1;
+; SM90-NEXT: st.param.b32 [func_retval0], %r5;
+; SM90-NEXT: ret;
%s = fadd <2 x bfloat> %a, %a
%r = call <2 x bfloat> @llvm.fabs.f16(<2 x bfloat> %s)
%d = fadd <2 x bfloat> %r, %b
ret <2 x bfloat> %d
}
-
-; CHECK-LABEL: test_minnum(
-; CHECK-DAG: ld.param.b32 [[AF0:%r[0-9]+]], [test_minnum_param_0];
-; CHECK-DAG: ld.param.b32 [[BF0:%r[0-9]+]], [test_minnum_param_1];
-; CHECK-DAG: min.bf16x2 [[RF0:%r[0-9]+]], [[AF0]], [[BF0]];
-; CHECK: st.param.b32 [func_retval0], [[RF0]];
-; CHECK: ret;
define <2 x bfloat> @test_minnum(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
+; CHECK-LABEL: test_minnum(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_minnum_param_1];
+; CHECK-NEXT: ld.param.b32 %r2, [test_minnum_param_0];
+; CHECK-NEXT: min.bf16x2 %r3, %r2, %r1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%r = call <2 x bfloat> @llvm.minnum.f16(<2 x bfloat> %a, <2 x bfloat> %b)
ret <2 x bfloat> %r
}
-; CHECK-LABEL: test_maxnum(
-; CHECK-DAG: ld.param.b32 [[AF0:%r[0-9]+]], [test_maxnum_param_0];
-; CHECK-DAG: ld.param.b32 [[BF0:%r[0-9]+]], [test_maxnum_param_1];
-; CHECK-DAG: max.bf16x2 [[RF0:%r[0-9]+]], [[AF0]], [[BF0]];
-; CHECK: st.param.b32 [func_retval0], [[RF0]];
-; CHECK: ret;
define <2 x bfloat> @test_maxnum(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
+; CHECK-LABEL: test_maxnum(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_maxnum_param_1];
+; CHECK-NEXT: ld.param.b32 %r2, [test_maxnum_param_0];
+; CHECK-NEXT: max.bf16x2 %r3, %r2, %r1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%r = call <2 x bfloat> @llvm.maxnum.f16(<2 x bfloat> %a, <2 x bfloat> %b)
ret <2 x bfloat> %r
}
-
-
-; CHECK-LABEL: test_floor(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_floor_param_0];
-; CHECK-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]];
-; SM90: cvt.rmi.bf16.bf16 [[R1:%rs[0-9]+]], [[A1]];
-; SM90: cvt.rmi.bf16.bf16 [[R0:%rs[0-9]+]], [[A0]];
-; SM80-DAG: cvt.f32.bf16 [[FA0:%f[0-9]+]], [[A0]];
-; SM80-DAG: cvt.f32.bf16 [[FA1:%f[0-9]+]], [[A1]];
-; SM80-DAG: cvt.rmi.f32.f32 [[RF0:%f[0-9]+]], [[FA0]];
-; SM80-DAG: cvt.rmi.f32.f32 [[RF1:%f[0-9]+]], [[FA1]];
-; SM80-DAG: cvt.rn.bf16.f32 [[R0:%rs[0-9]+]], [[RF0]];
-; SM80-DAG: cvt.rn.bf16.f32 [[R1:%rs[0-9]+]], [[RF1]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x bfloat> @test_floor(<2 x bfloat> %a) #0 {
+; SM80-LABEL: test_floor(
+; SM80: {
+; SM80-NEXT: .reg .b16 %rs<5>;
+; SM80-NEXT: .reg .b32 %r<3>;
+; SM80-NEXT: .reg .f32 %f<5>;
+; SM80-EMPTY:
+; SM80-NEXT: // %bb.0:
+; SM80-NEXT: ld.param.b32 %r1, [test_floor_param_0];
+; SM80-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; SM80-NEXT: cvt.f32.bf16 %f1, %rs2;
+; SM80-NEXT: cvt.rmi.f32.f32 %f2, %f1;
+; SM80-NEXT: cvt.rn.bf16.f32 %rs3, %f2;
+; SM80-NEXT: cvt.f32.bf16 %f3, %rs1;
+; SM80-NEXT: cvt.rmi.f32.f32 %f4, %f3;
+; SM80-NEXT: cvt.rn.bf16.f32 %rs4, %f4;
+; SM80-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; SM80-NEXT: st.param.b32 [func_retval0], %r2;
+; SM80-NEXT: ret;
+;
+; SM90-LABEL: test_floor(
+; SM90: {
+; SM90-NEXT: .reg .b16 %rs<5>;
+; SM90-NEXT: .reg .b32 %r<3>;
+; SM90-EMPTY:
+; SM90-NEXT: // %bb.0:
+; SM90-NEXT: ld.param.b32 %r1, [test_floor_param_0];
+; SM90-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; SM90-NEXT: cvt.rmi.bf16.bf16 %rs3, %rs2;
+; SM90-NEXT: cvt.rmi.bf16.bf16 %rs4, %rs1;
+; SM90-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: ret;
%r = call <2 x bfloat> @llvm.floor.f16(<2 x bfloat> %a)
ret <2 x bfloat> %r
}
-; CHECK-LABEL: test_ceil(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_ceil_param_0];
-; CHECK-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]];
-; SM90: cvt.rpi.bf16.bf16 [[R1:%rs[0-9]+]], [[A1]];
-; SM90: cvt.rpi.bf16.bf16 [[R0:%rs[0-9]+]], [[A0]];
-; SM80-DAG: cvt.f32.bf16 [[FA0:%f[0-9]+]], [[A0]];
-; SM80-DAG: cvt.f32.bf16 [[FA1:%f[0-9]+]], [[A1]];
-; SM80-DAG: cvt.rpi.f32.f32 [[RF0:%f[0-9]+]], [[FA0]];
-; SM80-DAG: cvt.rpi.f32.f32 [[RF1:%f[0-9]+]], [[FA1]];
-; SM80-DAG: cvt.rn.bf16.f32 [[R0:%rs[0-9]+]], [[RF0]];
-; SM80-DAG: cvt.rn.bf16.f32 [[R1:%rs[0-9]+]], [[RF1]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x bfloat> @test_ceil(<2 x bfloat> %a) #0 {
+; SM80-LABEL: test_ceil(
+; SM80: {
+; SM80-NEXT: .reg .b16 %rs<5>;
+; SM80-NEXT: .reg .b32 %r<3>;
+; SM80-NEXT: .reg .f32 %f<5>;
+; SM80-EMPTY:
+; SM80-NEXT: // %bb.0:
+; SM80-NEXT: ld.param.b32 %r1, [test_ceil_param_0];
+; SM80-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; SM80-NEXT: cvt.f32.bf16 %f1, %rs2;
+; SM80-NEXT: cvt.rpi.f32.f32 %f2, %f1;
+; SM80-NEXT: cvt.rn.bf16.f32 %rs3, %f2;
+; SM80-NEXT: cvt.f32.bf16 %f3, %rs1;
+; SM80-NEXT: cvt.rpi.f32.f32 %f4, %f3;
+; SM80-NEXT: cvt.rn.bf16.f32 %rs4, %f4;
+; SM80-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; SM80-NEXT: st.param.b32 [func_retval0], %r2;
+; SM80-NEXT: ret;
+;
+; SM90-LABEL: test_ceil(
+; SM90: {
+; SM90-NEXT: .reg .b16 %rs<5>;
+; SM90-NEXT: .reg .b32 %r<3>;
+; SM90-EMPTY:
+; SM90-NEXT: // %bb.0:
+; SM90-NEXT: ld.param.b32 %r1, [test_ceil_param_0];
+; SM90-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; SM90-NEXT: cvt.rpi.bf16.bf16 %rs3, %rs2;
+; SM90-NEXT: cvt.rpi.bf16.bf16 %rs4, %rs1;
+; SM90-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: ret;
%r = call <2 x bfloat> @llvm.ceil.f16(<2 x bfloat> %a)
ret <2 x bfloat> %r
}
-; CHECK-LABEL: test_trunc(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_trunc_param_0];
-; CHECK-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]];
-; SM90: cvt.rzi.bf16.bf16 [[R1:%rs[0-9]+]], [[A1]];
-; SM90: cvt.rzi.bf16.bf16 [[R0:%rs[0-9]+]], [[A0]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x bfloat> @test_trunc(<2 x bfloat> %a) #0 {
+; SM80-LABEL: test_trunc(
+; SM80: {
+; SM80-NEXT: .reg .b16 %rs<5>;
+; SM80-NEXT: .reg .b32 %r<3>;
+; SM80-NEXT: .reg .f32 %f<5>;
+; SM80-EMPTY:
+; SM80-NEXT: // %bb.0:
+; SM80-NEXT: ld.param.b32 %r1, [test_trunc_param_0];
+; SM80-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; SM80-NEXT: cvt.f32.bf16 %f1, %rs2;
+; SM80-NEXT: cvt.rzi.f32.f32 %f2, %f1;
+; SM80-NEXT: cvt.rn.bf16.f32 %rs3, %f2;
+; SM80-NEXT: cvt.f32.bf16 %f3, %rs1;
+; SM80-NEXT: cvt.rzi.f32.f32 %f4, %f3;
+; SM80-NEXT: cvt.rn.bf16.f32 %rs4, %f4;
+; SM80-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; SM80-NEXT: st.param.b32 [func_retval0], %r2;
+; SM80-NEXT: ret;
+;
+; SM90-LABEL: test_trunc(
+; SM90: {
+; SM90-NEXT: .reg .b16 %rs<5>;
+; SM90-NEXT: .reg .b32 %r<3>;
+; SM90-EMPTY:
+; SM90-NEXT: // %bb.0:
+; SM90-NEXT: ld.param.b32 %r1, [test_trunc_param_0];
+; SM90-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; SM90-NEXT: cvt.rzi.bf16.bf16 %rs3, %rs2;
+; SM90-NEXT: cvt.rzi.bf16.bf16 %rs4, %rs1;
+; SM90-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: ret;
%r = call <2 x bfloat> @llvm.trunc.f16(<2 x bfloat> %a)
ret <2 x bfloat> %r
}
-; CHECK-LABEL: test_rint(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_rint_param_0];
-; CHECK-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]];
-; SM90: cvt.rni.bf16.bf16 [[R1:%rs[0-9]+]], [[A1]];
-; SM90: cvt.rni.bf16.bf16 [[R0:%rs[0-9]+]], [[A0]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x bfloat> @test_rint(<2 x bfloat> %a) #0 {
+; SM80-LABEL: test_rint(
+; SM80: {
+; SM80-NEXT: .reg .b16 %rs<5>;
+; SM80-NEXT: .reg .b32 %r<3>;
+; SM80-NEXT: .reg .f32 %f<5>;
+; SM80-EMPTY:
+; SM80-NEXT: // %bb.0:
+; SM80-NEXT: ld.param.b32 %r1, [test_rint_param_0];
+; SM80-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; SM80-NEXT: cvt.f32.bf16 %f1, %rs2;
+; SM80-NEXT: cvt.rni.f32.f32 %f2, %f1;
+; SM80-NEXT: cvt.rn.bf16.f32 %rs3, %f2;
+; SM80-NEXT: cvt.f32.bf16 %f3, %rs1;
+; SM80-NEXT: cvt.rni.f32.f32 %f4, %f3;
+; SM80-NEXT: cvt.rn.bf16.f32 %rs4, %f4;
+; SM80-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; SM80-NEXT: st.param.b32 [func_retval0], %r2;
+; SM80-NEXT: ret;
+;
+; SM90-LABEL: test_rint(
+; SM90: {
+; SM90-NEXT: .reg .b16 %rs<5>;
+; SM90-NEXT: .reg .b32 %r<3>;
+; SM90-EMPTY:
+; SM90-NEXT: // %bb.0:
+; SM90-NEXT: ld.param.b32 %r1, [test_rint_param_0];
+; SM90-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; SM90-NEXT: cvt.rni.bf16.bf16 %rs3, %rs2;
+; SM90-NEXT: cvt.rni.bf16.bf16 %rs4, %rs1;
+; SM90-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; SM90-NEXT: st.param.b32 [func_retval0], %r2;
+; SM90-NEXT: ret;
%r = call <2 x bfloat> @llvm.rint.f16(<2 x bfloat> %a)
ret <2 x bfloat> %r
}
-; CHECK-LABEL: test_round(
-; CHECK: ld.param.b32 {{.*}}, [test_round_param_0];
-; check the use of sign mask and 0.5 to implement round
-; CHECK: and.b32 [[R1:%r[0-9]+]], {{.*}}, -2147483648;
-; CHECK: or.b32 {{.*}}, [[R1]], 1056964608;
-; CHECK: and.b32 [[R2:%r[0-9]+]], {{.*}}, -2147483648;
-; CHECK: or.b32 {{.*}}, [[R2]], 1056964608;
-; CHECK: st.param.b32 [func_retval0], {{.*}};
-; CHECK: ret;
define <2 x bfloat> @test_round(<2 x bfloat> %a) #0 {
+; CHECK-LABEL: test_round(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<5>;
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-NEXT: .reg .b32 %r<9>;
+; CHECK-NEXT: .reg .f32 %f<17>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_round_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.f32.bf16 %f1, %rs2;
+; CHECK-NEXT: mov.b32 %r2, %f1;
+; CHECK-NEXT: and.b32 %r3, %r2, -2147483648;
+; CHECK-NEXT: or.b32 %r4, %r3, 1056964608;
+; CHECK-NEXT: mov.b32 %f2, %r4;
+; CHECK-NEXT: add.rn.f32 %f3, %f1, %f2;
+; CHECK-NEXT: cvt.rzi.f32.f32 %f4, %f3;
+; CHECK-NEXT: abs.f32 %f5, %f1;
+; CHECK-NEXT: setp.gt.f32 %p1, %f5, 0f4B000000;
+; CHECK-NEXT: selp.f32 %f6, %f1, %f4, %p1;
+; CHECK-NEXT: cvt.rzi.f32.f32 %f7, %f1;
+; CHECK-NEXT: setp.lt.f32 %p2, %f5, 0f3F000000;
+; CHECK-NEXT: selp.f32 %f8, %f7, %f6, %p2;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs3, %f8;
+; CHECK-NEXT: cvt.f32.bf16 %f9, %rs1;
+; CHECK-NEXT: mov.b32 %r5, %f9;
+; CHECK-NEXT: and.b32 %r6, %r5, -2147483648;
+; CHECK-NEXT: or.b32 %r7, %r6, 1056964608;
+; CHECK-NEXT: mov.b32 %f10, %r7;
+; CHECK-NEXT: add.rn.f32 %f11, %f9, %f10;
+; CHECK-NEXT: cvt.rzi.f32.f32 %f12, %f11;
+; CHECK-NEXT: abs.f32 %f13, %f9;
+; CHECK-NEXT: setp.gt.f32 %p3, %f13, 0f4B000000;
+; CHECK-NEXT: selp.f32 %f14, %f9, %f12, %p3;
+; CHECK-NEXT: cvt.rzi.f32.f32 %f15, %f9;
+; CHECK-NEXT: setp.lt.f32 %p4, %f13, 0f3F000000;
+; CHECK-NEXT: selp.f32 %f16, %f15, %f14, %p4;
+; CHECK-NEXT: cvt.rn.bf16.f32 %rs4, %f16;
+; CHECK-NEXT: mov.b32 %r8, {%rs4, %rs3};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r8;
+; CHECK-NEXT: ret;
%r = call <2 x bfloat> @llvm.round.f16(<2 x bfloat> %a)
ret <2 x bfloat> %r
}
-; CHECK-LABEL: test_copysign(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_copysign_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_copysign_param_1];
-; SM80-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; SM80-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; SM80-DAG: abs.bf16 [[AW1:%rs[0-9]+]], [[A1]];
-; SM80-DAG: neg.bf16 [[AY1:%rs[0-9]+]], [[AW1]];
-; SM80-DAG: shr.u16 [[BS1:%rs[0-9]+]], [[B1]], 15;
-; SM80-DAG: and.b16 [[BR1:%rs[0-9]+]], [[BS1]], 1;
-; SM80-DAG: setp.eq.b16 [[P1:%p[0-9]+]], [[BR1]], 1;
-; SM80-DAG: selp.b16 [[RS1:%rs[0-9]+]], [[AY1]], [[AW1]], [[P1]]
-; SM80-DAG: abs.bf16 [[AW0:%rs[0-9]+]], [[A0]];
-; SM80-DAG: neg.bf16 [[AY0:%rs[0-9]+]], [[AW0]];
-; SM80-DAG: shr.u16 [[BS0:%rs[0-9]+]], [[B0]], 15;
-; SM80-DAG: and.b16 [[BR0:%rs[0-9]+]], [[BS0]], 1;
-; SM80-DAG: setp.eq.b16 [[P0:%p[0-9]+]], [[BR0]], 1;
-; SM80-DAG: selp.b16 [[RS0:%rs[0-9]+]], [[AY0]], [[AW0]], [[P0]]
-; SM80-DAG: mov.b32 [[R:%r[0-9]+]], {[[RS0]], [[RS1]]}
-; SM90-DAG: and.b32 [[R1:%r[0-9]+]], [[B]], -2147450880;
-; SM90-DAG: and.b32 [[R2:%r[0-9]+]], [[A]], 2147450879;
-; SM90-DAG: or.b32 [[R:%r[0-9]+]], [[R2]], [[R1]];
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x bfloat> @test_copysign(<2 x bfloat> %a, <2 x bfloat> %b) #0 {
+; SM80-LABEL: test_copysign(
+; SM80: {
+; SM80-NEXT: .reg .pred %p<3>;
+; SM80-NEXT: .reg .b16 %rs<17>;
+; SM80-NEXT: .reg .b32 %r<4>;
+; SM80-EMPTY:
+; SM80-NEXT: // %bb.0:
+; SM80-NEXT: ld.param.b32 %r1, [test_copysign_param_1];
+; SM80-NEXT: ld.param.b32 %r2, [test_copysign_param_0];
+; SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; SM80-NEXT: abs.bf16 %rs3, %rs2;
+; SM80-NEXT: neg.bf16 %rs4, %rs3;
+; SM80-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; SM80-NEXT: shr.u16 %rs8, %rs6, 15;
+; SM80-NEXT: and.b16 %rs9, %rs8, 1;
+; SM80-NEXT: setp.eq.b16 %p1, %rs9, 1;
+; SM80-NEXT: selp.b16 %rs10, %rs4, %rs3, %p1;
+; SM80-NEXT: abs.bf16 %rs11, %rs1;
+; SM80-NEXT: neg.bf16 %rs12, %rs11;
+; SM80-NEXT: shr.u16 %rs14, %rs5, 15;
+; SM80-NEXT: and.b16 %rs15, %rs14, 1;
+; SM80-NEXT: setp.eq.b16 %p2, %rs15, 1;
+; SM80-NEXT: selp.b16 %rs16, %rs12, %rs11, %p2;
+; SM80-NEXT: mov.b32 %r3, {%rs16, %rs10};
+; SM80-NEXT: st.param.b32 [func_retval0], %r3;
+; SM80-NEXT: ret;
+;
+; SM90-LABEL: test_copysign(
+; SM90: {
+; SM90-NEXT: .reg .b32 %r<9>;
+; SM90-EMPTY:
+; SM90-NEXT: // %bb.0:
+; SM90-NEXT: ld.param.b32 %r1, [test_copysign_param_0];
+; SM90-NEXT: ld.param.b32 %r2, [test_copysign_param_1];
+; SM90-NEXT: and.b32 %r4, %r2, -2147450880;
+; SM90-NEXT: and.b32 %r6, %r1, 2147450879;
+; SM90-NEXT: or.b32 %r7, %r6, %r4;
+; SM90-NEXT: st.param.b32 [func_retval0], %r7;
+; SM90-NEXT: ret;
%r = call <2 x bfloat> @llvm.copysign.f16(<2 x bfloat> %a, <2 x bfloat> %b)
ret <2 x bfloat> %r
}
diff --git a/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll b/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
index b11c69e064c4a6..eb0b00e883846d 100644
--- a/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
@@ -1,325 +1,459 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; ## Full FP16 support enabled by default.
-; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 -asm-verbose=false \
+; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 \
; RUN: -O0 -disable-post-ra -frame-pointer=all -verify-machineinstrs \
; RUN: | FileCheck -allow-deprecated-dag-overlap -check-prefixes CHECK,CHECK-F16 %s
; RUN: %if ptxas %{ \
-; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 -asm-verbose=false \
+; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 \
; RUN: -O0 -disable-post-ra -frame-pointer=all -verify-machineinstrs \
; RUN: | %ptxas-verify -arch=sm_53 \
; RUN: %}
; ## FP16 support explicitly disabled.
-; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 -asm-verbose=false \
+; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 \
; RUN: -O0 -disable-post-ra -frame-pointer=all --nvptx-no-f16-math \
; RUN: -verify-machineinstrs \
; RUN: | FileCheck -allow-deprecated-dag-overlap -check-prefixes CHECK,CHECK-NOF16 %s
; RUN: %if ptxas %{ \
-; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 -asm-verbose=false \
+; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 \
; RUN: -O0 -disable-post-ra -frame-pointer=all --nvptx-no-f16-math \
; RUN: -verify-machineinstrs \
; RUN: | %ptxas-verify -arch=sm_53 \
; RUN: %}
; ## FP16 is not supported by hardware.
-; RUN: llc < %s -O0 -mtriple=nvptx64-nvidia-cuda -mcpu=sm_52 -asm-verbose=false \
+; RUN: llc < %s -O0 -mtriple=nvptx64-nvidia-cuda -mcpu=sm_52 \
; RUN: -disable-post-ra -frame-pointer=all -verify-machineinstrs \
; RUN: | FileCheck -allow-deprecated-dag-overlap -check-prefixes CHECK,CHECK-NOF16 %s
; RUN: %if ptxas %{ \
-; RUN: llc < %s -O0 -mtriple=nvptx64-nvidia-cuda -mcpu=sm_52 -asm-verbose=false \
+; RUN: llc < %s -O0 -mtriple=nvptx64-nvidia-cuda -mcpu=sm_52 \
; RUN: -disable-post-ra -frame-pointer=all -verify-machineinstrs \
; RUN: | %ptxas-verify -arch=sm_52 \
; RUN: %}
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
-; CHECK-LABEL: test_ret_const(
-; CHECK: mov.b32 [[R:%r[0-9+]]], 1073757184;
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK-NEXT: ret;
define <2 x half> @test_ret_const() #0 {
+; CHECK-LABEL: test_ret_const(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: mov.b32 %r1, 1073757184;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
ret <2 x half> <half 1.0, half 2.0>
}
-; CHECK-LABEL: test_extract_0(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_extract_0_param_0];
-; CHECK: mov.b32 {[[R:%rs[0-9]+]], tmp}, [[A]];
-; CHECK: st.param.b16 [func_retval0], [[R]];
-; CHECK: ret;
define half @test_extract_0(<2 x half> %a) #0 {
+; CHECK-LABEL: test_extract_0(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_extract_0_param_0];
+; CHECK-NEXT: { .reg .b16 tmp; mov.b32 {%rs1, tmp}, %r1; }
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs1;
+; CHECK-NEXT: ret;
%e = extractelement <2 x half> %a, i32 0
ret half %e
}
-; CHECK-LABEL: test_extract_1(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_extract_1_param_0];
-; CHECK: mov.b32 {tmp, [[R:%rs[0-9]+]]}, [[A]];
-; CHECK: st.param.b16 [func_retval0], [[R]];
-; CHECK: ret;
define half @test_extract_1(<2 x half> %a) #0 {
+; CHECK-LABEL: test_extract_1(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<2>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_extract_1_param_0];
+; CHECK-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r1; }
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs1;
+; CHECK-NEXT: ret;
%e = extractelement <2 x half> %a, i32 1
ret half %e
}
-; CHECK-LABEL: test_extract_i(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_extract_i_param_0];
-; CHECK-DAG: ld.param.u64 [[IDX:%rd[0-9]+]], [test_extract_i_param_1];
-; CHECK-DAG: setp.eq.s64 [[PRED:%p[0-9]+]], [[IDX]], 0;
-; CHECK-DAG: mov.b32 {[[E0:%rs[0-9]+]], [[E1:%rs[0-9]+]]}, [[A]];
-; CHECK: selp.b16 [[R:%rs[0-9]+]], [[E0]], [[E1]], [[PRED]];
-; CHECK: st.param.b16 [func_retval0], [[R]];
-; CHECK: ret;
define half @test_extract_i(<2 x half> %a, i64 %idx) #0 {
+; CHECK-LABEL: test_extract_i(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<4>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.u64 %rd1, [test_extract_i_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_extract_i_param_0];
+; CHECK-NEXT: setp.eq.s64 %p1, %rd1, 0;
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: selp.b16 %rs3, %rs1, %rs2, %p1;
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs3;
+; CHECK-NEXT: ret;
%e = extractelement <2 x half> %a, i64 %idx
ret half %e
}
-; CHECK-LABEL: test_fadd(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fadd_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fadd_param_1];
-;
-; CHECK-F16-NEXT: add.rn.f16x2 [[R:%r[0-9]+]], [[A]], [[B]];
-;
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]]
-; CHECK-NOF16-DAG: add.rn.f32 [[FR0:%f[0-9]+]], [[FA0]], [[FB0]];
-; CHECK-NOF16-DAG: add.rn.f32 [[FR1:%f[0-9]+]], [[FA1]], [[FB1]];
-; CHECK-NOF16-DAG: cvt.rn.f16.f32 [[R0:%rs[0-9]+]], [[FR0]]
-; CHECK-NOF16-DAG: cvt.rn.f16.f32 [[R1:%rs[0-9]+]], [[FR1]]
-; CHECK-NOF16: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-;
-; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];
-; CHECK-NEXT: ret;
define <2 x half> @test_fadd(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-F16-LABEL: test_fadd(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .b32 %r<4>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fadd_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fadd_param_0];
+; CHECK-F16-NEXT: add.rn.f16x2 %r3, %r1, %r2;
+; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fadd(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<4>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<7>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fadd_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fadd_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NOF16-NEXT: add.rn.f32 %f3, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs5, %f3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f4, %rs1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f5, %rs3;
+; CHECK-NOF16-NEXT: add.rn.f32 %f6, %f5, %f4;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs6, %f6;
+; CHECK-NOF16-NEXT: mov.b32 %r3, {%rs6, %rs5};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NOF16-NEXT: ret;
%r = fadd <2 x half> %a, %b
ret <2 x half> %r
}
; Check that we can lower fadd with immediate arguments.
-; CHECK-LABEL: test_fadd_imm_0(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fadd_imm_0_param_0];
-;
-; CHECK-F16: mov.b32 [[I:%r[0-9+]]], 1073757184;
-; CHECK-F16: add.rn.f16x2 [[R:%r[0-9]+]], [[A]], [[I]];
-;
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]]
-; CHECK-NOF16-DAG: add.rn.f32 [[FR0:%f[0-9]+]], [[FA0]], 0f3F800000;
-; CHECK-NOF16-DAG: add.rn.f32 [[FR1:%f[0-9]+]], [[FA1]], 0f40000000;
-; CHECK-NOF16-DAG: cvt.rn.f16.f32 [[R0:%rs[0-9]+]], [[FR0]]
-; CHECK-NOF16-DAG: cvt.rn.f16.f32 [[R1:%rs[0-9]+]], [[FR1]]
-; CHECK-NOF16: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-;
-; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];
-; CHECK-NEXT: ret;
define <2 x half> @test_fadd_imm_0(<2 x half> %a) #0 {
+; CHECK-F16-LABEL: test_fadd_imm_0(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .b32 %r<4>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fadd_imm_0_param_0];
+; CHECK-F16-NEXT: mov.b32 %r2, 1073757184;
+; CHECK-F16-NEXT: add.rn.f16x2 %r3, %r1, %r2;
+; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fadd_imm_0(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .b16 %rs<5>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<5>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fadd_imm_0_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: add.rn.f32 %f2, %f1, 0f40000000;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs3, %f2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-NOF16-NEXT: add.rn.f32 %f4, %f3, 0f3F800000;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs4, %f4;
+; CHECK-NOF16-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NOF16-NEXT: ret;
%r = fadd <2 x half> <half 1.0, half 2.0>, %a
ret <2 x half> %r
}
-; CHECK-LABEL: test_fadd_imm_1(
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fadd_imm_1_param_0];
-;
-; CHECK-F16: mov.b32 [[I:%r[0-9+]]], 1073757184;
-; CHECK-F16: add.rn.f16x2 [[R:%r[0-9]+]], [[B]], [[I]];
-;
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]]
-; CHECK-NOF16-DAG: add.rn.f32 [[FR0:%f[0-9]+]], [[FA0]], 0f3F800000;
-; CHECK-NOF16-DAG: add.rn.f32 [[FR1:%f[0-9]+]], [[FA1]], 0f40000000;
-; CHECK-NOF16-DAG: cvt.rn.f16.f32 [[R0:%rs[0-9]+]], [[FR0]]
-; CHECK-NOF16-DAG: cvt.rn.f16.f32 [[R1:%rs[0-9]+]], [[FR1]]
-; CHECK-NOF16: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-;
-; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];
-; CHECK-NEXT: ret;
define <2 x half> @test_fadd_imm_1(<2 x half> %a) #0 {
+; CHECK-F16-LABEL: test_fadd_imm_1(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .b32 %r<4>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fadd_imm_1_param_0];
+; CHECK-F16-NEXT: mov.b32 %r2, 1073757184;
+; CHECK-F16-NEXT: add.rn.f16x2 %r3, %r1, %r2;
+; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fadd_imm_1(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .b16 %rs<5>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<5>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fadd_imm_1_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: add.rn.f32 %f2, %f1, 0f40000000;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs3, %f2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-NOF16-NEXT: add.rn.f32 %f4, %f3, 0f3F800000;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs4, %f4;
+; CHECK-NOF16-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NOF16-NEXT: ret;
%r = fadd <2 x half> %a, <half 1.0, half 2.0>
ret <2 x half> %r
}
-; CHECK-LABEL: test_fsub(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fsub_param_0];
-;
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fsub_param_1];
-; CHECK-F16-NEXT: sub.rn.f16x2 [[R:%r[0-9]+]], [[A]], [[B]];
-;
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]]
-; CHECK-NOF16-DAG: sub.rn.f32 [[FR0:%f[0-9]+]], [[FA0]], [[FB0]];
-; CHECK-NOF16-DAG: sub.rn.f32 [[FR1:%f[0-9]+]], [[FA1]], [[FB1]];
-; CHECK-NOF16-DAG: cvt.rn.f16.f32 [[R0:%rs[0-9]+]], [[FR0]]
-; CHECK-NOF16-DAG: cvt.rn.f16.f32 [[R1:%rs[0-9]+]], [[FR1]]
-; CHECK-NOF16: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-;
-; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];
-; CHECK-NEXT: ret;
define <2 x half> @test_fsub(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-F16-LABEL: test_fsub(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .b32 %r<4>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fsub_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fsub_param_0];
+; CHECK-F16-NEXT: sub.rn.f16x2 %r3, %r1, %r2;
+; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fsub(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<4>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<7>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fsub_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fsub_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NOF16-NEXT: sub.rn.f32 %f3, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs5, %f3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f4, %rs1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f5, %rs3;
+; CHECK-NOF16-NEXT: sub.rn.f32 %f6, %f5, %f4;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs6, %f6;
+; CHECK-NOF16-NEXT: mov.b32 %r3, {%rs6, %rs5};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NOF16-NEXT: ret;
%r = fsub <2 x half> %a, %b
ret <2 x half> %r
}
-; CHECK-LABEL: test_fneg(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fneg_param_0];
-;
-; CHECK-F16: mov.b32 [[I:%r[0-9+]]], 0;
-; CHECK-F16-NEXT: sub.rn.f16x2 [[R:%r[0-9]+]], [[I]], [[A]];
-;
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]]
-; CHECK-NOF16-DAG: mov.f32 [[Z:%f[0-9]+]], 0f00000000;
-; CHECK-NOF16-DAG: sub.rn.f32 [[FR0:%f[0-9]+]], [[Z]], [[FA0]];
-; CHECK-NOF16-DAG: sub.rn.f32 [[FR1:%f[0-9]+]], [[Z]], [[FA1]];
-; CHECK-NOF16-DAG: cvt.rn.f16.f32 [[R0:%rs[0-9]+]], [[FR0]]
-; CHECK-NOF16-DAG: cvt.rn.f16.f32 [[R1:%rs[0-9]+]], [[FR1]]
-; CHECK-NOF16: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-;
-; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];
-; CHECK-NEXT: ret;
define <2 x half> @test_fneg(<2 x half> %a) #0 {
+; CHECK-F16-LABEL: test_fneg(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .b32 %r<4>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fneg_param_0];
+; CHECK-F16-NEXT: mov.b32 %r2, 0;
+; CHECK-F16-NEXT: sub.rn.f16x2 %r3, %r2, %r1;
+; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fneg(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .b16 %rs<5>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<6>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fneg_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: mov.f32 %f2, 0f00000000;
+; CHECK-NOF16-NEXT: sub.rn.f32 %f3, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs3, %f3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f4, %rs1;
+; CHECK-NOF16-NEXT: sub.rn.f32 %f5, %f2, %f4;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs4, %f5;
+; CHECK-NOF16-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NOF16-NEXT: ret;
%r = fsub <2 x half> <half 0.0, half 0.0>, %a
ret <2 x half> %r
}
-; CHECK-LABEL: test_fmul(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fmul_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fmul_param_1];
-; CHECK-F16-NEXT: mul.rn.f16x2 [[R:%r[0-9]+]], [[A]], [[B]];
-;
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]]
-; CHECK-NOF16-DAG: mul.rn.f32 [[FR0:%f[0-9]+]], [[FA0]], [[FB0]];
-; CHECK-NOF16-DAG: mul.rn.f32 [[FR1:%f[0-9]+]], [[FA1]], [[FB1]];
-; CHECK-NOF16-DAG: cvt.rn.f16.f32 [[R0:%rs[0-9]+]], [[FR0]]
-; CHECK-NOF16-DAG: cvt.rn.f16.f32 [[R1:%rs[0-9]+]], [[FR1]]
-; CHECK-NOF16: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-;
-; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];
-; CHECK-NEXT: ret;
define <2 x half> @test_fmul(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-F16-LABEL: test_fmul(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .b32 %r<4>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fmul_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fmul_param_0];
+; CHECK-F16-NEXT: mul.rn.f16x2 %r3, %r1, %r2;
+; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fmul(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<4>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<7>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fmul_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fmul_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NOF16-NEXT: mul.rn.f32 %f3, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs5, %f3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f4, %rs1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f5, %rs3;
+; CHECK-NOF16-NEXT: mul.rn.f32 %f6, %f5, %f4;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs6, %f6;
+; CHECK-NOF16-NEXT: mov.b32 %r3, {%rs6, %rs5};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NOF16-NEXT: ret;
%r = fmul <2 x half> %a, %b
ret <2 x half> %r
}
-; CHECK-LABEL: test_fdiv(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fdiv_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fdiv_param_1];
-; CHECK-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]];
-; CHECK-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]];
-; CHECK-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]];
-; CHECK-DAG: div.rn.f32 [[FR0:%f[0-9]+]], [[FA0]], [[FB0]];
-; CHECK-DAG: div.rn.f32 [[FR1:%f[0-9]+]], [[FA1]], [[FB1]];
-; CHECK-DAG: cvt.rn.f16.f32 [[R0:%rs[0-9]+]], [[FR0]];
-; CHECK-DAG: cvt.rn.f16.f32 [[R1:%rs[0-9]+]], [[FR1]];
-; CHECK-NEXT: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];
-; CHECK-NEXT: ret;
define <2 x half> @test_fdiv(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-LABEL: test_fdiv(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<7>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-NEXT: .reg .f32 %f<7>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r2, [test_fdiv_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_fdiv_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NEXT: div.rn.f32 %f3, %f2, %f1;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs5, %f3;
+; CHECK-NEXT: cvt.f32.f16 %f4, %rs1;
+; CHECK-NEXT: cvt.f32.f16 %f5, %rs3;
+; CHECK-NEXT: div.rn.f32 %f6, %f5, %f4;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs6, %f6;
+; CHECK-NEXT: mov.b32 %r3, {%rs6, %rs5};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%r = fdiv <2 x half> %a, %b
ret <2 x half> %r
}
-; CHECK-LABEL: test_frem(
; -- Load two 16x2 inputs and split them into f16 elements
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_frem_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_frem_param_1];
; -- Split into elements
-; CHECK-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
; -- promote to f32.
-; CHECK-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]];
-; CHECK-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]];
-; CHECK-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]];
; -- frem(a[0],b[0]).
-; CHECK-DAG: div.rn.f32 [[FD0:%f[0-9]+]], [[FA0]], [[FB0]];
-; CHECK-DAG: cvt.rzi.f32.f32 [[DI0:%f[0-9]+]], [[FD0]];
-; CHECK-DAG: mul.f32 [[RI0:%f[0-9]+]], [[DI0]], [[FB0]];
-; CHECK-DAG: sub.f32 [[RFNINF0:%f[0-9]+]], [[FA0]], [[RI0]];
-; CHECK-DAG: testp.infinite.f32 [[ISB0INF:%p[0-9]+]], [[FB0]];
-; CHECK-DAG: selp.f32 [[RF0:%f[0-9]+]], [[FA0]], [[RFNINF0]], [[ISB0INF]];
; -- frem(a[1],b[1]).
-; CHECK-DAG: div.rn.f32 [[FD1:%f[0-9]+]], [[FA1]], [[FB1]];
-; CHECK-DAG: cvt.rzi.f32.f32 [[DI1:%f[0-9]+]], [[FD1]];
-; CHECK-DAG: mul.f32 [[RI1:%f[0-9]+]], [[DI1]], [[FB1]];
-; CHECK-DAG: sub.f32 [[RFNINF1:%f[0-9]+]], [[FA1]], [[RI1]];
-; CHECK-DAG: testp.infinite.f32 [[ISB1INF:%p[0-9]+]], [[FB1]];
-; CHECK-DAG: selp.f32 [[RF1:%f[0-9]+]], [[FA1]], [[RFNINF1]], [[ISB1INF]];
; -- convert back to f16.
-; CHECK-DAG: cvt.rn.f16.f32 [[R0:%rs[0-9]+]], [[RF0]];
-; CHECK-DAG: cvt.rn.f16.f32 [[R1:%rs[0-9]+]], [[RF1]];
; -- merge into f16x2 and return it.
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];
-; CHECK-NEXT: ret;
define <2 x half> @test_frem(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-LABEL: test_frem(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<7>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-NEXT: .reg .f32 %f<15>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r2, [test_frem_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_frem_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NEXT: div.rn.f32 %f3, %f2, %f1;
+; CHECK-NEXT: cvt.rzi.f32.f32 %f4, %f3;
+; CHECK-NEXT: mul.f32 %f5, %f4, %f1;
+; CHECK-NEXT: sub.f32 %f6, %f2, %f5;
+; CHECK-NEXT: testp.infinite.f32 %p1, %f1;
+; CHECK-NEXT: selp.f32 %f7, %f2, %f6, %p1;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs5, %f7;
+; CHECK-NEXT: cvt.f32.f16 %f8, %rs1;
+; CHECK-NEXT: cvt.f32.f16 %f9, %rs3;
+; CHECK-NEXT: div.rn.f32 %f10, %f9, %f8;
+; CHECK-NEXT: cvt.rzi.f32.f32 %f11, %f10;
+; CHECK-NEXT: mul.f32 %f12, %f11, %f8;
+; CHECK-NEXT: sub.f32 %f13, %f9, %f12;
+; CHECK-NEXT: testp.infinite.f32 %p2, %f8;
+; CHECK-NEXT: selp.f32 %f14, %f9, %f13, %p2;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs6, %f14;
+; CHECK-NEXT: mov.b32 %r3, {%rs6, %rs5};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%r = frem <2 x half> %a, %b
ret <2 x half> %r
}
-; CHECK-LABEL: .func test_ldst_v2f16(
-; CHECK-DAG: ld.param.u64 %[[A:rd[0-9]+]], [test_ldst_v2f16_param_0];
-; CHECK-DAG: ld.param.u64 %[[B:rd[0-9]+]], [test_ldst_v2f16_param_1];
-; CHECK-DAG: ld.b32 [[E:%r[0-9]+]], [%[[A]]]
-; CHECK-DAG: st.b32 [%[[B]]], [[E]];
-; CHECK: ret;
define void @test_ldst_v2f16(ptr %a, ptr %b) {
+; CHECK-LABEL: test_ldst_v2f16(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.u64 %rd2, [test_ldst_v2f16_param_1];
+; CHECK-NEXT: ld.param.u64 %rd1, [test_ldst_v2f16_param_0];
+; CHECK-NEXT: ld.b32 %r1, [%rd1];
+; CHECK-NEXT: st.b32 [%rd2], %r1;
+; CHECK-NEXT: ret;
%t1 = load <2 x half>, ptr %a
store <2 x half> %t1, ptr %b, align 16
ret void
}
-; CHECK-LABEL: .func test_ldst_v3f16(
-; CHECK-DAG: ld.param.u64 %[[A:rd[0-9]+]], [test_ldst_v3f16_param_0];
-; CHECK-DAG: ld.param.u64 %[[B:rd[0-9]+]], [test_ldst_v3f16_param_1];
; -- v3 is inconvenient to capture as it's lowered as ld.b64 + fair
; number of bitshifting instructions that may change at llvm's whim.
; So we only verify that we only issue correct number of writes using
; correct offset, but not the values we write.
-; CHECK-DAG: ld.u64
-; CHECK-DAG: st.u32 [%[[B]]],
-; CHECK-DAG: st.b16 [%[[B]]+4],
-; CHECK: ret;
define void @test_ldst_v3f16(ptr %a, ptr %b) {
+; CHECK-LABEL: test_ldst_v3f16(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<2>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-NEXT: .reg .b64 %rd<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.u64 %rd2, [test_ldst_v3f16_param_1];
+; CHECK-NEXT: ld.param.u64 %rd1, [test_ldst_v3f16_param_0];
+; CHECK-NEXT: ld.u64 %rd3, [%rd1];
+; CHECK-NEXT: { .reg .b32 tmp; mov.b64 {tmp, %r1}, %rd3; }
+; CHECK-NEXT: st.u32 [%rd2], %rd3;
+; CHECK-NEXT: { .reg .b16 tmp; mov.b32 {%rs1, tmp}, %r1; }
+; CHECK-NEXT: st.b16 [%rd2+4], %rs1;
+; CHECK-NEXT: ret;
%t1 = load <3 x half>, ptr %a
store <3 x half> %t1, ptr %b, align 16
ret void
}
-; CHECK-LABEL: .func test_ldst_v4f16(
-; CHECK-DAG: ld.param.u64 %[[A:rd[0-9]+]], [test_ldst_v4f16_param_0];
-; CHECK-DAG: ld.param.u64 %[[B:rd[0-9]+]], [test_ldst_v4f16_param_1];
-; CHECK-DAG: ld.v4.b16 {[[E0:%rs[0-9]+]], [[E1:%rs[0-9]+]], [[E2:%rs[0-9]+]], [[E3:%rs[0-9]+]]}, [%[[A]]];
-; CHECK-DAG: st.v4.b16 [%[[B]]], {[[E0]], [[E1]], [[E2]], [[E3]]};
-; CHECK: ret;
define void @test_ldst_v4f16(ptr %a, ptr %b) {
+; CHECK-LABEL: test_ldst_v4f16(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.u64 %rd2, [test_ldst_v4f16_param_1];
+; CHECK-NEXT: ld.param.u64 %rd1, [test_ldst_v4f16_param_0];
+; CHECK-NEXT: ld.v4.b16 {%rs1, %rs2, %rs3, %rs4}, [%rd1];
+; CHECK-NEXT: st.v4.b16 [%rd2], {%rs1, %rs2, %rs3, %rs4};
+; CHECK-NEXT: ret;
%t1 = load <4 x half>, ptr %a
store <4 x half> %t1, ptr %b, align 16
ret void
}
-; CHECK-LABEL: .func test_ldst_v8f16(
-; CHECK-DAG: ld.param.u64 %[[A:rd[0-9]+]], [test_ldst_v8f16_param_0];
-; CHECK-DAG: ld.param.u64 %[[B:rd[0-9]+]], [test_ldst_v8f16_param_1];
-; CHECK-DAG: ld.v4.b32 {[[E0:%r[0-9]+]], [[E1:%r[0-9]+]], [[E2:%r[0-9]+]], [[E3:%r[0-9]+]]}, [%[[A]]];
-; CHECK-DAG: st.v4.b32 [%[[B]]], {[[E0]], [[E1]], [[E2]], [[E3]]};
-; CHECK: ret;
define void @test_ldst_v8f16(ptr %a, ptr %b) {
+; CHECK-LABEL: test_ldst_v8f16(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.u64 %rd2, [test_ldst_v8f16_param_1];
+; CHECK-NEXT: ld.param.u64 %rd1, [test_ldst_v8f16_param_0];
+; CHECK-NEXT: ld.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
+; CHECK-NEXT: st.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
+; CHECK-NEXT: ret;
%t1 = load <8 x half>, ptr %a
store <8 x half> %t1, ptr %b, align 16
ret void
@@ -327,704 +461,1210 @@ define void @test_ldst_v8f16(ptr %a, ptr %b) {
declare <2 x half> @test_callee(<2 x half> %a, <2 x half> %b) #0
-; CHECK-LABEL: test_call(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_call_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_call_param_1];
-; CHECK: {
-; CHECK-DAG: .param .align 4 .b8 param0[4];
-; CHECK-DAG: .param .align 4 .b8 param1[4];
-; CHECK-DAG: st.param.b32 [param0], [[A]];
-; CHECK-DAG: st.param.b32 [param1], [[B]];
-; CHECK-DAG: .param .align 4 .b8 retval0[4];
-; CHECK: call.uni (retval0),
-; CHECK-NEXT: test_callee,
-; CHECK: );
-; CHECK-NEXT: ld.param.b32 [[R:%r[0-9]+]], [retval0];
-; CHECK-NEXT: }
-; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];
-; CHECK-NEXT: ret;
define <2 x half> @test_call(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-LABEL: test_call(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r2, [test_call_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_call_param_0];
+; CHECK-NEXT: { // callseq 0, 0
+; CHECK-NEXT: .param .align 4 .b8 param0[4];
+; CHECK-NEXT: st.param.b32 [param0], %r1;
+; CHECK-NEXT: .param .align 4 .b8 param1[4];
+; CHECK-NEXT: st.param.b32 [param1], %r2;
+; CHECK-NEXT: .param .align 4 .b8 retval0[4];
+; CHECK-NEXT: call.uni (retval0),
+; CHECK-NEXT: test_callee,
+; CHECK-NEXT: (
+; CHECK-NEXT: param0,
+; CHECK-NEXT: param1
+; CHECK-NEXT: );
+; CHECK-NEXT: ld.param.b32 %r3, [retval0];
+; CHECK-NEXT: } // callseq 0
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%r = call <2 x half> @test_callee(<2 x half> %a, <2 x half> %b)
ret <2 x half> %r
}
-; CHECK-LABEL: test_call_flipped(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_call_flipped_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_call_flipped_param_1];
-; CHECK: {
-; CHECK-DAG: .param .align 4 .b8 param0[4];
-; CHECK-DAG: .param .align 4 .b8 param1[4];
-; CHECK-DAG: st.param.b32 [param0], [[B]];
-; CHECK-DAG: st.param.b32 [param1], [[A]];
-; CHECK-DAG: .param .align 4 .b8 retval0[4];
-; CHECK: call.uni (retval0),
-; CHECK-NEXT: test_callee,
-; CHECK: );
-; CHECK-NEXT: ld.param.b32 [[R:%r[0-9]+]], [retval0];
-; CHECK-NEXT: }
-; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];
-; CHECK-NEXT: ret;
define <2 x half> @test_call_flipped(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-LABEL: test_call_flipped(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r2, [test_call_flipped_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_call_flipped_param_0];
+; CHECK-NEXT: { // callseq 1, 0
+; CHECK-NEXT: .param .align 4 .b8 param0[4];
+; CHECK-NEXT: st.param.b32 [param0], %r2;
+; CHECK-NEXT: .param .align 4 .b8 param1[4];
+; CHECK-NEXT: st.param.b32 [param1], %r1;
+; CHECK-NEXT: .param .align 4 .b8 retval0[4];
+; CHECK-NEXT: call.uni (retval0),
+; CHECK-NEXT: test_callee,
+; CHECK-NEXT: (
+; CHECK-NEXT: param0,
+; CHECK-NEXT: param1
+; CHECK-NEXT: );
+; CHECK-NEXT: ld.param.b32 %r3, [retval0];
+; CHECK-NEXT: } // callseq 1
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%r = call <2 x half> @test_callee(<2 x half> %b, <2 x half> %a)
ret <2 x half> %r
}
-; CHECK-LABEL: test_tailcall_flipped(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_tailcall_flipped_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_tailcall_flipped_param_1];
-; CHECK: {
-; CHECK-DAG: .param .align 4 .b8 param0[4];
-; CHECK-DAG: .param .align 4 .b8 param1[4];
-; CHECK-DAG: st.param.b32 [param0], [[B]];
-; CHECK-DAG: st.param.b32 [param1], [[A]];
-; CHECK-DAG: .param .align 4 .b8 retval0[4];
-; CHECK: call.uni (retval0),
-; CHECK-NEXT: test_callee,
-; CHECK: );
-; CHECK-NEXT: ld.param.b32 [[R:%r[0-9]+]], [retval0];
-; CHECK-NEXT: }
-; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];
-; CHECK-NEXT: ret;
define <2 x half> @test_tailcall_flipped(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-LABEL: test_tailcall_flipped(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r2, [test_tailcall_flipped_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_tailcall_flipped_param_0];
+; CHECK-NEXT: { // callseq 2, 0
+; CHECK-NEXT: .param .align 4 .b8 param0[4];
+; CHECK-NEXT: st.param.b32 [param0], %r2;
+; CHECK-NEXT: .param .align 4 .b8 param1[4];
+; CHECK-NEXT: st.param.b32 [param1], %r1;
+; CHECK-NEXT: .param .align 4 .b8 retval0[4];
+; CHECK-NEXT: call.uni (retval0),
+; CHECK-NEXT: test_callee,
+; CHECK-NEXT: (
+; CHECK-NEXT: param0,
+; CHECK-NEXT: param1
+; CHECK-NEXT: );
+; CHECK-NEXT: ld.param.b32 %r3, [retval0];
+; CHECK-NEXT: } // callseq 2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%r = tail call <2 x half> @test_callee(<2 x half> %b, <2 x half> %a)
ret <2 x half> %r
}
-; CHECK-LABEL: test_select(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_select_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_select_param_1];
-; CHECK-DAG: ld.param.u8 [[C:%rs[0-9]+]], [test_select_param_2]
-; CHECK-DAG: setp.eq.b16 [[PRED:%p[0-9]+]], %rs{{.*}}, 1;
-; CHECK-NEXT: selp.b32 [[R:%r[0-9]+]], [[A]], [[B]], [[PRED]];
-; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];
-; CHECK-NEXT: ret;
define <2 x half> @test_select(<2 x half> %a, <2 x half> %b, i1 zeroext %c) #0 {
+; CHECK-LABEL: test_select(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<2>;
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.u8 %rs1, [test_select_param_2];
+; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
+; CHECK-NEXT: setp.eq.b16 %p1, %rs2, 1;
+; CHECK-NEXT: ld.param.b32 %r2, [test_select_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_select_param_0];
+; CHECK-NEXT: selp.b32 %r3, %r1, %r2, %p1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%r = select i1 %c, <2 x half> %a, <2 x half> %b
ret <2 x half> %r
}
-; CHECK-LABEL: test_select_cc(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_select_cc_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_select_cc_param_1];
-; CHECK-DAG: ld.param.b32 [[C:%r[0-9]+]], [test_select_cc_param_2];
-; CHECK-DAG: ld.param.b32 [[D:%r[0-9]+]], [test_select_cc_param_3];
-;
-; CHECK-F16: setp.neu.f16x2 [[P0:%p[0-9]+]]|[[P1:%p[0-9]+]], [[C]], [[D]]
-;
-; CHECK-NOF16-DAG: mov.b32 {[[C0:%rs[0-9]+]], [[C1:%rs[0-9]+]]}, [[C]]
-; CHECK-NOF16-DAG: mov.b32 {[[D0:%rs[0-9]+]], [[D1:%rs[0-9]+]]}, [[D]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[DF0:%f[0-9]+]], [[D0]];
-; CHECK-NOF16-DAG: cvt.f32.f16 [[CF0:%f[0-9]+]], [[C0]];
-; CHECK-NOF16-DAG: cvt.f32.f16 [[DF1:%f[0-9]+]], [[D1]];
-; CHECK-NOF16-DAG: cvt.f32.f16 [[CF1:%f[0-9]+]], [[C1]];
-; CHECK-NOF16-DAG: setp.neu.f32 [[P0:%p[0-9]+]], [[CF0]], [[DF0]]
-; CHECK-NOF16-DAG: setp.neu.f32 [[P1:%p[0-9]+]], [[CF1]], [[DF1]]
-;
-; CHECK-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-DAG: selp.b16 [[R0:%rs[0-9]+]], [[A0]], [[B0]], [[P0]];
-; CHECK-DAG: selp.b16 [[R1:%rs[0-9]+]], [[A1]], [[B1]], [[P1]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];
-; CHECK-NEXT: ret;
define <2 x half> @test_select_cc(<2 x half> %a, <2 x half> %b, <2 x half> %c, <2 x half> %d) #0 {
+; CHECK-F16-LABEL: test_select_cc(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .pred %p<3>;
+; CHECK-F16-NEXT: .reg .b16 %rs<7>;
+; CHECK-F16-NEXT: .reg .b32 %r<6>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r4, [test_select_cc_param_3];
+; CHECK-F16-NEXT: ld.param.b32 %r3, [test_select_cc_param_2];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_select_cc_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_select_cc_param_0];
+; CHECK-F16-NEXT: setp.neu.f16x2 %p1|%p2, %r3, %r4;
+; CHECK-F16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-F16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-F16-NEXT: selp.b16 %rs5, %rs4, %rs2, %p2;
+; CHECK-F16-NEXT: selp.b16 %rs6, %rs3, %rs1, %p1;
+; CHECK-F16-NEXT: mov.b32 %r5, {%rs6, %rs5};
+; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r5;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_select_cc(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .pred %p<3>;
+; CHECK-NOF16-NEXT: .reg .b16 %rs<11>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<6>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<5>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r4, [test_select_cc_param_3];
+; CHECK-NOF16-NEXT: ld.param.b32 %r3, [test_select_cc_param_2];
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_select_cc_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_select_cc_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs1;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs3;
+; CHECK-NOF16-NEXT: setp.neu.f32 %p1, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f3, %rs2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f4, %rs4;
+; CHECK-NOF16-NEXT: setp.neu.f32 %p2, %f4, %f3;
+; CHECK-NOF16-NEXT: mov.b32 {%rs5, %rs6}, %r2;
+; CHECK-NOF16-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; CHECK-NOF16-NEXT: selp.b16 %rs9, %rs8, %rs6, %p2;
+; CHECK-NOF16-NEXT: selp.b16 %rs10, %rs7, %rs5, %p1;
+; CHECK-NOF16-NEXT: mov.b32 %r5, {%rs10, %rs9};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r5;
+; CHECK-NOF16-NEXT: ret;
%cc = fcmp une <2 x half> %c, %d
%r = select <2 x i1> %cc, <2 x half> %a, <2 x half> %b
ret <2 x half> %r
}
-; CHECK-LABEL: test_select_cc_f32_f16(
-; CHECK-DAG: ld.param.v2.f32 {[[A0:%f[0-9]+]], [[A1:%f[0-9]+]]}, [test_select_cc_f32_f16_param_0];
-; CHECK-DAG: ld.param.v2.f32 {[[B0:%f[0-9]+]], [[B1:%f[0-9]+]]}, [test_select_cc_f32_f16_param_1];
-; CHECK-DAG: ld.param.b32 [[C:%r[0-9]+]], [test_select_cc_f32_f16_param_2];
-; CHECK-DAG: ld.param.b32 [[D:%r[0-9]+]], [test_select_cc_f32_f16_param_3];
-;
-; CHECK-F16: setp.neu.f16x2 [[P0:%p[0-9]+]]|[[P1:%p[0-9]+]], [[C]], [[D]]
-; CHECK-NOF16-DAG: mov.b32 {[[C0:%rs[0-9]+]], [[C1:%rs[0-9]+]]}, [[C]]
-; CHECK-NOF16-DAG: mov.b32 {[[D0:%rs[0-9]+]], [[D1:%rs[0-9]+]]}, [[D]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[DF0:%f[0-9]+]], [[D0]];
-; CHECK-NOF16-DAG: cvt.f32.f16 [[CF0:%f[0-9]+]], [[C0]];
-; CHECK-NOF16-DAG: cvt.f32.f16 [[DF1:%f[0-9]+]], [[D1]];
-; CHECK-NOF16-DAG: cvt.f32.f16 [[CF1:%f[0-9]+]], [[C1]];
-; CHECK-NOF16-DAG: setp.neu.f32 [[P0:%p[0-9]+]], [[CF0]], [[DF0]]
-; CHECK-NOF16-DAG: setp.neu.f32 [[P1:%p[0-9]+]], [[CF1]], [[DF1]]
-;
-; CHECK-DAG: selp.f32 [[R0:%f[0-9]+]], [[A0]], [[B0]], [[P0]];
-; CHECK-DAG: selp.f32 [[R1:%f[0-9]+]], [[A1]], [[B1]], [[P1]];
-; CHECK-NEXT: st.param.v2.f32 [func_retval0], {[[R0]], [[R1]]};
-; CHECK-NEXT: ret;
define <2 x float> @test_select_cc_f32_f16(<2 x float> %a, <2 x float> %b,
+; CHECK-F16-LABEL: test_select_cc_f32_f16(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .pred %p<3>;
+; CHECK-F16-NEXT: .reg .b32 %r<3>;
+; CHECK-F16-NEXT: .reg .f32 %f<7>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.v2.f32 {%f3, %f4}, [test_select_cc_f32_f16_param_1];
+; CHECK-F16-NEXT: ld.param.v2.f32 {%f1, %f2}, [test_select_cc_f32_f16_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_select_cc_f32_f16_param_3];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_select_cc_f32_f16_param_2];
+; CHECK-F16-NEXT: setp.neu.f16x2 %p1|%p2, %r1, %r2;
+; CHECK-F16-NEXT: selp.f32 %f5, %f2, %f4, %p2;
+; CHECK-F16-NEXT: selp.f32 %f6, %f1, %f3, %p1;
+; CHECK-F16-NEXT: st.param.v2.f32 [func_retval0], {%f6, %f5};
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_select_cc_f32_f16(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .pred %p<3>;
+; CHECK-NOF16-NEXT: .reg .b16 %rs<5>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<11>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.v2.f32 {%f3, %f4}, [test_select_cc_f32_f16_param_1];
+; CHECK-NOF16-NEXT: ld.param.v2.f32 {%f1, %f2}, [test_select_cc_f32_f16_param_0];
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_select_cc_f32_f16_param_3];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_select_cc_f32_f16_param_2];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f5, %rs1;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f6, %rs3;
+; CHECK-NOF16-NEXT: setp.neu.f32 %p1, %f6, %f5;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f7, %rs2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f8, %rs4;
+; CHECK-NOF16-NEXT: setp.neu.f32 %p2, %f8, %f7;
+; CHECK-NOF16-NEXT: selp.f32 %f9, %f2, %f4, %p2;
+; CHECK-NOF16-NEXT: selp.f32 %f10, %f1, %f3, %p1;
+; CHECK-NOF16-NEXT: st.param.v2.f32 [func_retval0], {%f10, %f9};
+; CHECK-NOF16-NEXT: ret;
<2 x half> %c, <2 x half> %d) #0 {
%cc = fcmp une <2 x half> %c, %d
%r = select <2 x i1> %cc, <2 x float> %a, <2 x float> %b
ret <2 x float> %r
}
-; CHECK-LABEL: test_select_cc_f16_f32(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_select_cc_f16_f32_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_select_cc_f16_f32_param_1];
-; CHECK-DAG: ld.param.v2.f32 {[[C0:%f[0-9]+]], [[C1:%f[0-9]+]]}, [test_select_cc_f16_f32_param_2];
-; CHECK-DAG: ld.param.v2.f32 {[[D0:%f[0-9]+]], [[D1:%f[0-9]+]]}, [test_select_cc_f16_f32_param_3];
-; CHECK-DAG: setp.neu.f32 [[P0:%p[0-9]+]], [[C0]], [[D0]]
-; CHECK-DAG: setp.neu.f32 [[P1:%p[0-9]+]], [[C1]], [[D1]]
-; CHECK-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-DAG: selp.b16 [[R0:%rs[0-9]+]], [[A0]], [[B0]], [[P0]];
-; CHECK-DAG: selp.b16 [[R1:%rs[0-9]+]], [[A1]], [[B1]], [[P1]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];
-; CHECK-NEXT: ret;
define <2 x half> @test_select_cc_f16_f32(<2 x half> %a, <2 x half> %b,
+; CHECK-LABEL: test_select_cc_f16_f32(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<3>;
+; CHECK-NEXT: .reg .b16 %rs<7>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-NEXT: .reg .f32 %f<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.v2.f32 {%f3, %f4}, [test_select_cc_f16_f32_param_3];
+; CHECK-NEXT: ld.param.v2.f32 {%f1, %f2}, [test_select_cc_f16_f32_param_2];
+; CHECK-NEXT: ld.param.b32 %r2, [test_select_cc_f16_f32_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_select_cc_f16_f32_param_0];
+; CHECK-NEXT: setp.neu.f32 %p1, %f1, %f3;
+; CHECK-NEXT: setp.neu.f32 %p2, %f2, %f4;
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NEXT: selp.b16 %rs5, %rs4, %rs2, %p2;
+; CHECK-NEXT: selp.b16 %rs6, %rs3, %rs1, %p1;
+; CHECK-NEXT: mov.b32 %r3, {%rs6, %rs5};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
<2 x float> %c, <2 x float> %d) #0 {
%cc = fcmp une <2 x float> %c, %d
%r = select <2 x i1> %cc, <2 x half> %a, <2 x half> %b
ret <2 x half> %r
}
-; CHECK-LABEL: test_fcmp_une(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fcmp_une_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fcmp_une_param_1];
-; CHECK-F16: setp.neu.f16x2 [[P0:%p[0-9]+]]|[[P1:%p[0-9]+]], [[A]], [[B]]
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]]
-; CHECK-NOF16-DAG: setp.neu.f32 [[P0:%p[0-9]+]], [[FA0]], [[FB0]]
-; CHECK-NOF16-DAG: setp.neu.f32 [[P1:%p[0-9]+]], [[FA1]], [[FB1]]
-; CHECK-DAG: selp.u16 [[R0:%rs[0-9]+]], -1, 0, [[P0]];
-; CHECK-NEXT: st.param.b8 [func_retval0], [[R0]];
-; CHECK-DAG: selp.u16 [[R1:%rs[0-9]+]], -1, 0, [[P1]];
-; CHECK-NEXT: st.param.b8 [func_retval0+1], [[R1]];
-; CHECK-NEXT: ret;
define <2 x i1> @test_fcmp_une(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-F16-LABEL: test_fcmp_une(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .pred %p<3>;
+; CHECK-F16-NEXT: .reg .b16 %rs<3>;
+; CHECK-F16-NEXT: .reg .b32 %r<3>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_une_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_une_param_0];
+; CHECK-F16-NEXT: setp.neu.f16x2 %p1|%p2, %r1, %r2;
+; CHECK-F16-NEXT: selp.u16 %rs1, -1, 0, %p1;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F16-NEXT: selp.u16 %rs2, -1, 0, %p2;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fcmp_une(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .pred %p<3>;
+; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<5>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_une_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_une_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NOF16-NEXT: setp.neu.f32 %p1, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f4, %rs3;
+; CHECK-NOF16-NEXT: setp.neu.f32 %p2, %f4, %f3;
+; CHECK-NOF16-NEXT: selp.u16 %rs5, -1, 0, %p2;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
+; CHECK-NOF16-NEXT: selp.u16 %rs6, -1, 0, %p1;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0+1], %rs6;
+; CHECK-NOF16-NEXT: ret;
%r = fcmp une <2 x half> %a, %b
ret <2 x i1> %r
}
-; CHECK-LABEL: test_fcmp_ueq(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fcmp_ueq_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fcmp_ueq_param_1];
-; CHECK-F16: setp.equ.f16x2 [[P0:%p[0-9]+]]|[[P1:%p[0-9]+]], [[A]], [[B]]
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]]
-; CHECK-NOF16-DAG: setp.equ.f32 [[P0:%p[0-9]+]], [[FA0]], [[FB0]]
-; CHECK-NOF16-DAG: setp.equ.f32 [[P1:%p[0-9]+]], [[FA1]], [[FB1]]
-; CHECK-DAG: selp.u16 [[R0:%rs[0-9]+]], -1, 0, [[P0]];
-; CHECK-NEXT: st.param.b8 [func_retval0], [[R0]];
-; CHECK-DAG: selp.u16 [[R1:%rs[0-9]+]], -1, 0, [[P1]];
-; CHECK-NEXT: st.param.b8 [func_retval0+1], [[R1]];
-; CHECK-NEXT: ret;
define <2 x i1> @test_fcmp_ueq(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-F16-LABEL: test_fcmp_ueq(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .pred %p<3>;
+; CHECK-F16-NEXT: .reg .b16 %rs<3>;
+; CHECK-F16-NEXT: .reg .b32 %r<3>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_ueq_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_ueq_param_0];
+; CHECK-F16-NEXT: setp.equ.f16x2 %p1|%p2, %r1, %r2;
+; CHECK-F16-NEXT: selp.u16 %rs1, -1, 0, %p1;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F16-NEXT: selp.u16 %rs2, -1, 0, %p2;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fcmp_ueq(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .pred %p<3>;
+; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<5>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_ueq_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_ueq_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NOF16-NEXT: setp.equ.f32 %p1, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f4, %rs3;
+; CHECK-NOF16-NEXT: setp.equ.f32 %p2, %f4, %f3;
+; CHECK-NOF16-NEXT: selp.u16 %rs5, -1, 0, %p2;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
+; CHECK-NOF16-NEXT: selp.u16 %rs6, -1, 0, %p1;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0+1], %rs6;
+; CHECK-NOF16-NEXT: ret;
%r = fcmp ueq <2 x half> %a, %b
ret <2 x i1> %r
}
-; CHECK-LABEL: test_fcmp_ugt(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fcmp_ugt_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fcmp_ugt_param_1];
-; CHECK-F16: setp.gtu.f16x2 [[P0:%p[0-9]+]]|[[P1:%p[0-9]+]], [[A]], [[B]]
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]]
-; CHECK-NOF16-DAG: setp.gtu.f32 [[P0:%p[0-9]+]], [[FA0]], [[FB0]]
-; CHECK-NOF16-DAG: setp.gtu.f32 [[P1:%p[0-9]+]], [[FA1]], [[FB1]]
-; CHECK-DAG: selp.u16 [[R0:%rs[0-9]+]], -1, 0, [[P0]];
-; CHECK-NEXT: st.param.b8 [func_retval0], [[R0]];
-; CHECK-DAG: selp.u16 [[R1:%rs[0-9]+]], -1, 0, [[P1]];
-; CHECK-NEXT: st.param.b8 [func_retval0+1], [[R1]];
-; CHECK-NEXT: ret;
define <2 x i1> @test_fcmp_ugt(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-F16-LABEL: test_fcmp_ugt(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .pred %p<3>;
+; CHECK-F16-NEXT: .reg .b16 %rs<3>;
+; CHECK-F16-NEXT: .reg .b32 %r<3>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_ugt_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_ugt_param_0];
+; CHECK-F16-NEXT: setp.gtu.f16x2 %p1|%p2, %r1, %r2;
+; CHECK-F16-NEXT: selp.u16 %rs1, -1, 0, %p1;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F16-NEXT: selp.u16 %rs2, -1, 0, %p2;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fcmp_ugt(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .pred %p<3>;
+; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<5>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_ugt_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_ugt_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NOF16-NEXT: setp.gtu.f32 %p1, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f4, %rs3;
+; CHECK-NOF16-NEXT: setp.gtu.f32 %p2, %f4, %f3;
+; CHECK-NOF16-NEXT: selp.u16 %rs5, -1, 0, %p2;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
+; CHECK-NOF16-NEXT: selp.u16 %rs6, -1, 0, %p1;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0+1], %rs6;
+; CHECK-NOF16-NEXT: ret;
%r = fcmp ugt <2 x half> %a, %b
ret <2 x i1> %r
}
-; CHECK-LABEL: test_fcmp_uge(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fcmp_uge_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fcmp_uge_param_1];
-; CHECK-F16: setp.geu.f16x2 [[P0:%p[0-9]+]]|[[P1:%p[0-9]+]], [[A]], [[B]]
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]]
-; CHECK-NOF16-DAG: setp.geu.f32 [[P0:%p[0-9]+]], [[FA0]], [[FB0]]
-; CHECK-NOF16-DAG: setp.geu.f32 [[P1:%p[0-9]+]], [[FA1]], [[FB1]]
-; CHECK-DAG: selp.u16 [[R0:%rs[0-9]+]], -1, 0, [[P0]];
-; CHECK-NEXT: st.param.b8 [func_retval0], [[R0]];
-; CHECK-DAG: selp.u16 [[R1:%rs[0-9]+]], -1, 0, [[P1]];
-; CHECK-NEXT: st.param.b8 [func_retval0+1], [[R1]];
-; CHECK-NEXT: ret;
define <2 x i1> @test_fcmp_uge(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-F16-LABEL: test_fcmp_uge(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .pred %p<3>;
+; CHECK-F16-NEXT: .reg .b16 %rs<3>;
+; CHECK-F16-NEXT: .reg .b32 %r<3>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_uge_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_uge_param_0];
+; CHECK-F16-NEXT: setp.geu.f16x2 %p1|%p2, %r1, %r2;
+; CHECK-F16-NEXT: selp.u16 %rs1, -1, 0, %p1;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F16-NEXT: selp.u16 %rs2, -1, 0, %p2;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fcmp_uge(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .pred %p<3>;
+; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<5>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_uge_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_uge_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NOF16-NEXT: setp.geu.f32 %p1, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f4, %rs3;
+; CHECK-NOF16-NEXT: setp.geu.f32 %p2, %f4, %f3;
+; CHECK-NOF16-NEXT: selp.u16 %rs5, -1, 0, %p2;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
+; CHECK-NOF16-NEXT: selp.u16 %rs6, -1, 0, %p1;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0+1], %rs6;
+; CHECK-NOF16-NEXT: ret;
%r = fcmp uge <2 x half> %a, %b
ret <2 x i1> %r
}
-; CHECK-LABEL: test_fcmp_ult(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fcmp_ult_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fcmp_ult_param_1];
-; CHECK-F16: setp.ltu.f16x2 [[P0:%p[0-9]+]]|[[P1:%p[0-9]+]], [[A]], [[B]]
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]]
-; CHECK-NOF16-DAG: setp.ltu.f32 [[P0:%p[0-9]+]], [[FA0]], [[FB0]]
-; CHECK-NOF16-DAG: setp.ltu.f32 [[P1:%p[0-9]+]], [[FA1]], [[FB1]]
-; CHECK-DAG: selp.u16 [[R0:%rs[0-9]+]], -1, 0, [[P0]];
-; CHECK-NEXT: st.param.b8 [func_retval0], [[R0]];
-; CHECK-DAG: selp.u16 [[R1:%rs[0-9]+]], -1, 0, [[P1]];
-; CHECK-NEXT: st.param.b8 [func_retval0+1], [[R1]];
-; CHECK-NEXT: ret;
define <2 x i1> @test_fcmp_ult(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-F16-LABEL: test_fcmp_ult(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .pred %p<3>;
+; CHECK-F16-NEXT: .reg .b16 %rs<3>;
+; CHECK-F16-NEXT: .reg .b32 %r<3>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_ult_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_ult_param_0];
+; CHECK-F16-NEXT: setp.ltu.f16x2 %p1|%p2, %r1, %r2;
+; CHECK-F16-NEXT: selp.u16 %rs1, -1, 0, %p1;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F16-NEXT: selp.u16 %rs2, -1, 0, %p2;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fcmp_ult(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .pred %p<3>;
+; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<5>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_ult_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_ult_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NOF16-NEXT: setp.ltu.f32 %p1, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f4, %rs3;
+; CHECK-NOF16-NEXT: setp.ltu.f32 %p2, %f4, %f3;
+; CHECK-NOF16-NEXT: selp.u16 %rs5, -1, 0, %p2;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
+; CHECK-NOF16-NEXT: selp.u16 %rs6, -1, 0, %p1;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0+1], %rs6;
+; CHECK-NOF16-NEXT: ret;
%r = fcmp ult <2 x half> %a, %b
ret <2 x i1> %r
}
-; CHECK-LABEL: test_fcmp_ule(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fcmp_ule_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fcmp_ule_param_1];
-; CHECK-F16: setp.leu.f16x2 [[P0:%p[0-9]+]]|[[P1:%p[0-9]+]], [[A]], [[B]]
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]]
-; CHECK-NOF16-DAG: setp.leu.f32 [[P0:%p[0-9]+]], [[FA0]], [[FB0]]
-; CHECK-NOF16-DAG: setp.leu.f32 [[P1:%p[0-9]+]], [[FA1]], [[FB1]]
-; CHECK-DAG: selp.u16 [[R0:%rs[0-9]+]], -1, 0, [[P0]];
-; CHECK-NEXT: st.param.b8 [func_retval0], [[R0]];
-; CHECK-DAG: selp.u16 [[R1:%rs[0-9]+]], -1, 0, [[P1]];
-; CHECK-NEXT: st.param.b8 [func_retval0+1], [[R1]];
-; CHECK-NEXT: ret;
define <2 x i1> @test_fcmp_ule(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-F16-LABEL: test_fcmp_ule(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .pred %p<3>;
+; CHECK-F16-NEXT: .reg .b16 %rs<3>;
+; CHECK-F16-NEXT: .reg .b32 %r<3>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_ule_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_ule_param_0];
+; CHECK-F16-NEXT: setp.leu.f16x2 %p1|%p2, %r1, %r2;
+; CHECK-F16-NEXT: selp.u16 %rs1, -1, 0, %p1;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F16-NEXT: selp.u16 %rs2, -1, 0, %p2;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fcmp_ule(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .pred %p<3>;
+; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<5>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_ule_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_ule_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NOF16-NEXT: setp.leu.f32 %p1, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f4, %rs3;
+; CHECK-NOF16-NEXT: setp.leu.f32 %p2, %f4, %f3;
+; CHECK-NOF16-NEXT: selp.u16 %rs5, -1, 0, %p2;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
+; CHECK-NOF16-NEXT: selp.u16 %rs6, -1, 0, %p1;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0+1], %rs6;
+; CHECK-NOF16-NEXT: ret;
%r = fcmp ule <2 x half> %a, %b
ret <2 x i1> %r
}
-; CHECK-LABEL: test_fcmp_uno(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fcmp_uno_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fcmp_uno_param_1];
-; CHECK-F16: setp.nan.f16x2 [[P0:%p[0-9]+]]|[[P1:%p[0-9]+]], [[A]], [[B]]
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]]
-; CHECK-NOF16-DAG: setp.nan.f32 [[P0:%p[0-9]+]], [[FA0]], [[FB0]]
-; CHECK-NOF16-DAG: setp.nan.f32 [[P1:%p[0-9]+]], [[FA1]], [[FB1]]
-; CHECK-DAG: selp.u16 [[R0:%rs[0-9]+]], -1, 0, [[P0]];
-; CHECK-NEXT: st.param.b8 [func_retval0], [[R0]];
-; CHECK-DAG: selp.u16 [[R1:%rs[0-9]+]], -1, 0, [[P1]];
-; CHECK-NEXT: st.param.b8 [func_retval0+1], [[R1]];
-; CHECK-NEXT: ret;
define <2 x i1> @test_fcmp_uno(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-F16-LABEL: test_fcmp_uno(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .pred %p<3>;
+; CHECK-F16-NEXT: .reg .b16 %rs<3>;
+; CHECK-F16-NEXT: .reg .b32 %r<3>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_uno_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_uno_param_0];
+; CHECK-F16-NEXT: setp.nan.f16x2 %p1|%p2, %r1, %r2;
+; CHECK-F16-NEXT: selp.u16 %rs1, -1, 0, %p1;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F16-NEXT: selp.u16 %rs2, -1, 0, %p2;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fcmp_uno(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .pred %p<3>;
+; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<5>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_uno_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_uno_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NOF16-NEXT: setp.nan.f32 %p1, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f4, %rs3;
+; CHECK-NOF16-NEXT: setp.nan.f32 %p2, %f4, %f3;
+; CHECK-NOF16-NEXT: selp.u16 %rs5, -1, 0, %p2;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
+; CHECK-NOF16-NEXT: selp.u16 %rs6, -1, 0, %p1;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0+1], %rs6;
+; CHECK-NOF16-NEXT: ret;
%r = fcmp uno <2 x half> %a, %b
ret <2 x i1> %r
}
-; CHECK-LABEL: test_fcmp_one(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fcmp_one_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fcmp_one_param_1];
-; CHECK-F16: setp.ne.f16x2 [[P0:%p[0-9]+]]|[[P1:%p[0-9]+]], [[A]], [[B]]
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]]
-; CHECK-NOF16-DAG: setp.ne.f32 [[P0:%p[0-9]+]], [[FA0]], [[FB0]]
-; CHECK-NOF16-DAG: setp.ne.f32 [[P1:%p[0-9]+]], [[FA1]], [[FB1]]
-; CHECK-DAG: selp.u16 [[R0:%rs[0-9]+]], -1, 0, [[P0]];
-; CHECK-NEXT: st.param.b8 [func_retval0], [[R0]];
-; CHECK-DAG: selp.u16 [[R1:%rs[0-9]+]], -1, 0, [[P1]];
-; CHECK-NEXT: st.param.b8 [func_retval0+1], [[R1]];
-; CHECK-NEXT: ret;
define <2 x i1> @test_fcmp_one(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-F16-LABEL: test_fcmp_one(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .pred %p<3>;
+; CHECK-F16-NEXT: .reg .b16 %rs<3>;
+; CHECK-F16-NEXT: .reg .b32 %r<3>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_one_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_one_param_0];
+; CHECK-F16-NEXT: setp.ne.f16x2 %p1|%p2, %r1, %r2;
+; CHECK-F16-NEXT: selp.u16 %rs1, -1, 0, %p1;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F16-NEXT: selp.u16 %rs2, -1, 0, %p2;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fcmp_one(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .pred %p<3>;
+; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<5>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_one_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_one_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NOF16-NEXT: setp.ne.f32 %p1, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f4, %rs3;
+; CHECK-NOF16-NEXT: setp.ne.f32 %p2, %f4, %f3;
+; CHECK-NOF16-NEXT: selp.u16 %rs5, -1, 0, %p2;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
+; CHECK-NOF16-NEXT: selp.u16 %rs6, -1, 0, %p1;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0+1], %rs6;
+; CHECK-NOF16-NEXT: ret;
%r = fcmp one <2 x half> %a, %b
ret <2 x i1> %r
}
-; CHECK-LABEL: test_fcmp_oeq(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fcmp_oeq_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fcmp_oeq_param_1];
-; CHECK-F16: setp.eq.f16x2 [[P0:%p[0-9]+]]|[[P1:%p[0-9]+]], [[A]], [[B]]
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]]
-; CHECK-NOF16-DAG: setp.eq.f32 [[P0:%p[0-9]+]], [[FA0]], [[FB0]]
-; CHECK-NOF16-DAG: setp.eq.f32 [[P1:%p[0-9]+]], [[FA1]], [[FB1]]
-; CHECK-DAG: selp.u16 [[R0:%rs[0-9]+]], -1, 0, [[P0]];
-; CHECK-NEXT: st.param.b8 [func_retval0], [[R0]];
-; CHECK-DAG: selp.u16 [[R1:%rs[0-9]+]], -1, 0, [[P1]];
-; CHECK-NEXT: st.param.b8 [func_retval0+1], [[R1]];
-; CHECK-NEXT: ret;
define <2 x i1> @test_fcmp_oeq(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-F16-LABEL: test_fcmp_oeq(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .pred %p<3>;
+; CHECK-F16-NEXT: .reg .b16 %rs<3>;
+; CHECK-F16-NEXT: .reg .b32 %r<3>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_oeq_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_oeq_param_0];
+; CHECK-F16-NEXT: setp.eq.f16x2 %p1|%p2, %r1, %r2;
+; CHECK-F16-NEXT: selp.u16 %rs1, -1, 0, %p1;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F16-NEXT: selp.u16 %rs2, -1, 0, %p2;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fcmp_oeq(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .pred %p<3>;
+; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<5>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_oeq_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_oeq_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NOF16-NEXT: setp.eq.f32 %p1, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f4, %rs3;
+; CHECK-NOF16-NEXT: setp.eq.f32 %p2, %f4, %f3;
+; CHECK-NOF16-NEXT: selp.u16 %rs5, -1, 0, %p2;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
+; CHECK-NOF16-NEXT: selp.u16 %rs6, -1, 0, %p1;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0+1], %rs6;
+; CHECK-NOF16-NEXT: ret;
%r = fcmp oeq <2 x half> %a, %b
ret <2 x i1> %r
}
-; CHECK-LABEL: test_fcmp_ogt(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fcmp_ogt_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fcmp_ogt_param_1];
-; CHECK-F16: setp.gt.f16x2 [[P0:%p[0-9]+]]|[[P1:%p[0-9]+]], [[A]], [[B]]
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]]
-; CHECK-NOF16-DAG: setp.gt.f32 [[P0:%p[0-9]+]], [[FA0]], [[FB0]]
-; CHECK-NOF16-DAG: setp.gt.f32 [[P1:%p[0-9]+]], [[FA1]], [[FB1]]
-; CHECK-DAG: selp.u16 [[R0:%rs[0-9]+]], -1, 0, [[P0]];
-; CHECK-NEXT: st.param.b8 [func_retval0], [[R0]];
-; CHECK-DAG: selp.u16 [[R1:%rs[0-9]+]], -1, 0, [[P1]];
-; CHECK-NEXT: st.param.b8 [func_retval0+1], [[R1]];
-; CHECK-NEXT: ret;
define <2 x i1> @test_fcmp_ogt(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-F16-LABEL: test_fcmp_ogt(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .pred %p<3>;
+; CHECK-F16-NEXT: .reg .b16 %rs<3>;
+; CHECK-F16-NEXT: .reg .b32 %r<3>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_ogt_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_ogt_param_0];
+; CHECK-F16-NEXT: setp.gt.f16x2 %p1|%p2, %r1, %r2;
+; CHECK-F16-NEXT: selp.u16 %rs1, -1, 0, %p1;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F16-NEXT: selp.u16 %rs2, -1, 0, %p2;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fcmp_ogt(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .pred %p<3>;
+; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<5>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_ogt_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_ogt_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NOF16-NEXT: setp.gt.f32 %p1, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f4, %rs3;
+; CHECK-NOF16-NEXT: setp.gt.f32 %p2, %f4, %f3;
+; CHECK-NOF16-NEXT: selp.u16 %rs5, -1, 0, %p2;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
+; CHECK-NOF16-NEXT: selp.u16 %rs6, -1, 0, %p1;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0+1], %rs6;
+; CHECK-NOF16-NEXT: ret;
%r = fcmp ogt <2 x half> %a, %b
ret <2 x i1> %r
}
-; CHECK-LABEL: test_fcmp_oge(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fcmp_oge_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fcmp_oge_param_1];
-; CHECK-F16: setp.ge.f16x2 [[P0:%p[0-9]+]]|[[P1:%p[0-9]+]], [[A]], [[B]]
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]]
-; CHECK-NOF16-DAG: setp.ge.f32 [[P0:%p[0-9]+]], [[FA0]], [[FB0]]
-; CHECK-NOF16-DAG: setp.ge.f32 [[P1:%p[0-9]+]], [[FA1]], [[FB1]]
-; CHECK-DAG: selp.u16 [[R0:%rs[0-9]+]], -1, 0, [[P0]];
-; CHECK-NEXT: st.param.b8 [func_retval0], [[R0]];
-; CHECK-DAG: selp.u16 [[R1:%rs[0-9]+]], -1, 0, [[P1]];
-; CHECK-NEXT: st.param.b8 [func_retval0+1], [[R1]];
-; CHECK-NEXT: ret;
define <2 x i1> @test_fcmp_oge(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-F16-LABEL: test_fcmp_oge(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .pred %p<3>;
+; CHECK-F16-NEXT: .reg .b16 %rs<3>;
+; CHECK-F16-NEXT: .reg .b32 %r<3>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_oge_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_oge_param_0];
+; CHECK-F16-NEXT: setp.ge.f16x2 %p1|%p2, %r1, %r2;
+; CHECK-F16-NEXT: selp.u16 %rs1, -1, 0, %p1;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F16-NEXT: selp.u16 %rs2, -1, 0, %p2;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fcmp_oge(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .pred %p<3>;
+; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<5>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_oge_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_oge_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NOF16-NEXT: setp.ge.f32 %p1, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f4, %rs3;
+; CHECK-NOF16-NEXT: setp.ge.f32 %p2, %f4, %f3;
+; CHECK-NOF16-NEXT: selp.u16 %rs5, -1, 0, %p2;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
+; CHECK-NOF16-NEXT: selp.u16 %rs6, -1, 0, %p1;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0+1], %rs6;
+; CHECK-NOF16-NEXT: ret;
%r = fcmp oge <2 x half> %a, %b
ret <2 x i1> %r
}
-; CHECK-LABEL: test_fcmp_olt(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fcmp_olt_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fcmp_olt_param_1];
-; CHECK-F16: setp.lt.f16x2 [[P0:%p[0-9]+]]|[[P1:%p[0-9]+]], [[A]], [[B]]
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]]
-; CHECK-NOF16-DAG: setp.lt.f32 [[P0:%p[0-9]+]], [[FA0]], [[FB0]]
-; CHECK-NOF16-DAG: setp.lt.f32 [[P1:%p[0-9]+]], [[FA1]], [[FB1]]
-; CHECK-DAG: selp.u16 [[R0:%rs[0-9]+]], -1, 0, [[P0]];
-; CHECK-NEXT: st.param.b8 [func_retval0], [[R0]];
-; CHECK-DAG: selp.u16 [[R1:%rs[0-9]+]], -1, 0, [[P1]];
-; CHECK-NEXT: st.param.b8 [func_retval0+1], [[R1]];
-; CHECK-NEXT: ret;
define <2 x i1> @test_fcmp_olt(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-F16-LABEL: test_fcmp_olt(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .pred %p<3>;
+; CHECK-F16-NEXT: .reg .b16 %rs<3>;
+; CHECK-F16-NEXT: .reg .b32 %r<3>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_olt_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_olt_param_0];
+; CHECK-F16-NEXT: setp.lt.f16x2 %p1|%p2, %r1, %r2;
+; CHECK-F16-NEXT: selp.u16 %rs1, -1, 0, %p1;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F16-NEXT: selp.u16 %rs2, -1, 0, %p2;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fcmp_olt(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .pred %p<3>;
+; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<5>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_olt_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_olt_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NOF16-NEXT: setp.lt.f32 %p1, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f4, %rs3;
+; CHECK-NOF16-NEXT: setp.lt.f32 %p2, %f4, %f3;
+; CHECK-NOF16-NEXT: selp.u16 %rs5, -1, 0, %p2;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
+; CHECK-NOF16-NEXT: selp.u16 %rs6, -1, 0, %p1;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0+1], %rs6;
+; CHECK-NOF16-NEXT: ret;
%r = fcmp olt <2 x half> %a, %b
ret <2 x i1> %r
}
-; XCHECK-LABEL: test_fcmp_ole(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fcmp_ole_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fcmp_ole_param_1];
-; CHECK-F16: setp.le.f16x2 [[P0:%p[0-9]+]]|[[P1:%p[0-9]+]], [[A]], [[B]]
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]]
-; CHECK-NOF16-DAG: setp.le.f32 [[P0:%p[0-9]+]], [[FA0]], [[FB0]]
-; CHECK-NOF16-DAG: setp.le.f32 [[P1:%p[0-9]+]], [[FA1]], [[FB1]]
-; CHECK-DAG: selp.u16 [[R0:%rs[0-9]+]], -1, 0, [[P0]];
-; CHECK-NEXT: st.param.b8 [func_retval0], [[R0]];
-; CHECK-DAG: selp.u16 [[R1:%rs[0-9]+]], -1, 0, [[P1]];
-; CHECK-NEXT: st.param.b8 [func_retval0+1], [[R1]];
-; CHECK-NEXT: ret;
define <2 x i1> @test_fcmp_ole(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-F16-LABEL: test_fcmp_ole(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .pred %p<3>;
+; CHECK-F16-NEXT: .reg .b16 %rs<3>;
+; CHECK-F16-NEXT: .reg .b32 %r<3>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_ole_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_ole_param_0];
+; CHECK-F16-NEXT: setp.le.f16x2 %p1|%p2, %r1, %r2;
+; CHECK-F16-NEXT: selp.u16 %rs1, -1, 0, %p1;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F16-NEXT: selp.u16 %rs2, -1, 0, %p2;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fcmp_ole(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .pred %p<3>;
+; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<5>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_ole_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_ole_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NOF16-NEXT: setp.le.f32 %p1, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f4, %rs3;
+; CHECK-NOF16-NEXT: setp.le.f32 %p2, %f4, %f3;
+; CHECK-NOF16-NEXT: selp.u16 %rs5, -1, 0, %p2;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
+; CHECK-NOF16-NEXT: selp.u16 %rs6, -1, 0, %p1;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0+1], %rs6;
+; CHECK-NOF16-NEXT: ret;
%r = fcmp ole <2 x half> %a, %b
ret <2 x i1> %r
}
-; CHECK-LABEL: test_fcmp_ord(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fcmp_ord_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fcmp_ord_param_1];
-; CHECK-F16: setp.num.f16x2 [[P0:%p[0-9]+]]|[[P1:%p[0-9]+]], [[A]], [[B]]
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]]
-; CHECK-NOF16-DAG: setp.num.f32 [[P0:%p[0-9]+]], [[FA0]], [[FB0]]
-; CHECK-NOF16-DAG: setp.num.f32 [[P1:%p[0-9]+]], [[FA1]], [[FB1]]
-; CHECK-DAG: selp.u16 [[R0:%rs[0-9]+]], -1, 0, [[P0]];
-; CHECK-NEXT: st.param.b8 [func_retval0], [[R0]];
-; CHECK-DAG: selp.u16 [[R1:%rs[0-9]+]], -1, 0, [[P1]];
-; CHECK-NEXT: st.param.b8 [func_retval0+1], [[R1]];
-; CHECK-NEXT: ret;
define <2 x i1> @test_fcmp_ord(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-F16-LABEL: test_fcmp_ord(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .pred %p<3>;
+; CHECK-F16-NEXT: .reg .b16 %rs<3>;
+; CHECK-F16-NEXT: .reg .b32 %r<3>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_ord_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_ord_param_0];
+; CHECK-F16-NEXT: setp.num.f16x2 %p1|%p2, %r1, %r2;
+; CHECK-F16-NEXT: selp.u16 %rs1, -1, 0, %p1;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
+; CHECK-F16-NEXT: selp.u16 %rs2, -1, 0, %p2;
+; CHECK-F16-NEXT: st.param.b8 [func_retval0+1], %rs2;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fcmp_ord(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .pred %p<3>;
+; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<5>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_ord_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_ord_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NOF16-NEXT: setp.num.f32 %p1, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f4, %rs3;
+; CHECK-NOF16-NEXT: setp.num.f32 %p2, %f4, %f3;
+; CHECK-NOF16-NEXT: selp.u16 %rs5, -1, 0, %p2;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
+; CHECK-NOF16-NEXT: selp.u16 %rs6, -1, 0, %p1;
+; CHECK-NOF16-NEXT: st.param.b8 [func_retval0+1], %rs6;
+; CHECK-NOF16-NEXT: ret;
%r = fcmp ord <2 x half> %a, %b
ret <2 x i1> %r
}
-; CHECK-LABEL: test_fptosi_i32(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_fptosi_i32_param_0];
-; CHECK: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-DAG: cvt.rzi.s32.f16 [[R0:%r[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.rzi.s32.f16 [[R1:%r[0-9]+]], [[A1]];
-; CHECK: st.param.v2.b32 [func_retval0], {[[R0]], [[R1]]}
-; CHECK: ret;
define <2 x i32> @test_fptosi_i32(<2 x half> %a) #0 {
+; CHECK-LABEL: test_fptosi_i32(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_fptosi_i32_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.rzi.s32.f16 %r2, %rs2;
+; CHECK-NEXT: cvt.rzi.s32.f16 %r3, %rs1;
+; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r3, %r2};
+; CHECK-NEXT: ret;
%r = fptosi <2 x half> %a to <2 x i32>
ret <2 x i32> %r
}
-; CHECK-LABEL: test_fptosi_i64(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_fptosi_i64_param_0];
-; CHECK: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-DAG: cvt.rzi.s64.f16 [[R0:%rd[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.rzi.s64.f16 [[R1:%rd[0-9]+]], [[A1]];
-; CHECK: st.param.v2.b64 [func_retval0], {[[R0]], [[R1]]}
-; CHECK: ret;
define <2 x i64> @test_fptosi_i64(<2 x half> %a) #0 {
+; CHECK-LABEL: test_fptosi_i64(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_fptosi_i64_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.rzi.s64.f16 %rd1, %rs2;
+; CHECK-NEXT: cvt.rzi.s64.f16 %rd2, %rs1;
+; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd2, %rd1};
+; CHECK-NEXT: ret;
%r = fptosi <2 x half> %a to <2 x i64>
ret <2 x i64> %r
}
-; CHECK-LABEL: test_fptoui_2xi32(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_fptoui_2xi32_param_0];
-; CHECK: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-DAG: cvt.rzi.u32.f16 [[R0:%r[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.rzi.u32.f16 [[R1:%r[0-9]+]], [[A1]];
-; CHECK: st.param.v2.b32 [func_retval0], {[[R0]], [[R1]]}
-; CHECK: ret;
define <2 x i32> @test_fptoui_2xi32(<2 x half> %a) #0 {
+; CHECK-LABEL: test_fptoui_2xi32(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_fptoui_2xi32_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.rzi.u32.f16 %r2, %rs2;
+; CHECK-NEXT: cvt.rzi.u32.f16 %r3, %rs1;
+; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r3, %r2};
+; CHECK-NEXT: ret;
%r = fptoui <2 x half> %a to <2 x i32>
ret <2 x i32> %r
}
-; CHECK-LABEL: test_fptoui_2xi64(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_fptoui_2xi64_param_0];
-; CHECK: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-DAG: cvt.rzi.u64.f16 [[R0:%rd[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.rzi.u64.f16 [[R1:%rd[0-9]+]], [[A1]];
-; CHECK: st.param.v2.b64 [func_retval0], {[[R0]], [[R1]]}
-; CHECK: ret;
define <2 x i64> @test_fptoui_2xi64(<2 x half> %a) #0 {
+; CHECK-LABEL: test_fptoui_2xi64(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_fptoui_2xi64_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.rzi.u64.f16 %rd1, %rs2;
+; CHECK-NEXT: cvt.rzi.u64.f16 %rd2, %rs1;
+; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd2, %rd1};
+; CHECK-NEXT: ret;
%r = fptoui <2 x half> %a to <2 x i64>
ret <2 x i64> %r
}
-; CHECK-LABEL: test_uitofp_2xi32(
-; CHECK: ld.param.v2.u32 {[[A0:%r[0-9]+]], [[A1:%r[0-9]+]]}, [test_uitofp_2xi32_param_0];
-; CHECK-DAG: cvt.rn.f16.u32 [[R0:%rs[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.rn.f16.u32 [[R1:%rs[0-9]+]], [[A1]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_uitofp_2xi32(<2 x i32> %a) #0 {
+; CHECK-LABEL: test_uitofp_2xi32(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.v2.u32 {%r1, %r2}, [test_uitofp_2xi32_param_0];
+; CHECK-NEXT: cvt.rn.f16.u32 %rs1, %r2;
+; CHECK-NEXT: cvt.rn.f16.u32 %rs2, %r1;
+; CHECK-NEXT: mov.b32 %r3, {%rs2, %rs1};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%r = uitofp <2 x i32> %a to <2 x half>
ret <2 x half> %r
}
-; CHECK-LABEL: test_uitofp_2xi64(
-; CHECK: ld.param.v2.u64 {[[A0:%rd[0-9]+]], [[A1:%rd[0-9]+]]}, [test_uitofp_2xi64_param_0];
-; CHECK-DAG: cvt.rn.f16.u64 [[R0:%rs[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.rn.f16.u64 [[R1:%rs[0-9]+]], [[A1]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_uitofp_2xi64(<2 x i64> %a) #0 {
+; CHECK-LABEL: test_uitofp_2xi64(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.v2.u64 {%rd1, %rd2}, [test_uitofp_2xi64_param_0];
+; CHECK-NEXT: cvt.rn.f16.u64 %rs1, %rd2;
+; CHECK-NEXT: cvt.rn.f16.u64 %rs2, %rd1;
+; CHECK-NEXT: mov.b32 %r1, {%rs2, %rs1};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
%r = uitofp <2 x i64> %a to <2 x half>
ret <2 x half> %r
}
-; CHECK-LABEL: test_sitofp_2xi32(
-; CHECK: ld.param.v2.u32 {[[A0:%r[0-9]+]], [[A1:%r[0-9]+]]}, [test_sitofp_2xi32_param_0];
-; CHECK-DAG: cvt.rn.f16.s32 [[R0:%rs[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.rn.f16.s32 [[R1:%rs[0-9]+]], [[A1]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_sitofp_2xi32(<2 x i32> %a) #0 {
+; CHECK-LABEL: test_sitofp_2xi32(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.v2.u32 {%r1, %r2}, [test_sitofp_2xi32_param_0];
+; CHECK-NEXT: cvt.rn.f16.s32 %rs1, %r2;
+; CHECK-NEXT: cvt.rn.f16.s32 %rs2, %r1;
+; CHECK-NEXT: mov.b32 %r3, {%rs2, %rs1};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%r = sitofp <2 x i32> %a to <2 x half>
ret <2 x half> %r
}
-; CHECK-LABEL: test_sitofp_2xi64(
-; CHECK: ld.param.v2.u64 {[[A0:%rd[0-9]+]], [[A1:%rd[0-9]+]]}, [test_sitofp_2xi64_param_0];
-; CHECK-DAG: cvt.rn.f16.s64 [[R0:%rs[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.rn.f16.s64 [[R1:%rs[0-9]+]], [[A1]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_sitofp_2xi64(<2 x i64> %a) #0 {
+; CHECK-LABEL: test_sitofp_2xi64(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.v2.u64 {%rd1, %rd2}, [test_sitofp_2xi64_param_0];
+; CHECK-NEXT: cvt.rn.f16.s64 %rs1, %rd2;
+; CHECK-NEXT: cvt.rn.f16.s64 %rs2, %rd1;
+; CHECK-NEXT: mov.b32 %r1, {%rs2, %rs1};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
%r = sitofp <2 x i64> %a to <2 x half>
ret <2 x half> %r
}
-; CHECK-LABEL: test_uitofp_2xi32_fadd(
-; CHECK-DAG: ld.param.v2.u32 {[[A0:%r[0-9]+]], [[A1:%r[0-9]+]]}, [test_uitofp_2xi32_fadd_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_uitofp_2xi32_fadd_param_1];
-; CHECK-DAG: cvt.rn.f16.u32 [[C0:%rs[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.rn.f16.u32 [[C1:%rs[0-9]+]], [[A1]];
-; CHECK-F16-DAG: mov.b32 [[C:%r[0-9]+]], {[[C0]], [[C1]]}
-; CHECK-F16-DAG: add.rn.f16x2 [[R:%r[0-9]+]], [[B]], [[C]];
-;
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FC0:%f[0-9]+]], [[C0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FC1:%f[0-9]+]], [[C1]]
-; CHECK-NOF16-DAG: add.rn.f32 [[FR0:%f[0-9]+]], [[FB0]], [[FC0]];
-; CHECK-NOF16-DAG: add.rn.f32 [[FR1:%f[0-9]+]], [[FB1]], [[FC1]];
-; CHECK-NOF16-DAG: cvt.rn.f16.f32 [[R0:%rs[0-9]+]], [[FR0]]
-; CHECK-NOF16-DAG: cvt.rn.f16.f32 [[R1:%rs[0-9]+]], [[FR1]]
-; CHECK-NOF16: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-;
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_uitofp_2xi32_fadd(<2 x i32> %a, <2 x half> %b) #0 {
+; CHECK-F16-LABEL: test_uitofp_2xi32_fadd(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .b16 %rs<3>;
+; CHECK-F16-NEXT: .reg .b32 %r<6>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.v2.u32 {%r1, %r2}, [test_uitofp_2xi32_fadd_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r3, [test_uitofp_2xi32_fadd_param_1];
+; CHECK-F16-NEXT: cvt.rn.f16.u32 %rs1, %r2;
+; CHECK-F16-NEXT: cvt.rn.f16.u32 %rs2, %r1;
+; CHECK-F16-NEXT: mov.b32 %r4, {%rs2, %rs1};
+; CHECK-F16-NEXT: add.rn.f16x2 %r5, %r3, %r4;
+; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r5;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_uitofp_2xi32_fadd(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<7>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.v2.u32 {%r1, %r2}, [test_uitofp_2xi32_fadd_param_0];
+; CHECK-NOF16-NEXT: ld.param.b32 %r3, [test_uitofp_2xi32_fadd_param_1];
+; CHECK-NOF16-NEXT: cvt.rn.f16.u32 %rs1, %r1;
+; CHECK-NOF16-NEXT: cvt.rn.f16.u32 %rs2, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NOF16-NEXT: add.rn.f32 %f3, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs5, %f3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f4, %rs1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f5, %rs3;
+; CHECK-NOF16-NEXT: add.rn.f32 %f6, %f5, %f4;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs6, %f6;
+; CHECK-NOF16-NEXT: mov.b32 %r4, {%rs6, %rs5};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NOF16-NEXT: ret;
%c = uitofp <2 x i32> %a to <2 x half>
%r = fadd <2 x half> %b, %c
ret <2 x half> %r
}
-; CHECK-LABEL: test_sitofp_2xi32_fadd(
-; CHECK-DAG: ld.param.v2.u32 {[[A0:%r[0-9]+]], [[A1:%r[0-9]+]]}, [test_sitofp_2xi32_fadd_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_sitofp_2xi32_fadd_param_1];
-; CHECK-DAG: cvt.rn.f16.s32 [[C0:%rs[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.rn.f16.s32 [[C1:%rs[0-9]+]], [[A1]];
-;
-; CHECK-F16-DAG: mov.b32 [[C:%r[0-9]+]], {[[C0]], [[C1]]}
-; CHECK-F16-DAG: add.rn.f16x2 [[R:%r[0-9]+]], [[B]], [[C]];
-;
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FC0:%f[0-9]+]], [[C0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FC1:%f[0-9]+]], [[C1]]
-; CHECK-NOF16-DAG: add.rn.f32 [[FR0:%f[0-9]+]], [[FB0]], [[FC0]];
-; CHECK-NOF16-DAG: add.rn.f32 [[FR1:%f[0-9]+]], [[FB1]], [[FC1]];
-; CHECK-NOF16-DAG: cvt.rn.f16.f32 [[R0:%rs[0-9]+]], [[FR0]]
-; CHECK-NOF16-DAG: cvt.rn.f16.f32 [[R1:%rs[0-9]+]], [[FR1]]
-; CHECK-NOF16: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-;
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_sitofp_2xi32_fadd(<2 x i32> %a, <2 x half> %b) #0 {
+; CHECK-F16-LABEL: test_sitofp_2xi32_fadd(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .b16 %rs<3>;
+; CHECK-F16-NEXT: .reg .b32 %r<6>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.v2.u32 {%r1, %r2}, [test_sitofp_2xi32_fadd_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r3, [test_sitofp_2xi32_fadd_param_1];
+; CHECK-F16-NEXT: cvt.rn.f16.s32 %rs1, %r2;
+; CHECK-F16-NEXT: cvt.rn.f16.s32 %rs2, %r1;
+; CHECK-F16-NEXT: mov.b32 %r4, {%rs2, %rs1};
+; CHECK-F16-NEXT: add.rn.f16x2 %r5, %r3, %r4;
+; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r5;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_sitofp_2xi32_fadd(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<7>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.v2.u32 {%r1, %r2}, [test_sitofp_2xi32_fadd_param_0];
+; CHECK-NOF16-NEXT: ld.param.b32 %r3, [test_sitofp_2xi32_fadd_param_1];
+; CHECK-NOF16-NEXT: cvt.rn.f16.s32 %rs1, %r1;
+; CHECK-NOF16-NEXT: cvt.rn.f16.s32 %rs2, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NOF16-NEXT: add.rn.f32 %f3, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs5, %f3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f4, %rs1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f5, %rs3;
+; CHECK-NOF16-NEXT: add.rn.f32 %f6, %f5, %f4;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs6, %f6;
+; CHECK-NOF16-NEXT: mov.b32 %r4, {%rs6, %rs5};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NOF16-NEXT: ret;
%c = sitofp <2 x i32> %a to <2 x half>
%r = fadd <2 x half> %b, %c
ret <2 x half> %r
}
-; CHECK-LABEL: test_fptrunc_2xfloat(
-; CHECK: ld.param.v2.f32 {[[A0:%f[0-9]+]], [[A1:%f[0-9]+]]}, [test_fptrunc_2xfloat_param_0];
-; CHECK-DAG: cvt.rn.f16.f32 [[R0:%rs[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.rn.f16.f32 [[R1:%rs[0-9]+]], [[A1]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_fptrunc_2xfloat(<2 x float> %a) #0 {
+; CHECK-LABEL: test_fptrunc_2xfloat(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .f32 %f<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.v2.f32 {%f1, %f2}, [test_fptrunc_2xfloat_param_0];
+; CHECK-NEXT: cvt.rn.f16.f32 %rs1, %f2;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs2, %f1;
+; CHECK-NEXT: mov.b32 %r1, {%rs2, %rs1};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
%r = fptrunc <2 x float> %a to <2 x half>
ret <2 x half> %r
}
-; CHECK-LABEL: test_fptrunc_2xdouble(
-; CHECK: ld.param.v2.f64 {[[A0:%fd[0-9]+]], [[A1:%fd[0-9]+]]}, [test_fptrunc_2xdouble_param_0];
-; CHECK-DAG: cvt.rn.f16.f64 [[R0:%rs[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.rn.f16.f64 [[R1:%rs[0-9]+]], [[A1]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_fptrunc_2xdouble(<2 x double> %a) #0 {
+; CHECK-LABEL: test_fptrunc_2xdouble(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .f64 %fd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.v2.f64 {%fd1, %fd2}, [test_fptrunc_2xdouble_param_0];
+; CHECK-NEXT: cvt.rn.f16.f64 %rs1, %fd2;
+; CHECK-NEXT: cvt.rn.f16.f64 %rs2, %fd1;
+; CHECK-NEXT: mov.b32 %r1, {%rs2, %rs1};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
%r = fptrunc <2 x double> %a to <2 x half>
ret <2 x half> %r
}
-; CHECK-LABEL: test_fpext_2xfloat(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_fpext_2xfloat_param_0];
-; CHECK: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-DAG: cvt.f32.f16 [[R0:%f[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.f32.f16 [[R1:%f[0-9]+]], [[A1]];
-; CHECK-NEXT: st.param.v2.f32 [func_retval0], {[[R0]], [[R1]]};
-; CHECK: ret;
define <2 x float> @test_fpext_2xfloat(<2 x half> %a) #0 {
+; CHECK-LABEL: test_fpext_2xfloat(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .f32 %f<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_fpext_2xfloat_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NEXT: cvt.f32.f16 %f2, %rs1;
+; CHECK-NEXT: st.param.v2.f32 [func_retval0], {%f2, %f1};
+; CHECK-NEXT: ret;
%r = fpext <2 x half> %a to <2 x float>
ret <2 x float> %r
}
-; CHECK-LABEL: test_fpext_2xdouble(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_fpext_2xdouble_param_0];
-; CHECK: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-DAG: cvt.f64.f16 [[R0:%fd[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.f64.f16 [[R1:%fd[0-9]+]], [[A1]];
-; CHECK-NEXT: st.param.v2.f64 [func_retval0], {[[R0]], [[R1]]};
-; CHECK: ret;
define <2 x double> @test_fpext_2xdouble(<2 x half> %a) #0 {
+; CHECK-LABEL: test_fpext_2xdouble(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .f64 %fd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_fpext_2xdouble_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.f64.f16 %fd1, %rs2;
+; CHECK-NEXT: cvt.f64.f16 %fd2, %rs1;
+; CHECK-NEXT: st.param.v2.f64 [func_retval0], {%fd2, %fd1};
+; CHECK-NEXT: ret;
%r = fpext <2 x half> %a to <2 x double>
ret <2 x double> %r
}
-; CHECK-LABEL: test_bitcast_2xhalf_to_2xi16(
-; CHECK: ld.param.u32 [[A:%r[0-9]+]], [test_bitcast_2xhalf_to_2xi16_param_0];
-; CHECK: st.param.b32 [func_retval0], [[A]]
-; CHECK: ret;
define <2 x i16> @test_bitcast_2xhalf_to_2xi16(<2 x half> %a) #0 {
+; CHECK-LABEL: test_bitcast_2xhalf_to_2xi16(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.u32 %r2, [test_bitcast_2xhalf_to_2xi16_param_0];
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%r = bitcast <2 x half> %a to <2 x i16>
ret <2 x i16> %r
}
-; CHECK-LABEL: test_bitcast_2xi16_to_2xhalf(
-; CHECK: ld.param.u32 [[R:%r[0-9]+]], [test_bitcast_2xi16_to_2xhalf_param_0];
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_bitcast_2xi16_to_2xhalf(<2 x i16> %a) #0 {
+; CHECK-LABEL: test_bitcast_2xi16_to_2xhalf(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.u32 %r2, [test_bitcast_2xi16_to_2xhalf_param_0];
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%r = bitcast <2 x i16> %a to <2 x half>
ret <2 x half> %r
}
-; CHECK-LABEL: test_bitcast_float_to_2xhalf(
-; CHECK: ld.param.f32 [[AF1:%f[0-9]+]], [test_bitcast_float_to_2xhalf_param_0];
-; CHECK: mov.b32 [[R:%r[0-9]+]], [[AF1]];
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_bitcast_float_to_2xhalf(float %a) #0 {
+; CHECK-LABEL: test_bitcast_float_to_2xhalf(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .f32 %f<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.f32 %f1, [test_bitcast_float_to_2xhalf_param_0];
+; CHECK-NEXT: mov.b32 %r1, %f1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
%r = bitcast float %a to <2 x half>
ret <2 x half> %r
}
-; CHECK-LABEL: test_bitcast_2xhalf_to_float(
-; CHECK: ld.param.u32 [[R:%r[0-9]+]], [test_bitcast_2xhalf_to_float_param_0];
-; CHECK: mov.b32 [[AF1:%f[0-9]+]], [[R]];
-; CHECK: st.param.f32 [func_retval0], [[AF1]];
-; CHECK: ret;
define float @test_bitcast_2xhalf_to_float(<2 x half> %a) #0 {
+; CHECK-LABEL: test_bitcast_2xhalf_to_float(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-NEXT: .reg .f32 %f<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.u32 %r2, [test_bitcast_2xhalf_to_float_param_0];
+; CHECK-NEXT: mov.b32 %f1, %r2;
+; CHECK-NEXT: st.param.f32 [func_retval0], %f1;
+; CHECK-NEXT: ret;
%r = bitcast <2 x half> %a to float
ret float %r
}
@@ -1053,19 +1693,25 @@ declare <2 x half> @llvm.round.f16(<2 x half> %a) #0
declare <2 x half> @llvm.roundeven.f16(<2 x half> %a) #0
declare <2 x half> @llvm.fmuladd.f16(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0
-; CHECK-LABEL: test_sqrt(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_sqrt_param_0];
-; CHECK: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-DAG: cvt.f32.f16 [[AF0:%f[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.f32.f16 [[AF1:%f[0-9]+]], [[A1]];
-; CHECK-DAG: sqrt.rn.f32 [[RF0:%f[0-9]+]], [[AF0]];
-; CHECK-DAG: sqrt.rn.f32 [[RF1:%f[0-9]+]], [[AF1]];
-; CHECK-DAG: cvt.rn.f16.f32 [[R0:%rs[0-9]+]], [[RF0]];
-; CHECK-DAG: cvt.rn.f16.f32 [[R1:%rs[0-9]+]], [[RF1]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_sqrt(<2 x half> %a) #0 {
+; CHECK-LABEL: test_sqrt(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-NEXT: .reg .f32 %f<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_sqrt_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NEXT: sqrt.rn.f32 %f2, %f1;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs3, %f2;
+; CHECK-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-NEXT: sqrt.rn.f32 %f4, %f3;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs4, %f4;
+; CHECK-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%r = call <2 x half> @llvm.sqrt.f16(<2 x half> %a)
ret <2 x half> %r
}
@@ -1077,36 +1723,48 @@ define <2 x half> @test_sqrt(<2 x half> %a) #0 {
; ret <2 x half> %r
;}
-; CHECK-LABEL: test_sin(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_sin_param_0];
-; CHECK: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-DAG: cvt.f32.f16 [[AF0:%f[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.f32.f16 [[AF1:%f[0-9]+]], [[A1]];
-; CHECK-DAG: sin.approx.f32 [[RF0:%f[0-9]+]], [[AF0]];
-; CHECK-DAG: sin.approx.f32 [[RF1:%f[0-9]+]], [[AF1]];
-; CHECK-DAG: cvt.rn.f16.f32 [[R0:%rs[0-9]+]], [[RF0]];
-; CHECK-DAG: cvt.rn.f16.f32 [[R1:%rs[0-9]+]], [[RF1]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_sin(<2 x half> %a) #0 #1 {
+; CHECK-LABEL: test_sin(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-NEXT: .reg .f32 %f<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_sin_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NEXT: sin.approx.f32 %f2, %f1;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs3, %f2;
+; CHECK-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-NEXT: sin.approx.f32 %f4, %f3;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs4, %f4;
+; CHECK-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%r = call <2 x half> @llvm.sin.f16(<2 x half> %a)
ret <2 x half> %r
}
-; CHECK-LABEL: test_cos(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_cos_param_0];
-; CHECK: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-DAG: cvt.f32.f16 [[AF0:%f[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.f32.f16 [[AF1:%f[0-9]+]], [[A1]];
-; CHECK-DAG: cos.approx.f32 [[RF0:%f[0-9]+]], [[AF0]];
-; CHECK-DAG: cos.approx.f32 [[RF1:%f[0-9]+]], [[AF1]];
-; CHECK-DAG: cvt.rn.f16.f32 [[R0:%rs[0-9]+]], [[RF0]];
-; CHECK-DAG: cvt.rn.f16.f32 [[R1:%rs[0-9]+]], [[RF1]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_cos(<2 x half> %a) #0 #1 {
+; CHECK-LABEL: test_cos(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-NEXT: .reg .f32 %f<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_cos_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NEXT: cos.approx.f32 %f2, %f1;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs3, %f2;
+; CHECK-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-NEXT: cos.approx.f32 %f4, %f3;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs4, %f4;
+; CHECK-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%r = call <2 x half> @llvm.cos.f16(<2 x half> %a)
ret <2 x half> %r
}
@@ -1153,355 +1811,579 @@ define <2 x half> @test_cos(<2 x half> %a) #0 #1 {
; ret <2 x half> %r
;}
-; CHECK-LABEL: test_fma(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fma_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fma_param_1];
-; CHECK-DAG: ld.param.b32 [[C:%r[0-9]+]], [test_fma_param_2];
-;
-; CHECK-F16: fma.rn.f16x2 [[R:%r[0-9]+]], [[A]], [[B]], [[C]];
-;
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: mov.b32 {[[C0:%rs[0-9]+]], [[C1:%rs[0-9]+]]}, [[C]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FC0:%f[0-9]+]], [[C0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FC0:%f[0-9]+]], [[C0]]
-; CHECK-NOF16-DAG: fma.rn.f32 [[FR0:%f[0-9]+]], [[FA0]], [[FB0]], [[FC0]];
-; CHECK-NOF16-DAG: fma.rn.f32 [[FR1:%f[0-9]+]], [[FA1]], [[FB1]], [[FC1]];
-; CHECK-NOF16-DAG: cvt.rn.f16.f32 [[R0:%rs[0-9]+]], [[FR0]]
-; CHECK-NOF16-DAG: cvt.rn.f16.f32 [[R1:%rs[0-9]+]], [[FR1]]
-; CHECK-NOF16: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret
+
define <2 x half> @test_fma(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
+; CHECK-F16-LABEL: test_fma(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .b32 %r<5>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r3, [test_fma_param_2];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fma_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fma_param_0];
+; CHECK-F16-NEXT: fma.rn.f16x2 %r4, %r1, %r2, %r3;
+; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fma(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .b16 %rs<9>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<9>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r3, [test_fma_param_2];
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fma_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fma_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NOF16-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f3, %rs6;
+; CHECK-NOF16-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs7, %f4;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f5, %rs1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f6, %rs3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f7, %rs5;
+; CHECK-NOF16-NEXT: fma.rn.f32 %f8, %f7, %f6, %f5;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs8, %f8;
+; CHECK-NOF16-NEXT: mov.b32 %r4, {%rs8, %rs7};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NOF16-NEXT: ret;
%r = call <2 x half> @llvm.fma.f16(<2 x half> %a, <2 x half> %b, <2 x half> %c)
ret <2 x half> %r
}
-; CHECK-LABEL: test_fabs(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_fabs_param_0];
-; CHECK-NOF16: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[AF0:%f[0-9]+]], [[A0]];
-; CHECK-NOF16-DAG: cvt.f32.f16 [[AF1:%f[0-9]+]], [[A1]];
-; CHECK-NOF16-DAG: abs.f32 [[RF0:%f[0-9]+]], [[AF0]];
-; CHECK-NOF16-DAG: abs.f32 [[RF1:%f[0-9]+]], [[AF1]];
-; CHECK-NOF16-DAG: cvt.rn.f16.f32 [[R0:%rs[0-9]+]], [[RF0]];
-; CHECK-NOF16-DAG: cvt.rn.f16.f32 [[R1:%rs[0-9]+]], [[RF1]];
-; CHECK-NOF16: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK-F16: and.b32 [[R:%r[0-9]+]], [[A]], 2147450879;
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_fabs(<2 x half> %a) #0 {
+; CHECK-F16-LABEL: test_fabs(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .b32 %r<5>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fabs_param_0];
+; CHECK-F16-NEXT: and.b32 %r3, %r1, 2147450879;
+; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fabs(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .b16 %rs<5>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<5>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fabs_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: abs.f32 %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs3, %f2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f3, %rs1;
+; CHECK-NOF16-NEXT: abs.f32 %f4, %f3;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs4, %f4;
+; CHECK-NOF16-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NOF16-NEXT: ret;
%r = call <2 x half> @llvm.fabs.f16(<2 x half> %a)
ret <2 x half> %r
}
-; CHECK-LABEL: test_minnum(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_minnum_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_minnum_param_1];
-; CHECK-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-DAG: cvt.f32.f16 [[AF0:%f[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.f32.f16 [[AF1:%f[0-9]+]], [[A1]];
-; CHECK-DAG: cvt.f32.f16 [[BF0:%f[0-9]+]], [[B0]];
-; CHECK-DAG: cvt.f32.f16 [[BF1:%f[0-9]+]], [[B1]];
-; CHECK-DAG: min.f32 [[RF0:%f[0-9]+]], [[AF0]], [[BF0]];
-; CHECK-DAG: min.f32 [[RF1:%f[0-9]+]], [[AF1]], [[BF1]];
-; CHECK-DAG: cvt.rn.f16.f32 [[R0:%rs[0-9]+]], [[RF0]];
-; CHECK-DAG: cvt.rn.f16.f32 [[R1:%rs[0-9]+]], [[RF1]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_minnum(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-LABEL: test_minnum(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<7>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-NEXT: .reg .f32 %f<7>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r2, [test_minnum_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_minnum_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NEXT: min.f32 %f3, %f2, %f1;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs5, %f3;
+; CHECK-NEXT: cvt.f32.f16 %f4, %rs1;
+; CHECK-NEXT: cvt.f32.f16 %f5, %rs3;
+; CHECK-NEXT: min.f32 %f6, %f5, %f4;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs6, %f6;
+; CHECK-NEXT: mov.b32 %r3, {%rs6, %rs5};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%r = call <2 x half> @llvm.minnum.f16(<2 x half> %a, <2 x half> %b)
ret <2 x half> %r
}
-; CHECK-LABEL: test_maxnum(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_maxnum_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_maxnum_param_1];
-; CHECK-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-DAG: cvt.f32.f16 [[AF0:%f[0-9]+]], [[A0]];
-; CHECK-DAG: cvt.f32.f16 [[AF1:%f[0-9]+]], [[A1]];
-; CHECK-DAG: cvt.f32.f16 [[BF0:%f[0-9]+]], [[B0]];
-; CHECK-DAG: cvt.f32.f16 [[BF1:%f[0-9]+]], [[B1]];
-; CHECK-DAG: max.f32 [[RF0:%f[0-9]+]], [[AF0]], [[BF0]];
-; CHECK-DAG: max.f32 [[RF1:%f[0-9]+]], [[AF1]], [[BF1]];
-; CHECK-DAG: cvt.rn.f16.f32 [[R0:%rs[0-9]+]], [[RF0]];
-; CHECK-DAG: cvt.rn.f16.f32 [[R1:%rs[0-9]+]], [[RF1]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_maxnum(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-LABEL: test_maxnum(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<7>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-NEXT: .reg .f32 %f<7>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r2, [test_maxnum_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_maxnum_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; CHECK-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NEXT: max.f32 %f3, %f2, %f1;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs5, %f3;
+; CHECK-NEXT: cvt.f32.f16 %f4, %rs1;
+; CHECK-NEXT: cvt.f32.f16 %f5, %rs3;
+; CHECK-NEXT: max.f32 %f6, %f5, %f4;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs6, %f6;
+; CHECK-NEXT: mov.b32 %r3, {%rs6, %rs5};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%r = call <2 x half> @llvm.maxnum.f16(<2 x half> %a, <2 x half> %b)
ret <2 x half> %r
}
-; CHECK-LABEL: test_copysign(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_copysign_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_copysign_param_1];
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: and.b16 [[AX0:%rs[0-9]+]], [[A0]], 32767;
-; CHECK-NOF16-DAG: and.b16 [[AX1:%rs[0-9]+]], [[A1]], 32767;
-; CHECK-NOF16-DAG: and.b16 [[BX0:%rs[0-9]+]], [[B0]], -32768;
-; CHECK-NOF16-DAG: and.b16 [[BX1:%rs[0-9]+]], [[B1]], -32768;
-; CHECK-NOF16-DAG: or.b16 [[R0:%rs[0-9]+]], [[AX0]], [[BX0]];
-; CHECK-NOF16-DAG: or.b16 [[R1:%rs[0-9]+]], [[AX1]], [[BX1]];
-; CHECK-NOF16-DAG: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK-F16-DAG: and.b32 [[R0:%r[0-9]+]], [[B]], -2147450880;
-; CHECK-F16-DAG: and.b32 [[R1:%r[0-9]+]], [[A]], 2147450879;
-; CHECK-F16-DAG: or.b32 [[R:%r[0-9]+]], [[R1]], [[R0]]
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_copysign(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-F16-LABEL: test_copysign(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .b32 %r<9>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_copysign_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_copysign_param_0];
+; CHECK-F16-NEXT: and.b32 %r4, %r2, -2147450880;
+; CHECK-F16-NEXT: and.b32 %r6, %r1, 2147450879;
+; CHECK-F16-NEXT: or.b32 %r7, %r6, %r4;
+; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r7;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_copysign(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .b16 %rs<17>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<4>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_copysign_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_copysign_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NOF16-NEXT: and.b16 %rs4, %rs2, -32768;
+; CHECK-NOF16-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-NOF16-NEXT: and.b16 %rs8, %rs6, 32767;
+; CHECK-NOF16-NEXT: or.b16 %rs9, %rs8, %rs4;
+; CHECK-NOF16-NEXT: and.b16 %rs12, %rs1, -32768;
+; CHECK-NOF16-NEXT: and.b16 %rs14, %rs5, 32767;
+; CHECK-NOF16-NEXT: or.b16 %rs15, %rs14, %rs12;
+; CHECK-NOF16-NEXT: mov.b32 %r3, {%rs15, %rs9};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NOF16-NEXT: ret;
%r = call <2 x half> @llvm.copysign.f16(<2 x half> %a, <2 x half> %b)
ret <2 x half> %r
}
-; CHECK-LABEL: test_copysign_f32(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_copysign_f32_param_0];
-; CHECK-DAG: ld.param.v2.f32 {[[B0:%f[0-9]+]], [[B1:%f[0-9]+]]}, [test_copysign_f32_param_1];
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b32 [[BI0:%r[0-9]+]], [[B0]];
-; CHECK-NOF16-DAG: mov.b32 [[BI1:%r[0-9]+]], [[B1]];
-; CHECK-NOF16-DAG: and.b16 [[AI0:%rs[0-9]+]], [[A0]], 32767;
-; CHECK-NOF16-DAG: and.b16 [[AI1:%rs[0-9]+]], [[A1]], 32767;
-; CHECK-NOF16-DAG: and.b32 [[BX0:%r[0-9]+]], [[BI0]], -2147483648;
-; CHECK-NOF16-DAG: and.b32 [[BX1:%r[0-9]+]], [[BI1]], -2147483648;
-; CHECK-NOF16-DAG: mov.b32 {tmp, [[BZ0:%rs[0-9]+]]}, [[BX0]]; }
-; CHECK-NOF16-DAG: mov.b32 {tmp, [[BZ1:%rs[0-9]+]]}, [[BX1]]; }
-; CHECK-NOF16-DAG: or.b16 [[R0:%rs[0-9]+]], [[AI0]], [[BZ0]];
-; CHECK-NOF16-DAG: or.b16 [[R1:%rs[0-9]+]], [[AI1]], [[BZ1]];
-; CHECK-NOF16-DAG: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK-F16-DAG: cvt.rn.f16.f32 [[R0:%rs[0-9]+]], [[B1]];
-; CHECK-F16-DAG: cvt.rn.f16.f32 [[R1:%rs[0-9]+]], [[B0]];
-; CHECK-F16-DAG: mov.b32 [[R2:%r[0-9]+]], {[[R1]], [[R0]]};
-; CHECK-F16-DAG: and.b32 [[R3:%r[0-9]+]], [[R2]], -2147450880;
-; CHECK-F16-DAG: and.b32 [[R4:%r[0-9]+]], [[A]], 2147450879;
-; CHECK-F16-DAG: or.b32 [[R:%r[0-9]+]], [[R4]], [[R3]]
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_copysign_f32(<2 x half> %a, <2 x float> %b) #0 {
+; CHECK-F16-LABEL: test_copysign_f32(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .b16 %rs<3>;
+; CHECK-F16-NEXT: .reg .b32 %r<9>;
+; CHECK-F16-NEXT: .reg .f32 %f<3>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.v2.f32 {%f1, %f2}, [test_copysign_f32_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_copysign_f32_param_0];
+; CHECK-F16-NEXT: cvt.rn.f16.f32 %rs1, %f2;
+; CHECK-F16-NEXT: cvt.rn.f16.f32 %rs2, %f1;
+; CHECK-F16-NEXT: mov.b32 %r2, {%rs2, %rs1};
+; CHECK-F16-NEXT: and.b32 %r4, %r2, -2147450880;
+; CHECK-F16-NEXT: and.b32 %r6, %r1, 2147450879;
+; CHECK-F16-NEXT: or.b32 %r7, %r6, %r4;
+; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r7;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_copysign_f32(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .b16 %rs<13>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<3>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.v2.f32 {%f1, %f2}, [test_copysign_f32_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_copysign_f32_param_0];
+; CHECK-NOF16-NEXT: mov.b32 %r2, %f2;
+; CHECK-NOF16-NEXT: and.b32 %r3, %r2, -2147483648;
+; CHECK-NOF16-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r3; }
+; CHECK-NOF16-NEXT: mov.b32 {%rs2, %rs3}, %r1;
+; CHECK-NOF16-NEXT: and.b16 %rs5, %rs3, 32767;
+; CHECK-NOF16-NEXT: or.b16 %rs6, %rs5, %rs1;
+; CHECK-NOF16-NEXT: mov.b32 %r4, %f1;
+; CHECK-NOF16-NEXT: and.b32 %r5, %r4, -2147483648;
+; CHECK-NOF16-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs8}, %r5; }
+; CHECK-NOF16-NEXT: and.b16 %rs10, %rs2, 32767;
+; CHECK-NOF16-NEXT: or.b16 %rs11, %rs10, %rs8;
+; CHECK-NOF16-NEXT: mov.b32 %r6, {%rs11, %rs6};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-NOF16-NEXT: ret;
%tb = fptrunc <2 x float> %b to <2 x half>
%r = call <2 x half> @llvm.copysign.f16(<2 x half> %a, <2 x half> %tb)
ret <2 x half> %r
}
-; CHECK-LABEL: test_copysign_f64(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_copysign_f64_param_0];
-; CHECK-DAG: ld.param.v2.f64 {[[B0:%fd[0-9]+]], [[B1:%fd[0-9]+]]}, [test_copysign_f64_param_1];
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b64 [[BI0:%rd[0-9]+]], [[B0]];
-; CHECK-NOF16-DAG: mov.b64 [[BI1:%rd[0-9]+]], [[B1]];
-; CHECK-NOF16-DAG: and.b16 [[AI0:%rs[0-9]+]], [[A0]], 32767;
-; CHECK-NOF16-DAG: and.b16 [[AI1:%rs[0-9]+]], [[A1]], 32767;
-; CHECK-NOF16-DAG: and.b64 [[BX0:%rd[0-9]+]], [[BI0]], -9223372036854775808;
-; CHECK-NOF16-DAG: and.b64 [[BX1:%rd[0-9]+]], [[BI1]], -9223372036854775808;
-; CHECK-NOF16-DAG: shr.u64 [[BY0:%rd[0-9]+]], [[BX0]], 48;
-; CHECK-NOF16-DAG: shr.u64 [[BY1:%rd[0-9]+]], [[BX1]], 48;
-; CHECK-NOF16-DAG: cvt.u16.u64 [[BZ0:%rs[0-9]+]], [[BY0]];
-; CHECK-NOF16-DAG: cvt.u16.u64 [[BZ1:%rs[0-9]+]], [[BY1]];
-; CHECK-NOF16-DAG: or.b16 [[R0:%rs[0-9]+]], [[AI0]], [[BZ0]];
-; CHECK-NOF16-DAG: or.b16 [[R1:%rs[0-9]+]], [[AI1]], [[BZ1]];
-; CHECK-NOF16-DAG: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK-F16-DAG: cvt.rn.f16.f64 [[R0:%rs[0-9]+]], [[B1]];
-; CHECK-F16-DAG: cvt.rn.f16.f64 [[R1:%rs[0-9]+]], [[B0]];
-; CHECK-F16-DAG: mov.b32 [[R2:%r[0-9]+]], {[[R1]], [[R0]]};
-; CHECK-F16-DAG: and.b32 [[R3:%r[0-9]+]], [[R2]], -2147450880;
-; CHECK-F16-DAG: and.b32 [[R4:%r[0-9]+]], [[A]], 2147450879;
-; CHECK-F16-DAG: or.b32 [[R:%r[0-9]+]], [[R4]], [[R3]];
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_copysign_f64(<2 x half> %a, <2 x double> %b) #0 {
+; CHECK-F16-LABEL: test_copysign_f64(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .b16 %rs<3>;
+; CHECK-F16-NEXT: .reg .b32 %r<9>;
+; CHECK-F16-NEXT: .reg .f64 %fd<3>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.v2.f64 {%fd1, %fd2}, [test_copysign_f64_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_copysign_f64_param_0];
+; CHECK-F16-NEXT: cvt.rn.f16.f64 %rs1, %fd2;
+; CHECK-F16-NEXT: cvt.rn.f16.f64 %rs2, %fd1;
+; CHECK-F16-NEXT: mov.b32 %r2, {%rs2, %rs1};
+; CHECK-F16-NEXT: and.b32 %r4, %r2, -2147450880;
+; CHECK-F16-NEXT: and.b32 %r6, %r1, 2147450879;
+; CHECK-F16-NEXT: or.b32 %r7, %r6, %r4;
+; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r7;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_copysign_f64(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .b16 %rs<13>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF16-NEXT: .reg .b64 %rd<7>;
+; CHECK-NOF16-NEXT: .reg .f64 %fd<3>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.v2.f64 {%fd1, %fd2}, [test_copysign_f64_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_copysign_f64_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NOF16-NEXT: and.b16 %rs4, %rs2, 32767;
+; CHECK-NOF16-NEXT: mov.b64 %rd1, %fd2;
+; CHECK-NOF16-NEXT: and.b64 %rd2, %rd1, -9223372036854775808;
+; CHECK-NOF16-NEXT: shr.u64 %rd3, %rd2, 48;
+; CHECK-NOF16-NEXT: cvt.u16.u64 %rs5, %rd3;
+; CHECK-NOF16-NEXT: or.b16 %rs6, %rs4, %rs5;
+; CHECK-NOF16-NEXT: and.b16 %rs9, %rs1, 32767;
+; CHECK-NOF16-NEXT: mov.b64 %rd4, %fd1;
+; CHECK-NOF16-NEXT: and.b64 %rd5, %rd4, -9223372036854775808;
+; CHECK-NOF16-NEXT: shr.u64 %rd6, %rd5, 48;
+; CHECK-NOF16-NEXT: cvt.u16.u64 %rs10, %rd6;
+; CHECK-NOF16-NEXT: or.b16 %rs11, %rs9, %rs10;
+; CHECK-NOF16-NEXT: mov.b32 %r2, {%rs11, %rs6};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NOF16-NEXT: ret;
%tb = fptrunc <2 x double> %b to <2 x half>
%r = call <2 x half> @llvm.copysign.f16(<2 x half> %a, <2 x half> %tb)
ret <2 x half> %r
}
-; CHECK-LABEL: test_copysign_extended(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_copysign_extended_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_copysign_extended_param_1];
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: and.b16 [[AX0:%rs[0-9]+]], [[A0]], 32767;
-; CHECK-NOF16-DAG: and.b16 [[AX1:%rs[0-9]+]], [[A1]], 32767;
-; CHECK-NOF16-DAG: and.b16 [[BX0:%rs[0-9]+]], [[B0]], -32768;
-; CHECK-NOF16-DAG: and.b16 [[BX1:%rs[0-9]+]], [[B1]], -32768;
-; CHECK-NOF16-DAG: or.b16 [[R0:%rs[0-9]+]], [[AX0]], [[BX0]];
-; CHECK-NOF16-DAG: or.b16 [[R1:%rs[0-9]+]], [[AX1]], [[BX1]];
-; CHECK-NOF16-DAG: cvt.f32.f16 [[XR0:%f[0-9]+]], [[R0]];
-; CHECK-NOF16-DAG: cvt.f32.f16 [[XR1:%f[0-9]+]], [[R1]];
-; CHECK-F16-DAG: and.b32 [[R0:%r[0-9]+]], [[B]], -2147450880;
-; CHECK-F16-DAG: and.b32 [[R1:%r[0-9]+]], [[A]], 2147450879;
-; CHECK-F16-DAG: or.b32 [[R2:%r[0-9]+]], [[R1]], [[R0]]
-; CHECK-F16-DAG: mov.b32 {[[R3:%rs[0-9]+]], [[R4:%rs[0-9]+]]}, [[R2]]
-; CHECK-F16-DAG: cvt.f32.f16 [[XR0:%f[0-9]+]], [[R3]]
-; CHECK-F16-DAG: cvt.f32.f16 [[XR1:%f[0-9]+]], [[R4]]
-; CHECK: st.param.v2.f32 [func_retval0], {[[XR0]], [[XR1]]};
-; CHECK: ret;
define <2 x float> @test_copysign_extended(<2 x half> %a, <2 x half> %b) #0 {
+; CHECK-F16-LABEL: test_copysign_extended(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .b16 %rs<3>;
+; CHECK-F16-NEXT: .reg .b32 %r<9>;
+; CHECK-F16-NEXT: .reg .f32 %f<3>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_copysign_extended_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_copysign_extended_param_0];
+; CHECK-F16-NEXT: and.b32 %r4, %r2, -2147450880;
+; CHECK-F16-NEXT: and.b32 %r6, %r1, 2147450879;
+; CHECK-F16-NEXT: or.b32 %r7, %r6, %r4;
+; CHECK-F16-NEXT: mov.b32 {%rs1, %rs2}, %r7;
+; CHECK-F16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-F16-NEXT: cvt.f32.f16 %f2, %rs1;
+; CHECK-F16-NEXT: st.param.v2.f32 [func_retval0], {%f2, %f1};
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_copysign_extended(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .b16 %rs<17>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<3>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_copysign_extended_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_copysign_extended_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; CHECK-NOF16-NEXT: and.b16 %rs4, %rs1, -32768;
+; CHECK-NOF16-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-NOF16-NEXT: and.b16 %rs8, %rs5, 32767;
+; CHECK-NOF16-NEXT: or.b16 %rs9, %rs8, %rs4;
+; CHECK-NOF16-NEXT: and.b16 %rs12, %rs2, -32768;
+; CHECK-NOF16-NEXT: and.b16 %rs14, %rs6, 32767;
+; CHECK-NOF16-NEXT: or.b16 %rs15, %rs14, %rs12;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs15;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs9;
+; CHECK-NOF16-NEXT: st.param.v2.f32 [func_retval0], {%f2, %f1};
+; CHECK-NOF16-NEXT: ret;
%r = call <2 x half> @llvm.copysign.f16(<2 x half> %a, <2 x half> %b)
%xr = fpext <2 x half> %r to <2 x float>
ret <2 x float> %xr
}
-; CHECK-LABEL: test_floor(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_floor_param_0];
-; CHECK-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]];
-; CHECK-DAG: cvt.rmi.f16.f16 [[R1:%rs[0-9]+]], [[A1]];
-; CHECK-DAG: cvt.rmi.f16.f16 [[R0:%rs[0-9]+]], [[A0]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_floor(<2 x half> %a) #0 {
+; CHECK-LABEL: test_floor(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_floor_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.rmi.f16.f16 %rs3, %rs2;
+; CHECK-NEXT: cvt.rmi.f16.f16 %rs4, %rs1;
+; CHECK-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%r = call <2 x half> @llvm.floor.f16(<2 x half> %a)
ret <2 x half> %r
}
-; CHECK-LABEL: test_ceil(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_ceil_param_0];
-; CHECK-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]];
-; CHECK-DAG: cvt.rpi.f16.f16 [[R1:%rs[0-9]+]], [[A1]];
-; CHECK-DAG: cvt.rpi.f16.f16 [[R0:%rs[0-9]+]], [[A0]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_ceil(<2 x half> %a) #0 {
+; CHECK-LABEL: test_ceil(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_ceil_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.rpi.f16.f16 %rs3, %rs2;
+; CHECK-NEXT: cvt.rpi.f16.f16 %rs4, %rs1;
+; CHECK-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%r = call <2 x half> @llvm.ceil.f16(<2 x half> %a)
ret <2 x half> %r
}
-; CHECK-LABEL: test_trunc(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_trunc_param_0];
-; CHECK-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]];
-; CHECK-DAG: cvt.rzi.f16.f16 [[R1:%rs[0-9]+]], [[A1]];
-; CHECK-DAG: cvt.rzi.f16.f16 [[R0:%rs[0-9]+]], [[A0]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_trunc(<2 x half> %a) #0 {
+; CHECK-LABEL: test_trunc(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_trunc_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.rzi.f16.f16 %rs3, %rs2;
+; CHECK-NEXT: cvt.rzi.f16.f16 %rs4, %rs1;
+; CHECK-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%r = call <2 x half> @llvm.trunc.f16(<2 x half> %a)
ret <2 x half> %r
}
-; CHECK-LABEL: test_rint(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_rint_param_0];
-; CHECK-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]];
-; CHECK-DAG: cvt.rni.f16.f16 [[R1:%rs[0-9]+]], [[A1]];
-; CHECK-DAG: cvt.rni.f16.f16 [[R0:%rs[0-9]+]], [[A0]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_rint(<2 x half> %a) #0 {
+; CHECK-LABEL: test_rint(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_rint_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.rni.f16.f16 %rs3, %rs2;
+; CHECK-NEXT: cvt.rni.f16.f16 %rs4, %rs1;
+; CHECK-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%r = call <2 x half> @llvm.rint.f16(<2 x half> %a)
ret <2 x half> %r
}
-; CHECK-LABEL: test_nearbyint(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_nearbyint_param_0];
-; CHECK-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]];
-; CHECK-DAG: cvt.rni.f16.f16 [[R1:%rs[0-9]+]], [[A1]];
-; CHECK-DAG: cvt.rni.f16.f16 [[R0:%rs[0-9]+]], [[A0]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_nearbyint(<2 x half> %a) #0 {
+; CHECK-LABEL: test_nearbyint(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_nearbyint_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.rni.f16.f16 %rs3, %rs2;
+; CHECK-NEXT: cvt.rni.f16.f16 %rs4, %rs1;
+; CHECK-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%r = call <2 x half> @llvm.nearbyint.f16(<2 x half> %a)
ret <2 x half> %r
}
-; CHECK-LABEL: test_roundeven(
-; CHECK: ld.param.b32 [[A:%r[0-9]+]], [test_roundeven_param_0];
-; CHECK-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]];
-; CHECK-DAG: cvt.rni.f16.f16 [[R1:%rs[0-9]+]], [[A1]];
-; CHECK-DAG: cvt.rni.f16.f16 [[R0:%rs[0-9]+]], [[A0]];
-; CHECK: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_roundeven(<2 x half> %a) #0 {
+; CHECK-LABEL: test_roundeven(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_roundeven_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.rni.f16.f16 %rs3, %rs2;
+; CHECK-NEXT: cvt.rni.f16.f16 %rs4, %rs1;
+; CHECK-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%r = call <2 x half> @llvm.roundeven.f16(<2 x half> %a)
ret <2 x half> %r
}
-; CHECK-LABEL: test_round(
-; CHECK: ld.param.b32 {{.*}}, [test_round_param_0];
; check the use of sign mask and 0.5 to implement round
-; CHECK: and.b32 [[R1:%r[0-9]+]], {{.*}}, -2147483648;
-; CHECK: or.b32 {{.*}}, [[R1]], 1056964608;
-; CHECK: and.b32 [[R2:%r[0-9]+]], {{.*}}, -2147483648;
-; CHECK: or.b32 {{.*}}, [[R2]], 1056964608;
-; CHECK: st.param.b32 [func_retval0], {{.*}};
-; CHECK: ret;
define <2 x half> @test_round(<2 x half> %a) #0 {
+; CHECK-LABEL: test_round(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<5>;
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-NEXT: .reg .b32 %r<9>;
+; CHECK-NEXT: .reg .f32 %f<17>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_round_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NEXT: mov.b32 %r2, %f1;
+; CHECK-NEXT: and.b32 %r3, %r2, -2147483648;
+; CHECK-NEXT: or.b32 %r4, %r3, 1056964608;
+; CHECK-NEXT: mov.b32 %f2, %r4;
+; CHECK-NEXT: add.rn.f32 %f3, %f1, %f2;
+; CHECK-NEXT: cvt.rzi.f32.f32 %f4, %f3;
+; CHECK-NEXT: abs.f32 %f5, %f1;
+; CHECK-NEXT: setp.gt.f32 %p1, %f5, 0f4B000000;
+; CHECK-NEXT: selp.f32 %f6, %f1, %f4, %p1;
+; CHECK-NEXT: cvt.rzi.f32.f32 %f7, %f1;
+; CHECK-NEXT: setp.lt.f32 %p2, %f5, 0f3F000000;
+; CHECK-NEXT: selp.f32 %f8, %f7, %f6, %p2;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs3, %f8;
+; CHECK-NEXT: cvt.f32.f16 %f9, %rs1;
+; CHECK-NEXT: mov.b32 %r5, %f9;
+; CHECK-NEXT: and.b32 %r6, %r5, -2147483648;
+; CHECK-NEXT: or.b32 %r7, %r6, 1056964608;
+; CHECK-NEXT: mov.b32 %f10, %r7;
+; CHECK-NEXT: add.rn.f32 %f11, %f9, %f10;
+; CHECK-NEXT: cvt.rzi.f32.f32 %f12, %f11;
+; CHECK-NEXT: abs.f32 %f13, %f9;
+; CHECK-NEXT: setp.gt.f32 %p3, %f13, 0f4B000000;
+; CHECK-NEXT: selp.f32 %f14, %f9, %f12, %p3;
+; CHECK-NEXT: cvt.rzi.f32.f32 %f15, %f9;
+; CHECK-NEXT: setp.lt.f32 %p4, %f13, 0f3F000000;
+; CHECK-NEXT: selp.f32 %f16, %f15, %f14, %p4;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs4, %f16;
+; CHECK-NEXT: mov.b32 %r8, {%rs4, %rs3};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r8;
+; CHECK-NEXT: ret;
%r = call <2 x half> @llvm.round.f16(<2 x half> %a)
ret <2 x half> %r
}
-; CHECK-LABEL: test_fmuladd(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_fmuladd_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_fmuladd_param_1];
-; CHECK-DAG: ld.param.b32 [[C:%r[0-9]+]], [test_fmuladd_param_2];
-;
-; CHECK-F16: fma.rn.f16x2 [[R:%r[0-9]+]], [[A]], [[B]], [[C]];
-;
-; CHECK-NOF16-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; CHECK-NOF16-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; CHECK-NOF16-DAG: mov.b32 {[[C0:%rs[0-9]+]], [[C1:%rs[0-9]+]]}, [[C]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA0:%f[0-9]+]], [[A0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB0:%f[0-9]+]], [[B0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FC0:%f[0-9]+]], [[C0]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FA1:%f[0-9]+]], [[A1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FB1:%f[0-9]+]], [[B1]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[FC0:%f[0-9]+]], [[C0]]
-; CHECK-NOF16-DAG: fma.rn.f32 [[FR0:%f[0-9]+]], [[FA0]], [[FB0]], [[FC0]];
-; CHECK-NOF16-DAG: fma.rn.f32 [[FR1:%f[0-9]+]], [[FA1]], [[FB1]], [[FC1]];
-; CHECK-NOF16-DAG: cvt.rn.f16.f32 [[R0:%rs[0-9]+]], [[FR0]]
-; CHECK-NOF16-DAG: cvt.rn.f16.f32 [[R1:%rs[0-9]+]], [[FR1]]
-; CHECK-NOF16: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-;
-; CHECK: st.param.b32 [func_retval0], [[R]];
-; CHECK: ret;
define <2 x half> @test_fmuladd(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
+; CHECK-F16-LABEL: test_fmuladd(
+; CHECK-F16: {
+; CHECK-F16-NEXT: .reg .b32 %r<5>;
+; CHECK-F16-EMPTY:
+; CHECK-F16-NEXT: // %bb.0:
+; CHECK-F16-NEXT: ld.param.b32 %r3, [test_fmuladd_param_2];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fmuladd_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fmuladd_param_0];
+; CHECK-F16-NEXT: fma.rn.f16x2 %r4, %r1, %r2, %r3;
+; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-F16-NEXT: ret;
+;
+; CHECK-NOF16-LABEL: test_fmuladd(
+; CHECK-NOF16: {
+; CHECK-NOF16-NEXT: .reg .b16 %rs<9>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
+; CHECK-NOF16-NEXT: .reg .f32 %f<9>;
+; CHECK-NOF16-EMPTY:
+; CHECK-NOF16-NEXT: // %bb.0:
+; CHECK-NOF16-NEXT: ld.param.b32 %r3, [test_fmuladd_param_2];
+; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fmuladd_param_1];
+; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fmuladd_param_0];
+; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f1, %rs2;
+; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f2, %rs4;
+; CHECK-NOF16-NEXT: mov.b32 {%rs5, %rs6}, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f3, %rs6;
+; CHECK-NOF16-NEXT: fma.rn.f32 %f4, %f3, %f2, %f1;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs7, %f4;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f5, %rs1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f6, %rs3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %f7, %rs5;
+; CHECK-NOF16-NEXT: fma.rn.f32 %f8, %f7, %f6, %f5;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs8, %f8;
+; CHECK-NOF16-NEXT: mov.b32 %r4, {%rs8, %rs7};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NOF16-NEXT: ret;
%r = call <2 x half> @llvm.fmuladd.f16(<2 x half> %a, <2 x half> %b, <2 x half> %c)
ret <2 x half> %r
}
-; CHECK-LABEL: test_shufflevector(
-; CHECK: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK: mov.b32 %r2, {%rs2, %rs1};
define <2 x half> @test_shufflevector(<2 x half> %a) #0 {
+; CHECK-LABEL: test_shufflevector(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_shufflevector_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: mov.b32 %r2, {%rs2, %rs1};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%s = shufflevector <2 x half> %a, <2 x half> undef, <2 x i32> <i32 1, i32 0>
ret <2 x half> %s
}
-; CHECK-LABEL: test_insertelement(
-; CHECK: mov.b32 {%rs2, tmp}, %r1;
-; CHECK: mov.b32 %r2, {%rs2, %rs1};
define <2 x half> @test_insertelement(<2 x half> %a, half %x) #0 {
+; CHECK-LABEL: test_insertelement(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [test_insertelement_param_1];
+; CHECK-NEXT: ld.param.b32 %r1, [test_insertelement_param_0];
+; CHECK-NEXT: { .reg .b16 tmp; mov.b32 {%rs2, tmp}, %r1; }
+; CHECK-NEXT: mov.b32 %r2, {%rs2, %rs1};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%i = insertelement <2 x half> %a, half %x, i64 1
ret <2 x half> %i
}
-; CHECK-LABEL: test_sitofp_2xi16_to_2xhalf(
-; CHECK: cvt.rn.f16.s16
-; CHECK: cvt.rn.f16.s16
-; CHECK: ret;
define <2 x half> @test_sitofp_2xi16_to_2xhalf(<2 x i16> %a) #0 {
+; CHECK-LABEL: test_sitofp_2xi16_to_2xhalf(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.u32 %r1, [test_sitofp_2xi16_to_2xhalf_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.rn.f16.s16 %rs3, %rs2;
+; CHECK-NEXT: cvt.rn.f16.s16 %rs4, %rs1;
+; CHECK-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%r = sitofp <2 x i16> %a to <2 x half>
ret <2 x half> %r
}
-; CHECK-LABEL: test_uitofp_2xi16_to_2xhalf(
-; CHECK: cvt.rn.f16.u16
-; CHECK: cvt.rn.f16.u16
-; CHECK: ret;
define <2 x half> @test_uitofp_2xi16_to_2xhalf(<2 x i16> %a) #0 {
+; CHECK-LABEL: test_uitofp_2xi16_to_2xhalf(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<5>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.u32 %r1, [test_uitofp_2xi16_to_2xhalf_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: cvt.rn.f16.u16 %rs3, %rs2;
+; CHECK-NEXT: cvt.rn.f16.u16 %rs4, %rs1;
+; CHECK-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%r = uitofp <2 x i16> %a to <2 x half>
ret <2 x half> %r
}
diff --git a/llvm/test/CodeGen/NVPTX/i16x2-instructions.ll b/llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
index 988438bebea6d0..388bd314801fc7 100644
--- a/llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
@@ -1,262 +1,381 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; ## Support i16x2 instructions
-; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_90 -mattr=+ptx80 -asm-verbose=false \
+; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_90 -mattr=+ptx80 \
; RUN: -O0 -disable-post-ra -frame-pointer=all -verify-machineinstrs \
; RUN: | FileCheck -allow-deprecated-dag-overlap -check-prefixes COMMON,I16x2 %s
; RUN: %if ptxas %{ \
-; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_90 -asm-verbose=false \
+; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_90 \
; RUN: -O0 -disable-post-ra -frame-pointer=all -verify-machineinstrs \
; RUN: | %ptxas-verify -arch=sm_90 \
; RUN: %}
; ## No support for i16x2 instructions
-; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 -asm-verbose=false \
+; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 \
; RUN: -O0 -disable-post-ra -frame-pointer=all -verify-machineinstrs \
; RUN: | FileCheck -allow-deprecated-dag-overlap -check-prefixes COMMON,NO-I16x2 %s
; RUN: %if ptxas %{ \
-; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 -asm-verbose=false \
+; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_53 \
; RUN: -O0 -disable-post-ra -frame-pointer=all -verify-machineinstrs \
; RUN: | %ptxas-verify -arch=sm_53 \
; RUN: %}
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
-; COMMON-LABEL: test_ret_const(
-; COMMON: mov.b32 [[R:%r[0-9+]]], 131073;
-; COMMON: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_ret_const() #0 {
+; COMMON-LABEL: test_ret_const(
+; COMMON: {
+; COMMON-NEXT: .reg .b32 %r<2>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: mov.b32 %r1, 131073;
+; COMMON-NEXT: st.param.b32 [func_retval0], %r1;
+; COMMON-NEXT: ret;
ret <2 x i16> <i16 1, i16 2>
}
-; COMMON-LABEL: test_extract_0(
-; COMMON: ld.param.u32 [[A:%r[0-9]+]], [test_extract_0_param_0];
-; COMMON: mov.b32 {[[RS:%rs[0-9]+]], tmp}, [[A]];
-; COMMON: cvt.u32.u16 [[R:%r[0-9]+]], [[RS]];
-; COMMON: st.param.b32 [func_retval0], [[R]];
-; COMMON: ret;
define i16 @test_extract_0(<2 x i16> %a) #0 {
+; COMMON-LABEL: test_extract_0(
+; COMMON: {
+; COMMON-NEXT: .reg .b16 %rs<2>;
+; COMMON-NEXT: .reg .b32 %r<3>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u32 %r1, [test_extract_0_param_0];
+; COMMON-NEXT: { .reg .b16 tmp; mov.b32 {%rs1, tmp}, %r1; }
+; COMMON-NEXT: cvt.u32.u16 %r2, %rs1;
+; COMMON-NEXT: st.param.b32 [func_retval0], %r2;
+; COMMON-NEXT: ret;
%e = extractelement <2 x i16> %a, i32 0
ret i16 %e
}
-; COMMON-LABEL: test_extract_1(
-; COMMON: ld.param.u32 [[A:%r[0-9]+]], [test_extract_1_param_0];
-; COMMON: mov.b32 {tmp, [[RS:%rs[0-9]+]]}, [[A]];
-; COMMON: cvt.u32.u16 [[R:%r[0-9]+]], [[RS]];
-; COMMON: st.param.b32 [func_retval0], [[R]];
-; COMMON: ret;
define i16 @test_extract_1(<2 x i16> %a) #0 {
+; COMMON-LABEL: test_extract_1(
+; COMMON: {
+; COMMON-NEXT: .reg .b16 %rs<2>;
+; COMMON-NEXT: .reg .b32 %r<3>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u32 %r1, [test_extract_1_param_0];
+; COMMON-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r1; }
+; COMMON-NEXT: cvt.u32.u16 %r2, %rs1;
+; COMMON-NEXT: st.param.b32 [func_retval0], %r2;
+; COMMON-NEXT: ret;
%e = extractelement <2 x i16> %a, i32 1
ret i16 %e
}
-; COMMON-LABEL: test_extract_i(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_extract_i_param_0];
-; COMMON-DAG: ld.param.u64 [[IDX:%rd[0-9]+]], [test_extract_i_param_1];
-; COMMON-DAG: setp.eq.s64 [[PRED:%p[0-9]+]], [[IDX]], 0;
-; COMMON-DAG: mov.b32 {[[E0:%rs[0-9]+]], [[E1:%rs[0-9]+]]}, [[A]];
-; COMMON: selp.b16 [[RS:%rs[0-9]+]], [[E0]], [[E1]], [[PRED]];
-; COMMON: cvt.u32.u16 [[R:%r[0-9]+]], [[RS]];
-; COMMON: st.param.b32 [func_retval0], [[R]];
-; COMMON: ret;
define i16 @test_extract_i(<2 x i16> %a, i64 %idx) #0 {
+; COMMON-LABEL: test_extract_i(
+; COMMON: {
+; COMMON-NEXT: .reg .pred %p<2>;
+; COMMON-NEXT: .reg .b16 %rs<4>;
+; COMMON-NEXT: .reg .b32 %r<3>;
+; COMMON-NEXT: .reg .b64 %rd<2>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u64 %rd1, [test_extract_i_param_1];
+; COMMON-NEXT: ld.param.u32 %r1, [test_extract_i_param_0];
+; COMMON-NEXT: setp.eq.s64 %p1, %rd1, 0;
+; COMMON-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; COMMON-NEXT: selp.b16 %rs3, %rs1, %rs2, %p1;
+; COMMON-NEXT: cvt.u32.u16 %r2, %rs3;
+; COMMON-NEXT: st.param.b32 [func_retval0], %r2;
+; COMMON-NEXT: ret;
%e = extractelement <2 x i16> %a, i64 %idx
ret i16 %e
}
-; COMMON-LABEL: test_add(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_add_param_0];
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_add_param_1];
-;
-; I16x2-NEXT: add.s16x2 [[R:%r[0-9]+]], [[A]], [[B]];
-;
-; NO-I16x2-DAG: mov.b32 {[[RS0:%rs[0-9]+]], [[RS1:%rs[0-9]+]]}, [[A]];
-; NO-I16x2-DAG: mov.b32 {[[RS2:%rs[0-9]+]], [[RS3:%rs[0-9]+]]}, [[B]];
-; NO-I16x2-DAG: add.s16 [[RS4:%rs[0-9]+]], [[RS0]], [[RS2]];
-; NO-I16x2-DAG: add.s16 [[RS5:%rs[0-9]+]], [[RS1]], [[RS3]];
-; NO-I16x2-DAG: mov.b32 [[R:%r[0-9]+]], {[[RS4]], [[RS5]]};
-;
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_add(<2 x i16> %a, <2 x i16> %b) #0 {
+; I16x2-LABEL: test_add(
+; I16x2: {
+; I16x2-NEXT: .reg .b32 %r<4>;
+; I16x2-EMPTY:
+; I16x2-NEXT: // %bb.0:
+; I16x2-NEXT: ld.param.u32 %r2, [test_add_param_1];
+; I16x2-NEXT: ld.param.u32 %r1, [test_add_param_0];
+; I16x2-NEXT: add.s16x2 %r3, %r1, %r2;
+; I16x2-NEXT: st.param.b32 [func_retval0], %r3;
+; I16x2-NEXT: ret;
+;
+; NO-I16x2-LABEL: test_add(
+; NO-I16x2: {
+; NO-I16x2-NEXT: .reg .b16 %rs<7>;
+; NO-I16x2-NEXT: .reg .b32 %r<4>;
+; NO-I16x2-EMPTY:
+; NO-I16x2-NEXT: // %bb.0:
+; NO-I16x2-NEXT: ld.param.u32 %r2, [test_add_param_1];
+; NO-I16x2-NEXT: ld.param.u32 %r1, [test_add_param_0];
+; NO-I16x2-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; NO-I16x2-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; NO-I16x2-NEXT: add.s16 %rs5, %rs4, %rs2;
+; NO-I16x2-NEXT: add.s16 %rs6, %rs3, %rs1;
+; NO-I16x2-NEXT: mov.b32 %r3, {%rs6, %rs5};
+; NO-I16x2-NEXT: st.param.b32 [func_retval0], %r3;
+; NO-I16x2-NEXT: ret;
%r = add <2 x i16> %a, %b
ret <2 x i16> %r
}
; Check that we can lower add with immediate arguments.
-; COMMON-LABEL: test_add_imm_0(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_add_imm_0_param_0];
-;
-; I16x2: mov.b32 [[I:%r[0-9+]]], 131073;
-; I16x2: add.s16x2 [[R:%r[0-9]+]], [[A]], [[I]];
-;
-; NO-I16x2-DAG: mov.b32 {[[RS0:%rs[0-9]+]], [[RS1:%rs[0-9]+]]}, [[A]];
-; NO-I16x2-DAG: add.s16 [[RS2:%rs[0-9]+]], [[RS0]], 1;
-; NO-I16x2-DAG: add.s16 [[RS3:%rs[0-9]+]], [[RS1]], 2;
-; NO-I16x2-DAG: mov.b32 [[R:%r[0-9]+]], {[[RS2]], [[RS3]]};
-;
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_add_imm_0(<2 x i16> %a) #0 {
+; I16x2-LABEL: test_add_imm_0(
+; I16x2: {
+; I16x2-NEXT: .reg .b32 %r<4>;
+; I16x2-EMPTY:
+; I16x2-NEXT: // %bb.0:
+; I16x2-NEXT: ld.param.u32 %r1, [test_add_imm_0_param_0];
+; I16x2-NEXT: mov.b32 %r2, 131073;
+; I16x2-NEXT: add.s16x2 %r3, %r1, %r2;
+; I16x2-NEXT: st.param.b32 [func_retval0], %r3;
+; I16x2-NEXT: ret;
+;
+; NO-I16x2-LABEL: test_add_imm_0(
+; NO-I16x2: {
+; NO-I16x2-NEXT: .reg .b16 %rs<5>;
+; NO-I16x2-NEXT: .reg .b32 %r<3>;
+; NO-I16x2-EMPTY:
+; NO-I16x2-NEXT: // %bb.0:
+; NO-I16x2-NEXT: ld.param.u32 %r1, [test_add_imm_0_param_0];
+; NO-I16x2-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; NO-I16x2-NEXT: add.s16 %rs3, %rs2, 2;
+; NO-I16x2-NEXT: add.s16 %rs4, %rs1, 1;
+; NO-I16x2-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; NO-I16x2-NEXT: st.param.b32 [func_retval0], %r2;
+; NO-I16x2-NEXT: ret;
%r = add <2 x i16> <i16 1, i16 2>, %a
ret <2 x i16> %r
}
-; COMMON-LABEL: test_add_imm_1(
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_add_imm_1_param_0];
-;
-; I16x2: mov.b32 [[I:%r[0-9+]]], 131073;
-; I16x2: add.s16x2 [[R:%r[0-9]+]], [[A]], [[I]];
-;
-; NO-I16x2-DAG: mov.b32 {[[RS0:%rs[0-9]+]], [[RS1:%rs[0-9]+]]}, [[A]];
-; NO-I16x2-DAG: add.s16 [[RS2:%rs[0-9]+]], [[RS0]], 1;
-; NO-I16x2-DAG: add.s16 [[RS3:%rs[0-9]+]], [[RS1]], 2;
-; NO-I16x2-DAG: mov.b32 [[R:%r[0-9]+]], {[[RS2]], [[RS3]]};
-;
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_add_imm_1(<2 x i16> %a) #0 {
+; I16x2-LABEL: test_add_imm_1(
+; I16x2: {
+; I16x2-NEXT: .reg .b32 %r<4>;
+; I16x2-EMPTY:
+; I16x2-NEXT: // %bb.0:
+; I16x2-NEXT: ld.param.u32 %r1, [test_add_imm_1_param_0];
+; I16x2-NEXT: mov.b32 %r2, 131073;
+; I16x2-NEXT: add.s16x2 %r3, %r1, %r2;
+; I16x2-NEXT: st.param.b32 [func_retval0], %r3;
+; I16x2-NEXT: ret;
+;
+; NO-I16x2-LABEL: test_add_imm_1(
+; NO-I16x2: {
+; NO-I16x2-NEXT: .reg .b16 %rs<5>;
+; NO-I16x2-NEXT: .reg .b32 %r<3>;
+; NO-I16x2-EMPTY:
+; NO-I16x2-NEXT: // %bb.0:
+; NO-I16x2-NEXT: ld.param.u32 %r1, [test_add_imm_1_param_0];
+; NO-I16x2-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; NO-I16x2-NEXT: add.s16 %rs3, %rs2, 2;
+; NO-I16x2-NEXT: add.s16 %rs4, %rs1, 1;
+; NO-I16x2-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; NO-I16x2-NEXT: st.param.b32 [func_retval0], %r2;
+; NO-I16x2-NEXT: ret;
%r = add <2 x i16> %a, <i16 1, i16 2>
ret <2 x i16> %r
}
-; COMMON-LABEL: test_sub(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_sub_param_0];
-;
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_sub_param_1];
-;
-; COMMON-DAG: mov.b32 {[[RS0:%rs[0-9]+]], [[RS1:%rs[0-9]+]]}, [[A]];
-; COMMON-DAG: mov.b32 {[[RS2:%rs[0-9]+]], [[RS3:%rs[0-9]+]]}, [[B]];
-; COMMON-DAG: sub.s16 [[RS4:%rs[0-9]+]], [[RS0]], [[RS2]];
-; COMMON-DAG: sub.s16 [[RS5:%rs[0-9]+]], [[RS1]], [[RS3]];
-; COMMON-DAG: mov.b32 [[R:%r[0-9]+]], {[[RS4]], [[RS5]]};
-;
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_sub(<2 x i16> %a, <2 x i16> %b) #0 {
+; COMMON-LABEL: test_sub(
+; COMMON: {
+; COMMON-NEXT: .reg .b16 %rs<7>;
+; COMMON-NEXT: .reg .b32 %r<4>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u32 %r2, [test_sub_param_1];
+; COMMON-NEXT: ld.param.u32 %r1, [test_sub_param_0];
+; COMMON-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; COMMON-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; COMMON-NEXT: sub.s16 %rs5, %rs4, %rs2;
+; COMMON-NEXT: sub.s16 %rs6, %rs3, %rs1;
+; COMMON-NEXT: mov.b32 %r3, {%rs6, %rs5};
+; COMMON-NEXT: st.param.b32 [func_retval0], %r3;
+; COMMON-NEXT: ret;
%r = sub <2 x i16> %a, %b
ret <2 x i16> %r
}
-; COMMON-LABEL: test_smax(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_smax_param_0];
-;
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_smax_param_1];
-; I16x2: max.s16x2 [[R:%r[0-9]+]], [[A]], [[B]];
-;
-; NO-I16x2-DAG: mov.b32 {[[RS0:%rs[0-9]+]], [[RS1:%rs[0-9]+]]}, [[A]];
-; NO-I16x2-DAG: mov.b32 {[[RS2:%rs[0-9]+]], [[RS3:%rs[0-9]+]]}, [[B]];
-; NO-I16x2-DAG: max.s16 [[RS4:%rs[0-9]+]], [[RS0]], [[RS2]];
-; NO-I16x2-DAG: max.s16 [[RS5:%rs[0-9]+]], [[RS1]], [[RS3]];
-; NO-I16x2-DAG: mov.b32 [[R:%r[0-9]+]], {[[RS4]], [[RS5]]};
-;
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_smax(<2 x i16> %a, <2 x i16> %b) #0 {
+; I16x2-LABEL: test_smax(
+; I16x2: {
+; I16x2-NEXT: .reg .b32 %r<4>;
+; I16x2-EMPTY:
+; I16x2-NEXT: // %bb.0:
+; I16x2-NEXT: ld.param.u32 %r2, [test_smax_param_1];
+; I16x2-NEXT: ld.param.u32 %r1, [test_smax_param_0];
+; I16x2-NEXT: max.s16x2 %r3, %r1, %r2;
+; I16x2-NEXT: st.param.b32 [func_retval0], %r3;
+; I16x2-NEXT: ret;
+;
+; NO-I16x2-LABEL: test_smax(
+; NO-I16x2: {
+; NO-I16x2-NEXT: .reg .b16 %rs<7>;
+; NO-I16x2-NEXT: .reg .b32 %r<4>;
+; NO-I16x2-EMPTY:
+; NO-I16x2-NEXT: // %bb.0:
+; NO-I16x2-NEXT: ld.param.u32 %r2, [test_smax_param_1];
+; NO-I16x2-NEXT: ld.param.u32 %r1, [test_smax_param_0];
+; NO-I16x2-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; NO-I16x2-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; NO-I16x2-NEXT: max.s16 %rs5, %rs4, %rs2;
+; NO-I16x2-NEXT: max.s16 %rs6, %rs3, %rs1;
+; NO-I16x2-NEXT: mov.b32 %r3, {%rs6, %rs5};
+; NO-I16x2-NEXT: st.param.b32 [func_retval0], %r3;
+; NO-I16x2-NEXT: ret;
%cmp = icmp sgt <2 x i16> %a, %b
%r = select <2 x i1> %cmp, <2 x i16> %a, <2 x i16> %b
ret <2 x i16> %r
}
-; COMMON-LABEL: test_umax(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_umax_param_0];
-;
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_umax_param_1];
-; I16x2: max.u16x2 [[R:%r[0-9]+]], [[A]], [[B]];
-;
-; NO-I16x2-DAG: mov.b32 {[[RS0:%rs[0-9]+]], [[RS1:%rs[0-9]+]]}, [[A]];
-; NO-I16x2-DAG: mov.b32 {[[RS2:%rs[0-9]+]], [[RS3:%rs[0-9]+]]}, [[B]];
-; NO-I16x2-DAG: max.u16 [[RS4:%rs[0-9]+]], [[RS0]], [[RS2]];
-; NO-I16x2-DAG: max.u16 [[RS5:%rs[0-9]+]], [[RS1]], [[RS3]];
-; NO-I16x2-DAG: mov.b32 [[R:%r[0-9]+]], {[[RS4]], [[RS5]]};
-;
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_umax(<2 x i16> %a, <2 x i16> %b) #0 {
+; I16x2-LABEL: test_umax(
+; I16x2: {
+; I16x2-NEXT: .reg .b32 %r<4>;
+; I16x2-EMPTY:
+; I16x2-NEXT: // %bb.0:
+; I16x2-NEXT: ld.param.u32 %r2, [test_umax_param_1];
+; I16x2-NEXT: ld.param.u32 %r1, [test_umax_param_0];
+; I16x2-NEXT: max.u16x2 %r3, %r1, %r2;
+; I16x2-NEXT: st.param.b32 [func_retval0], %r3;
+; I16x2-NEXT: ret;
+;
+; NO-I16x2-LABEL: test_umax(
+; NO-I16x2: {
+; NO-I16x2-NEXT: .reg .b16 %rs<7>;
+; NO-I16x2-NEXT: .reg .b32 %r<4>;
+; NO-I16x2-EMPTY:
+; NO-I16x2-NEXT: // %bb.0:
+; NO-I16x2-NEXT: ld.param.u32 %r2, [test_umax_param_1];
+; NO-I16x2-NEXT: ld.param.u32 %r1, [test_umax_param_0];
+; NO-I16x2-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; NO-I16x2-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; NO-I16x2-NEXT: max.u16 %rs5, %rs4, %rs2;
+; NO-I16x2-NEXT: max.u16 %rs6, %rs3, %rs1;
+; NO-I16x2-NEXT: mov.b32 %r3, {%rs6, %rs5};
+; NO-I16x2-NEXT: st.param.b32 [func_retval0], %r3;
+; NO-I16x2-NEXT: ret;
%cmp = icmp ugt <2 x i16> %a, %b
%r = select <2 x i1> %cmp, <2 x i16> %a, <2 x i16> %b
ret <2 x i16> %r
}
-; COMMON-LABEL: test_smin(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_smin_param_0];
-;
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_smin_param_1];
-; I16x2: min.s16x2 [[R:%r[0-9]+]], [[A]], [[B]];
-;
-; NO-I16x2-DAG: mov.b32 {[[RS0:%rs[0-9]+]], [[RS1:%rs[0-9]+]]}, [[A]];
-; NO-I16x2-DAG: mov.b32 {[[RS2:%rs[0-9]+]], [[RS3:%rs[0-9]+]]}, [[B]];
-; NO-I16x2-DAG: min.s16 [[RS4:%rs[0-9]+]], [[RS0]], [[RS2]];
-; NO-I16x2-DAG: min.s16 [[RS5:%rs[0-9]+]], [[RS1]], [[RS3]];
-; NO-I16x2-DAG: mov.b32 [[R:%r[0-9]+]], {[[RS4]], [[RS5]]};
-;
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_smin(<2 x i16> %a, <2 x i16> %b) #0 {
+; I16x2-LABEL: test_smin(
+; I16x2: {
+; I16x2-NEXT: .reg .b32 %r<4>;
+; I16x2-EMPTY:
+; I16x2-NEXT: // %bb.0:
+; I16x2-NEXT: ld.param.u32 %r2, [test_smin_param_1];
+; I16x2-NEXT: ld.param.u32 %r1, [test_smin_param_0];
+; I16x2-NEXT: min.s16x2 %r3, %r1, %r2;
+; I16x2-NEXT: st.param.b32 [func_retval0], %r3;
+; I16x2-NEXT: ret;
+;
+; NO-I16x2-LABEL: test_smin(
+; NO-I16x2: {
+; NO-I16x2-NEXT: .reg .b16 %rs<7>;
+; NO-I16x2-NEXT: .reg .b32 %r<4>;
+; NO-I16x2-EMPTY:
+; NO-I16x2-NEXT: // %bb.0:
+; NO-I16x2-NEXT: ld.param.u32 %r2, [test_smin_param_1];
+; NO-I16x2-NEXT: ld.param.u32 %r1, [test_smin_param_0];
+; NO-I16x2-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; NO-I16x2-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; NO-I16x2-NEXT: min.s16 %rs5, %rs4, %rs2;
+; NO-I16x2-NEXT: min.s16 %rs6, %rs3, %rs1;
+; NO-I16x2-NEXT: mov.b32 %r3, {%rs6, %rs5};
+; NO-I16x2-NEXT: st.param.b32 [func_retval0], %r3;
+; NO-I16x2-NEXT: ret;
%cmp = icmp sle <2 x i16> %a, %b
%r = select <2 x i1> %cmp, <2 x i16> %a, <2 x i16> %b
ret <2 x i16> %r
}
-; COMMON-LABEL: test_umin(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_umin_param_0];
-;
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_umin_param_1];
-; I16x2: min.u16x2 [[R:%r[0-9]+]], [[A]], [[B]];
-;
-; NO-I16x2-DAG: mov.b32 {[[RS0:%rs[0-9]+]], [[RS1:%rs[0-9]+]]}, [[A]];
-; NO-I16x2-DAG: mov.b32 {[[RS2:%rs[0-9]+]], [[RS3:%rs[0-9]+]]}, [[B]];
-; NO-I16x2-DAG: min.u16 [[RS4:%rs[0-9]+]], [[RS0]], [[RS2]];
-; NO-I16x2-DAG: min.u16 [[RS5:%rs[0-9]+]], [[RS1]], [[RS3]];
-; NO-I16x2-DAG: mov.b32 [[R:%r[0-9]+]], {[[RS4]], [[RS5]]};
-;
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_umin(<2 x i16> %a, <2 x i16> %b) #0 {
+; I16x2-LABEL: test_umin(
+; I16x2: {
+; I16x2-NEXT: .reg .b32 %r<4>;
+; I16x2-EMPTY:
+; I16x2-NEXT: // %bb.0:
+; I16x2-NEXT: ld.param.u32 %r2, [test_umin_param_1];
+; I16x2-NEXT: ld.param.u32 %r1, [test_umin_param_0];
+; I16x2-NEXT: min.u16x2 %r3, %r1, %r2;
+; I16x2-NEXT: st.param.b32 [func_retval0], %r3;
+; I16x2-NEXT: ret;
+;
+; NO-I16x2-LABEL: test_umin(
+; NO-I16x2: {
+; NO-I16x2-NEXT: .reg .b16 %rs<7>;
+; NO-I16x2-NEXT: .reg .b32 %r<4>;
+; NO-I16x2-EMPTY:
+; NO-I16x2-NEXT: // %bb.0:
+; NO-I16x2-NEXT: ld.param.u32 %r2, [test_umin_param_1];
+; NO-I16x2-NEXT: ld.param.u32 %r1, [test_umin_param_0];
+; NO-I16x2-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; NO-I16x2-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; NO-I16x2-NEXT: min.u16 %rs5, %rs4, %rs2;
+; NO-I16x2-NEXT: min.u16 %rs6, %rs3, %rs1;
+; NO-I16x2-NEXT: mov.b32 %r3, {%rs6, %rs5};
+; NO-I16x2-NEXT: st.param.b32 [func_retval0], %r3;
+; NO-I16x2-NEXT: ret;
%cmp = icmp ule <2 x i16> %a, %b
%r = select <2 x i1> %cmp, <2 x i16> %a, <2 x i16> %b
ret <2 x i16> %r
}
-; COMMON-LABEL: test_mul(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_mul_param_0];
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_mul_param_1];
-;
-; COMMON-DAG: mov.b32 {[[RS0:%rs[0-9]+]], [[RS1:%rs[0-9]+]]}, [[A]];
-; COMMON-DAG: mov.b32 {[[RS2:%rs[0-9]+]], [[RS3:%rs[0-9]+]]}, [[B]];
-; COMMON-DAG: mul.lo.s16 [[RS4:%rs[0-9]+]], [[RS0]], [[RS2]];
-; COMMON-DAG: mul.lo.s16 [[RS5:%rs[0-9]+]], [[RS1]], [[RS3]];
-; COMMON-DAG: mov.b32 [[R:%r[0-9]+]], {[[RS4]], [[RS5]]};
-;
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_mul(<2 x i16> %a, <2 x i16> %b) #0 {
+; COMMON-LABEL: test_mul(
+; COMMON: {
+; COMMON-NEXT: .reg .b16 %rs<7>;
+; COMMON-NEXT: .reg .b32 %r<4>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u32 %r2, [test_mul_param_1];
+; COMMON-NEXT: ld.param.u32 %r1, [test_mul_param_0];
+; COMMON-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; COMMON-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; COMMON-NEXT: mul.lo.s16 %rs5, %rs4, %rs2;
+; COMMON-NEXT: mul.lo.s16 %rs6, %rs3, %rs1;
+; COMMON-NEXT: mov.b32 %r3, {%rs6, %rs5};
+; COMMON-NEXT: st.param.b32 [func_retval0], %r3;
+; COMMON-NEXT: ret;
%r = mul <2 x i16> %a, %b
ret <2 x i16> %r
}
;; Logical ops are available on all GPUs as regular 32-bit logical ops
-; COMMON-LABEL: test_or(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_or_param_0];
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_or_param_1];
-; COMMON-NEXT: or.b32 [[R:%r[0-9]+]], [[A]], [[B]];
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_or(<2 x i16> %a, <2 x i16> %b) #0 {
+; COMMON-LABEL: test_or(
+; COMMON: {
+; COMMON-NEXT: .reg .b32 %r<7>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u32 %r3, [test_or_param_1];
+; COMMON-NEXT: ld.param.u32 %r4, [test_or_param_0];
+; COMMON-NEXT: or.b32 %r5, %r4, %r3;
+; COMMON-NEXT: st.param.b32 [func_retval0], %r5;
+; COMMON-NEXT: ret;
%r = or <2 x i16> %a, %b
ret <2 x i16> %r
}
; Ops that operate on computed arguments go though a
diff erent lowering path.
; compared to the ones that operate on loaded data. So we test them separately.
-; COMMON-LABEL: test_or_computed(
-; COMMON: ld.param.u16 [[A:%rs[0-9+]]], [test_or_computed_param_0];
-; COMMON-DAG: mov.u16 [[C0:%rs[0-9]+]], 0;
-; COMMON-DAG: mov.b32 [[R1:%r[0-9]+]], {[[A]], [[C0]]};
-; COMMON-DAG: mov.u16 [[C5:%rs[0-9]+]], 5;
-; COMMON-DAG: mov.b32 [[R2:%r[0-9]+]], {[[A]], [[C5]]};
-; COMMON: or.b32 [[R:%r[0-9]+]], [[R2]], [[R1]];
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
define <2 x i16> @test_or_computed(i16 %a) {
+; COMMON-LABEL: test_or_computed(
+; COMMON: {
+; COMMON-NEXT: .reg .b16 %rs<4>;
+; COMMON-NEXT: .reg .b32 %r<4>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u16 %rs1, [test_or_computed_param_0];
+; COMMON-NEXT: mov.u16 %rs2, 0;
+; COMMON-NEXT: mov.b32 %r1, {%rs1, %rs2};
+; COMMON-NEXT: mov.u16 %rs3, 5;
+; COMMON-NEXT: mov.b32 %r2, {%rs1, %rs3};
+; COMMON-NEXT: or.b32 %r3, %r2, %r1;
+; COMMON-NEXT: st.param.b32 [func_retval0], %r3;
+; COMMON-NEXT: ret;
%ins.0 = insertelement <2 x i16> zeroinitializer, i16 %a, i32 0
%ins.1 = insertelement <2 x i16> %ins.0, i16 5, i32 1
%r = or <2 x i16> %ins.1, %ins.0
@@ -264,46 +383,64 @@ define <2 x i16> @test_or_computed(i16 %a) {
}
; Check that we can lower or with immediate arguments.
-; COMMON-LABEL: test_or_imm_0(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_or_imm_0_param_0];
-; COMMON-NEXT: or.b32 [[R:%r[0-9]+]], [[A]], 131073;
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_or_imm_0(<2 x i16> %a) #0 {
+; COMMON-LABEL: test_or_imm_0(
+; COMMON: {
+; COMMON-NEXT: .reg .b32 %r<3>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u32 %r1, [test_or_imm_0_param_0];
+; COMMON-NEXT: or.b32 %r2, %r1, 131073;
+; COMMON-NEXT: st.param.b32 [func_retval0], %r2;
+; COMMON-NEXT: ret;
%r = or <2 x i16> <i16 1, i16 2>, %a
ret <2 x i16> %r
}
-; COMMON-LABEL: test_or_imm_1(
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_or_imm_1_param_0];
-; COMMON-NEXT: or.b32 [[R:%r[0-9]+]], [[A]], 131073;
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_or_imm_1(<2 x i16> %a) #0 {
+; COMMON-LABEL: test_or_imm_1(
+; COMMON: {
+; COMMON-NEXT: .reg .b32 %r<3>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u32 %r1, [test_or_imm_1_param_0];
+; COMMON-NEXT: or.b32 %r2, %r1, 131073;
+; COMMON-NEXT: st.param.b32 [func_retval0], %r2;
+; COMMON-NEXT: ret;
%r = or <2 x i16> %a, <i16 1, i16 2>
ret <2 x i16> %r
}
-; COMMON-LABEL: test_xor(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_xor_param_0];
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_xor_param_1];
-; COMMON-NEXT: xor.b32 [[R:%r[0-9]+]], [[A]], [[B]];
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_xor(<2 x i16> %a, <2 x i16> %b) #0 {
+; COMMON-LABEL: test_xor(
+; COMMON: {
+; COMMON-NEXT: .reg .b32 %r<7>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u32 %r3, [test_xor_param_1];
+; COMMON-NEXT: ld.param.u32 %r4, [test_xor_param_0];
+; COMMON-NEXT: xor.b32 %r5, %r4, %r3;
+; COMMON-NEXT: st.param.b32 [func_retval0], %r5;
+; COMMON-NEXT: ret;
%r = xor <2 x i16> %a, %b
ret <2 x i16> %r
}
-; COMMON-LABEL: test_xor_computed(
-; COMMON: ld.param.u16 [[A:%rs[0-9+]]], [test_xor_computed_param_0];
-; COMMON-DAG: mov.u16 [[C0:%rs[0-9]+]], 0;
-; COMMON-DAG: mov.b32 [[R1:%r[0-9]+]], {[[A]], [[C0]]};
-; COMMON-DAG: mov.u16 [[C5:%rs[0-9]+]], 5;
-; COMMON-DAG: mov.b32 [[R2:%r[0-9]+]], {[[A]], [[C5]]};
-; COMMON: xor.b32 [[R:%r[0-9]+]], [[R2]], [[R1]];
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
define <2 x i16> @test_xor_computed(i16 %a) {
+; COMMON-LABEL: test_xor_computed(
+; COMMON: {
+; COMMON-NEXT: .reg .b16 %rs<4>;
+; COMMON-NEXT: .reg .b32 %r<4>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u16 %rs1, [test_xor_computed_param_0];
+; COMMON-NEXT: mov.u16 %rs2, 0;
+; COMMON-NEXT: mov.b32 %r1, {%rs1, %rs2};
+; COMMON-NEXT: mov.u16 %rs3, 5;
+; COMMON-NEXT: mov.b32 %r2, {%rs1, %rs3};
+; COMMON-NEXT: xor.b32 %r3, %r2, %r1;
+; COMMON-NEXT: st.param.b32 [func_retval0], %r3;
+; COMMON-NEXT: ret;
%ins.0 = insertelement <2 x i16> zeroinitializer, i16 %a, i32 0
%ins.1 = insertelement <2 x i16> %ins.0, i16 5, i32 1
%r = xor <2 x i16> %ins.1, %ins.0
@@ -311,48 +448,66 @@ define <2 x i16> @test_xor_computed(i16 %a) {
}
; Check that we can lower xor with immediate arguments.
-; COMMON-LABEL: test_xor_imm_0(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_xor_imm_0_param_0];
-; COMMON-NEXT: xor.b32 [[R:%r[0-9]+]], [[A]], 131073;
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_xor_imm_0(<2 x i16> %a) #0 {
+; COMMON-LABEL: test_xor_imm_0(
+; COMMON: {
+; COMMON-NEXT: .reg .b32 %r<3>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u32 %r1, [test_xor_imm_0_param_0];
+; COMMON-NEXT: xor.b32 %r2, %r1, 131073;
+; COMMON-NEXT: st.param.b32 [func_retval0], %r2;
+; COMMON-NEXT: ret;
%r = xor <2 x i16> <i16 1, i16 2>, %a
ret <2 x i16> %r
}
-; COMMON-LABEL: test_xor_imm_1(
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_xor_imm_1_param_0];
-; COMMON-NEXT: xor.b32 [[R:%r[0-9]+]], [[A]], 131073;
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_xor_imm_1(<2 x i16> %a) #0 {
+; COMMON-LABEL: test_xor_imm_1(
+; COMMON: {
+; COMMON-NEXT: .reg .b32 %r<3>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u32 %r1, [test_xor_imm_1_param_0];
+; COMMON-NEXT: xor.b32 %r2, %r1, 131073;
+; COMMON-NEXT: st.param.b32 [func_retval0], %r2;
+; COMMON-NEXT: ret;
%r = xor <2 x i16> %a, <i16 1, i16 2>
ret <2 x i16> %r
}
-; COMMON-LABEL: test_and(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_and_param_0];
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_and_param_1];
-; COMMON-NEXT: and.b32 [[R:%r[0-9]+]], [[A]], [[B]];
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_and(<2 x i16> %a, <2 x i16> %b) #0 {
+; COMMON-LABEL: test_and(
+; COMMON: {
+; COMMON-NEXT: .reg .b32 %r<7>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u32 %r3, [test_and_param_1];
+; COMMON-NEXT: ld.param.u32 %r4, [test_and_param_0];
+; COMMON-NEXT: and.b32 %r5, %r4, %r3;
+; COMMON-NEXT: st.param.b32 [func_retval0], %r5;
+; COMMON-NEXT: ret;
%r = and <2 x i16> %a, %b
ret <2 x i16> %r
}
; Ops that operate on computed arguments go though a
diff erent lowering path.
; compared to the ones that operate on loaded data. So we test them separately.
-; COMMON-LABEL: test_and_computed(
-; COMMON: ld.param.u16 [[A:%rs[0-9+]]], [test_and_computed_param_0];
-; COMMON-DAG: mov.u16 [[C0:%rs[0-9]+]], 0;
-; COMMON-DAG: mov.b32 [[R1:%r[0-9]+]], {[[A]], [[C0]]};
-; COMMON-DAG: mov.u16 [[C5:%rs[0-9]+]], 5;
-; COMMON-DAG: mov.b32 [[R2:%r[0-9]+]], {[[A]], [[C5]]};
-; COMMON: and.b32 [[R:%r[0-9]+]], [[R2]], [[R1]];
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
define <2 x i16> @test_and_computed(i16 %a) {
+; COMMON-LABEL: test_and_computed(
+; COMMON: {
+; COMMON-NEXT: .reg .b16 %rs<4>;
+; COMMON-NEXT: .reg .b32 %r<4>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u16 %rs1, [test_and_computed_param_0];
+; COMMON-NEXT: mov.u16 %rs2, 0;
+; COMMON-NEXT: mov.b32 %r1, {%rs1, %rs2};
+; COMMON-NEXT: mov.u16 %rs3, 5;
+; COMMON-NEXT: mov.b32 %r2, {%rs1, %rs3};
+; COMMON-NEXT: and.b32 %r3, %r2, %r1;
+; COMMON-NEXT: st.param.b32 [func_retval0], %r3;
+; COMMON-NEXT: ret;
%ins.0 = insertelement <2 x i16> zeroinitializer, i16 %a, i32 0
%ins.1 = insertelement <2 x i16> %ins.0, i16 5, i32 1
%r = and <2 x i16> %ins.1, %ins.0
@@ -360,74 +515,102 @@ define <2 x i16> @test_and_computed(i16 %a) {
}
; Check that we can lower and with immediate arguments.
-; COMMON-LABEL: test_and_imm_0(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_and_imm_0_param_0];
-; COMMON-NEXT: and.b32 [[R:%r[0-9]+]], [[A]], 131073;
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_and_imm_0(<2 x i16> %a) #0 {
+; COMMON-LABEL: test_and_imm_0(
+; COMMON: {
+; COMMON-NEXT: .reg .b32 %r<3>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u32 %r1, [test_and_imm_0_param_0];
+; COMMON-NEXT: and.b32 %r2, %r1, 131073;
+; COMMON-NEXT: st.param.b32 [func_retval0], %r2;
+; COMMON-NEXT: ret;
%r = and <2 x i16> <i16 1, i16 2>, %a
ret <2 x i16> %r
}
-; COMMON-LABEL: test_and_imm_1(
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_and_imm_1_param_0];
-; COMMON-NEXT: and.b32 [[R:%r[0-9]+]], [[A]], 131073;
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_and_imm_1(<2 x i16> %a) #0 {
+; COMMON-LABEL: test_and_imm_1(
+; COMMON: {
+; COMMON-NEXT: .reg .b32 %r<3>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u32 %r1, [test_and_imm_1_param_0];
+; COMMON-NEXT: and.b32 %r2, %r1, 131073;
+; COMMON-NEXT: st.param.b32 [func_retval0], %r2;
+; COMMON-NEXT: ret;
%r = and <2 x i16> %a, <i16 1, i16 2>
ret <2 x i16> %r
}
-; COMMON-LABEL: .func test_ldst_v2i16(
-; COMMON-DAG: ld.param.u64 [[A:%rd[0-9]+]], [test_ldst_v2i16_param_0];
-; COMMON-DAG: ld.param.u64 [[B:%rd[0-9]+]], [test_ldst_v2i16_param_1];
-; COMMON-DAG: ld.u32 [[E:%r[0-9]+]], [[[A]]];
-; COMMON-DAG: st.u32 [[[B]]], [[E]];
-; COMMON: ret;
define void @test_ldst_v2i16(ptr %a, ptr %b) {
+; COMMON-LABEL: test_ldst_v2i16(
+; COMMON: {
+; COMMON-NEXT: .reg .b32 %r<2>;
+; COMMON-NEXT: .reg .b64 %rd<3>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u64 %rd2, [test_ldst_v2i16_param_1];
+; COMMON-NEXT: ld.param.u64 %rd1, [test_ldst_v2i16_param_0];
+; COMMON-NEXT: ld.u32 %r1, [%rd1];
+; COMMON-NEXT: st.u32 [%rd2], %r1;
+; COMMON-NEXT: ret;
%t1 = load <2 x i16>, ptr %a
store <2 x i16> %t1, ptr %b, align 16
ret void
}
-; COMMON-LABEL: .func test_ldst_v3i16(
-; COMMON-DAG: ld.param.u64 %[[A:rd[0-9]+]], [test_ldst_v3i16_param_0];
-; COMMON-DAG: ld.param.u64 %[[B:rd[0-9]+]], [test_ldst_v3i16_param_1];
; -- v3 is inconvenient to capture as it's lowered as ld.b64 + fair
; number of bitshifting instructions that may change at llvm's whim.
; So we only verify that we only issue correct number of writes using
; correct offset, but not the values we write.
-; COMMON-DAG: ld.u64
-; COMMON-DAG: st.u32 [%[[B]]],
-; COMMON-DAG: st.u16 [%[[B]]+4],
-; COMMON: ret;
define void @test_ldst_v3i16(ptr %a, ptr %b) {
+; COMMON-LABEL: test_ldst_v3i16(
+; COMMON: {
+; COMMON-NEXT: .reg .b64 %rd<5>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u64 %rd2, [test_ldst_v3i16_param_1];
+; COMMON-NEXT: ld.param.u64 %rd1, [test_ldst_v3i16_param_0];
+; COMMON-NEXT: ld.u64 %rd3, [%rd1];
+; COMMON-NEXT: shr.u64 %rd4, %rd3, 32;
+; COMMON-NEXT: st.u32 [%rd2], %rd3;
+; COMMON-NEXT: st.u16 [%rd2+4], %rd4;
+; COMMON-NEXT: ret;
%t1 = load <3 x i16>, ptr %a
store <3 x i16> %t1, ptr %b, align 16
ret void
}
-; COMMON-LABEL: .func test_ldst_v4i16(
-; COMMON-DAG: ld.param.u64 %[[A:rd[0-9]+]], [test_ldst_v4i16_param_0];
-; COMMON-DAG: ld.param.u64 %[[B:rd[0-9]+]], [test_ldst_v4i16_param_1];
-; COMMON-DAG: ld.v4.u16 {[[E0:%rs[0-9]+]], [[E1:%rs[0-9]+]], [[E2:%rs[0-9]+]], [[E3:%rs[0-9]+]]}, [%[[A]]];
-; COMMON-DAG: st.v4.u16 [%[[B]]], {[[E0]], [[E1]], [[E2]], [[E3]]};
-; COMMON: ret;
define void @test_ldst_v4i16(ptr %a, ptr %b) {
+; COMMON-LABEL: test_ldst_v4i16(
+; COMMON: {
+; COMMON-NEXT: .reg .b16 %rs<5>;
+; COMMON-NEXT: .reg .b64 %rd<3>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u64 %rd2, [test_ldst_v4i16_param_1];
+; COMMON-NEXT: ld.param.u64 %rd1, [test_ldst_v4i16_param_0];
+; COMMON-NEXT: ld.v4.u16 {%rs1, %rs2, %rs3, %rs4}, [%rd1];
+; COMMON-NEXT: st.v4.u16 [%rd2], {%rs1, %rs2, %rs3, %rs4};
+; COMMON-NEXT: ret;
%t1 = load <4 x i16>, ptr %a
store <4 x i16> %t1, ptr %b, align 16
ret void
}
-; COMMON-LABEL: .func test_ldst_v8i16(
-; COMMON-DAG: ld.param.u64 %[[A:rd[0-9]+]], [test_ldst_v8i16_param_0];
-; COMMON-DAG: ld.param.u64 %[[B:rd[0-9]+]], [test_ldst_v8i16_param_1];
-; COMMON-DAG: ld.v4.b32 {[[E0:%r[0-9]+]], [[E1:%r[0-9]+]], [[E2:%r[0-9]+]], [[E3:%r[0-9]+]]}, [%[[A]]];
-; COMMON-DAG: st.v4.b32 [%[[B]]], {[[E0]], [[E1]], [[E2]], [[E3]]};
-; COMMON: ret;
define void @test_ldst_v8i16(ptr %a, ptr %b) {
+; COMMON-LABEL: test_ldst_v8i16(
+; COMMON: {
+; COMMON-NEXT: .reg .b32 %r<5>;
+; COMMON-NEXT: .reg .b64 %rd<3>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u64 %rd2, [test_ldst_v8i16_param_1];
+; COMMON-NEXT: ld.param.u64 %rd1, [test_ldst_v8i16_param_0];
+; COMMON-NEXT: ld.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
+; COMMON-NEXT: st.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
+; COMMON-NEXT: ret;
%t1 = load <8 x i16>, ptr %a
store <8 x i16> %t1, ptr %b, align 16
ret void
@@ -435,139 +618,185 @@ define void @test_ldst_v8i16(ptr %a, ptr %b) {
declare <2 x i16> @test_callee(<2 x i16> %a, <2 x i16> %b) #0
-; COMMON-LABEL: test_call(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_call_param_0];
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_call_param_1];
-; COMMON: {
-; COMMON-DAG: .param .align 4 .b8 param0[4];
-; COMMON-DAG: .param .align 4 .b8 param1[4];
-; COMMON-DAG: st.param.b32 [param0], [[A]];
-; COMMON-DAG: st.param.b32 [param1], [[B]];
-; COMMON-DAG: .param .align 4 .b8 retval0[4];
-; COMMON: call.uni (retval0),
-; COMMON-NEXT: test_callee,
-; COMMON: );
-; COMMON-NEXT: ld.param.b32 [[R:%r[0-9]+]], [retval0];
-; COMMON-NEXT: }
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_call(<2 x i16> %a, <2 x i16> %b) #0 {
+; COMMON-LABEL: test_call(
+; COMMON: {
+; COMMON-NEXT: .reg .b32 %r<5>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u32 %r2, [test_call_param_1];
+; COMMON-NEXT: ld.param.u32 %r1, [test_call_param_0];
+; COMMON-NEXT: { // callseq 0, 0
+; COMMON-NEXT: .param .align 4 .b8 param0[4];
+; COMMON-NEXT: st.param.b32 [param0], %r1;
+; COMMON-NEXT: .param .align 4 .b8 param1[4];
+; COMMON-NEXT: st.param.b32 [param1], %r2;
+; COMMON-NEXT: .param .align 4 .b8 retval0[4];
+; COMMON-NEXT: call.uni (retval0),
+; COMMON-NEXT: test_callee,
+; COMMON-NEXT: (
+; COMMON-NEXT: param0,
+; COMMON-NEXT: param1
+; COMMON-NEXT: );
+; COMMON-NEXT: ld.param.b32 %r3, [retval0];
+; COMMON-NEXT: } // callseq 0
+; COMMON-NEXT: st.param.b32 [func_retval0], %r3;
+; COMMON-NEXT: ret;
%r = call <2 x i16> @test_callee(<2 x i16> %a, <2 x i16> %b)
ret <2 x i16> %r
}
-; COMMON-LABEL: test_call_flipped(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_call_flipped_param_0];
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_call_flipped_param_1];
-; COMMON: {
-; COMMON-DAG: .param .align 4 .b8 param0[4];
-; COMMON-DAG: .param .align 4 .b8 param1[4];
-; COMMON-DAG: st.param.b32 [param0], [[B]];
-; COMMON-DAG: st.param.b32 [param1], [[A]];
-; COMMON-DAG: .param .align 4 .b8 retval0[4];
-; COMMON: call.uni (retval0),
-; COMMON-NEXT: test_callee,
-; COMMON: );
-; COMMON-NEXT: ld.param.b32 [[R:%r[0-9]+]], [retval0];
-; COMMON-NEXT: }
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_call_flipped(<2 x i16> %a, <2 x i16> %b) #0 {
+; COMMON-LABEL: test_call_flipped(
+; COMMON: {
+; COMMON-NEXT: .reg .b32 %r<5>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u32 %r2, [test_call_flipped_param_1];
+; COMMON-NEXT: ld.param.u32 %r1, [test_call_flipped_param_0];
+; COMMON-NEXT: { // callseq 1, 0
+; COMMON-NEXT: .param .align 4 .b8 param0[4];
+; COMMON-NEXT: st.param.b32 [param0], %r2;
+; COMMON-NEXT: .param .align 4 .b8 param1[4];
+; COMMON-NEXT: st.param.b32 [param1], %r1;
+; COMMON-NEXT: .param .align 4 .b8 retval0[4];
+; COMMON-NEXT: call.uni (retval0),
+; COMMON-NEXT: test_callee,
+; COMMON-NEXT: (
+; COMMON-NEXT: param0,
+; COMMON-NEXT: param1
+; COMMON-NEXT: );
+; COMMON-NEXT: ld.param.b32 %r3, [retval0];
+; COMMON-NEXT: } // callseq 1
+; COMMON-NEXT: st.param.b32 [func_retval0], %r3;
+; COMMON-NEXT: ret;
%r = call <2 x i16> @test_callee(<2 x i16> %b, <2 x i16> %a)
ret <2 x i16> %r
}
-; COMMON-LABEL: test_tailcall_flipped(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_tailcall_flipped_param_0];
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_tailcall_flipped_param_1];
-; COMMON: {
-; COMMON-DAG: .param .align 4 .b8 param0[4];
-; COMMON-DAG: .param .align 4 .b8 param1[4];
-; COMMON-DAG: st.param.b32 [param0], [[B]];
-; COMMON-DAG: st.param.b32 [param1], [[A]];
-; COMMON-DAG: .param .align 4 .b8 retval0[4];
-; COMMON: call.uni (retval0),
-; COMMON-NEXT: test_callee,
-; COMMON: );
-; COMMON-NEXT: ld.param.b32 [[R:%r[0-9]+]], [retval0];
-; COMMON-NEXT: }
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_tailcall_flipped(<2 x i16> %a, <2 x i16> %b) #0 {
+; COMMON-LABEL: test_tailcall_flipped(
+; COMMON: {
+; COMMON-NEXT: .reg .b32 %r<5>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u32 %r2, [test_tailcall_flipped_param_1];
+; COMMON-NEXT: ld.param.u32 %r1, [test_tailcall_flipped_param_0];
+; COMMON-NEXT: { // callseq 2, 0
+; COMMON-NEXT: .param .align 4 .b8 param0[4];
+; COMMON-NEXT: st.param.b32 [param0], %r2;
+; COMMON-NEXT: .param .align 4 .b8 param1[4];
+; COMMON-NEXT: st.param.b32 [param1], %r1;
+; COMMON-NEXT: .param .align 4 .b8 retval0[4];
+; COMMON-NEXT: call.uni (retval0),
+; COMMON-NEXT: test_callee,
+; COMMON-NEXT: (
+; COMMON-NEXT: param0,
+; COMMON-NEXT: param1
+; COMMON-NEXT: );
+; COMMON-NEXT: ld.param.b32 %r3, [retval0];
+; COMMON-NEXT: } // callseq 2
+; COMMON-NEXT: st.param.b32 [func_retval0], %r3;
+; COMMON-NEXT: ret;
%r = tail call <2 x i16> @test_callee(<2 x i16> %b, <2 x i16> %a)
ret <2 x i16> %r
}
-; COMMON-LABEL: test_select(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_select_param_0];
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_select_param_1];
-; COMMON-DAG: ld.param.u8 [[C:%rs[0-9]+]], [test_select_param_2]
-; COMMON-DAG: setp.eq.b16 [[PRED:%p[0-9]+]], %rs{{.*}}, 1;
-; COMMON-NEXT: selp.b32 [[R:%r[0-9]+]], [[A]], [[B]], [[PRED]];
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_select(<2 x i16> %a, <2 x i16> %b, i1 zeroext %c) #0 {
+; COMMON-LABEL: test_select(
+; COMMON: {
+; COMMON-NEXT: .reg .pred %p<2>;
+; COMMON-NEXT: .reg .b16 %rs<3>;
+; COMMON-NEXT: .reg .b32 %r<4>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u8 %rs1, [test_select_param_2];
+; COMMON-NEXT: and.b16 %rs2, %rs1, 1;
+; COMMON-NEXT: setp.eq.b16 %p1, %rs2, 1;
+; COMMON-NEXT: ld.param.u32 %r2, [test_select_param_1];
+; COMMON-NEXT: ld.param.u32 %r1, [test_select_param_0];
+; COMMON-NEXT: selp.b32 %r3, %r1, %r2, %p1;
+; COMMON-NEXT: st.param.b32 [func_retval0], %r3;
+; COMMON-NEXT: ret;
%r = select i1 %c, <2 x i16> %a, <2 x i16> %b
ret <2 x i16> %r
}
-; COMMON-LABEL: test_select_cc(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_select_cc_param_0];
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_select_cc_param_1];
-; COMMON-DAG: ld.param.u32 [[C:%r[0-9]+]], [test_select_cc_param_2];
-; COMMON-DAG: ld.param.u32 [[D:%r[0-9]+]], [test_select_cc_param_3];
-; COMMON-DAG: mov.b32 {[[C0:%rs[0-9]+]], [[C1:%rs[0-9]+]]}, [[C]]
-; COMMON-DAG: mov.b32 {[[D0:%rs[0-9]+]], [[D1:%rs[0-9]+]]}, [[D]]
-; COMMON-DAG: setp.ne.s16 [[P0:%p[0-9]+]], [[C0]], [[D0]]
-; COMMON-DAG: setp.ne.s16 [[P1:%p[0-9]+]], [[C1]], [[D1]]
-; COMMON-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; COMMON-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; COMMON-DAG: selp.b16 [[R0:%rs[0-9]+]], [[A0]], [[B0]], [[P0]];
-; COMMON-DAG: selp.b16 [[R1:%rs[0-9]+]], [[A1]], [[B1]], [[P1]];
-; COMMON: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_select_cc(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x i16> %d) #0 {
+; COMMON-LABEL: test_select_cc(
+; COMMON: {
+; COMMON-NEXT: .reg .pred %p<3>;
+; COMMON-NEXT: .reg .b16 %rs<11>;
+; COMMON-NEXT: .reg .b32 %r<6>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u32 %r4, [test_select_cc_param_3];
+; COMMON-NEXT: ld.param.u32 %r3, [test_select_cc_param_2];
+; COMMON-NEXT: ld.param.u32 %r2, [test_select_cc_param_1];
+; COMMON-NEXT: ld.param.u32 %r1, [test_select_cc_param_0];
+; COMMON-NEXT: mov.b32 {%rs1, %rs2}, %r4;
+; COMMON-NEXT: mov.b32 {%rs3, %rs4}, %r3;
+; COMMON-NEXT: setp.ne.s16 %p1, %rs3, %rs1;
+; COMMON-NEXT: setp.ne.s16 %p2, %rs4, %rs2;
+; COMMON-NEXT: mov.b32 {%rs5, %rs6}, %r2;
+; COMMON-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; COMMON-NEXT: selp.b16 %rs9, %rs8, %rs6, %p2;
+; COMMON-NEXT: selp.b16 %rs10, %rs7, %rs5, %p1;
+; COMMON-NEXT: mov.b32 %r5, {%rs10, %rs9};
+; COMMON-NEXT: st.param.b32 [func_retval0], %r5;
+; COMMON-NEXT: ret;
%cc = icmp ne <2 x i16> %c, %d
%r = select <2 x i1> %cc, <2 x i16> %a, <2 x i16> %b
ret <2 x i16> %r
}
-; COMMON-LABEL: test_select_cc_i32_i16(
-; COMMON-DAG: ld.param.v2.u32 {[[A0:%r[0-9]+]], [[A1:%r[0-9]+]]}, [test_select_cc_i32_i16_param_0];
-; COMMON-DAG: ld.param.v2.u32 {[[B0:%r[0-9]+]], [[B1:%r[0-9]+]]}, [test_select_cc_i32_i16_param_1];
-; COMMON-DAG: ld.param.u32 [[C:%r[0-9]+]], [test_select_cc_i32_i16_param_2];
-; COMMON-DAG: ld.param.u32 [[D:%r[0-9]+]], [test_select_cc_i32_i16_param_3];
-; COMMON-DAG: mov.b32 {[[C0:%rs[0-9]+]], [[C1:%rs[0-9]+]]}, [[C]]
-; COMMON-DAG: mov.b32 {[[D0:%rs[0-9]+]], [[D1:%rs[0-9]+]]}, [[D]]
-; COMMON-DAG: setp.ne.s16 [[P0:%p[0-9]+]], [[C0]], [[D0]]
-; COMMON-DAG: setp.ne.s16 [[P1:%p[0-9]+]], [[C1]], [[D1]]
-; COMMON-DAG: selp.b32 [[R0:%r[0-9]+]], [[A0]], [[B0]], [[P0]];
-; COMMON-DAG: selp.b32 [[R1:%r[0-9]+]], [[A1]], [[B1]], [[P1]];
-; COMMON-NEXT: st.param.v2.b32 [func_retval0], {[[R0]], [[R1]]};
-; COMMON-NEXT: ret;
define <2 x i32> @test_select_cc_i32_i16(<2 x i32> %a, <2 x i32> %b,
+; COMMON-LABEL: test_select_cc_i32_i16(
+; COMMON: {
+; COMMON-NEXT: .reg .pred %p<3>;
+; COMMON-NEXT: .reg .b16 %rs<5>;
+; COMMON-NEXT: .reg .b32 %r<9>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.v2.u32 {%r3, %r4}, [test_select_cc_i32_i16_param_1];
+; COMMON-NEXT: ld.param.v2.u32 {%r1, %r2}, [test_select_cc_i32_i16_param_0];
+; COMMON-NEXT: ld.param.u32 %r6, [test_select_cc_i32_i16_param_3];
+; COMMON-NEXT: ld.param.u32 %r5, [test_select_cc_i32_i16_param_2];
+; COMMON-NEXT: mov.b32 {%rs1, %rs2}, %r6;
+; COMMON-NEXT: mov.b32 {%rs3, %rs4}, %r5;
+; COMMON-NEXT: setp.ne.s16 %p1, %rs3, %rs1;
+; COMMON-NEXT: setp.ne.s16 %p2, %rs4, %rs2;
+; COMMON-NEXT: selp.b32 %r7, %r2, %r4, %p2;
+; COMMON-NEXT: selp.b32 %r8, %r1, %r3, %p1;
+; COMMON-NEXT: st.param.v2.b32 [func_retval0], {%r8, %r7};
+; COMMON-NEXT: ret;
<2 x i16> %c, <2 x i16> %d) #0 {
%cc = icmp ne <2 x i16> %c, %d
%r = select <2 x i1> %cc, <2 x i32> %a, <2 x i32> %b
ret <2 x i32> %r
}
-; COMMON-LABEL: test_select_cc_i16_i32(
-; COMMON-DAG: ld.param.u32 [[A:%r[0-9]+]], [test_select_cc_i16_i32_param_0];
-; COMMON-DAG: ld.param.u32 [[B:%r[0-9]+]], [test_select_cc_i16_i32_param_1];
-; COMMON-DAG: ld.param.v2.u32 {[[C0:%r[0-9]+]], [[C1:%r[0-9]+]]}, [test_select_cc_i16_i32_param_2];
-; COMMON-DAG: ld.param.v2.u32 {[[D0:%r[0-9]+]], [[D1:%r[0-9]+]]}, [test_select_cc_i16_i32_param_3];
-; COMMON-DAG: setp.ne.s32 [[P0:%p[0-9]+]], [[C0]], [[D0]]
-; COMMON-DAG: setp.ne.s32 [[P1:%p[0-9]+]], [[C1]], [[D1]]
-; COMMON-DAG: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; COMMON-DAG: mov.b32 {[[B0:%rs[0-9]+]], [[B1:%rs[0-9]+]]}, [[B]]
-; COMMON-DAG: selp.b16 [[R0:%rs[0-9]+]], [[A0]], [[B0]], [[P0]];
-; COMMON-DAG: selp.b16 [[R1:%rs[0-9]+]], [[A1]], [[B1]], [[P1]];
-; COMMON: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; COMMON-NEXT: st.param.b32 [func_retval0], [[R]];
-; COMMON-NEXT: ret;
define <2 x i16> @test_select_cc_i16_i32(<2 x i16> %a, <2 x i16> %b,
+; COMMON-LABEL: test_select_cc_i16_i32(
+; COMMON: {
+; COMMON-NEXT: .reg .pred %p<3>;
+; COMMON-NEXT: .reg .b16 %rs<7>;
+; COMMON-NEXT: .reg .b32 %r<8>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.v2.u32 {%r5, %r6}, [test_select_cc_i16_i32_param_3];
+; COMMON-NEXT: ld.param.v2.u32 {%r3, %r4}, [test_select_cc_i16_i32_param_2];
+; COMMON-NEXT: ld.param.u32 %r2, [test_select_cc_i16_i32_param_1];
+; COMMON-NEXT: ld.param.u32 %r1, [test_select_cc_i16_i32_param_0];
+; COMMON-NEXT: setp.ne.s32 %p1, %r3, %r5;
+; COMMON-NEXT: setp.ne.s32 %p2, %r4, %r6;
+; COMMON-NEXT: mov.b32 {%rs1, %rs2}, %r2;
+; COMMON-NEXT: mov.b32 {%rs3, %rs4}, %r1;
+; COMMON-NEXT: selp.b16 %rs5, %rs4, %rs2, %p2;
+; COMMON-NEXT: selp.b16 %rs6, %rs3, %rs1, %p1;
+; COMMON-NEXT: mov.b32 %r7, {%rs6, %rs5};
+; COMMON-NEXT: st.param.b32 [func_retval0], %r7;
+; COMMON-NEXT: ret;
<2 x i32> %c, <2 x i32> %d) #0 {
%cc = icmp ne <2 x i32> %c, %d
%r = select <2 x i1> %cc, <2 x i16> %a, <2 x i16> %b
@@ -575,79 +804,114 @@ define <2 x i16> @test_select_cc_i16_i32(<2 x i16> %a, <2 x i16> %b,
}
-; COMMON-LABEL: test_trunc_2xi32(
-; COMMON: ld.param.v2.u32 {[[A0:%r[0-9]+]], [[A1:%r[0-9]+]]}, [test_trunc_2xi32_param_0];
-; COMMON-DAG: cvt.u16.u32 [[R0:%rs[0-9]+]], [[A0]];
-; COMMON-DAG: cvt.u16.u32 [[R1:%rs[0-9]+]], [[A1]];
-; COMMON: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; COMMON: st.param.b32 [func_retval0], [[R]];
-; COMMON: ret;
define <2 x i16> @test_trunc_2xi32(<2 x i32> %a) #0 {
+; COMMON-LABEL: test_trunc_2xi32(
+; COMMON: {
+; COMMON-NEXT: .reg .b16 %rs<3>;
+; COMMON-NEXT: .reg .b32 %r<4>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.v2.u32 {%r1, %r2}, [test_trunc_2xi32_param_0];
+; COMMON-NEXT: cvt.u16.u32 %rs1, %r2;
+; COMMON-NEXT: cvt.u16.u32 %rs2, %r1;
+; COMMON-NEXT: mov.b32 %r3, {%rs2, %rs1};
+; COMMON-NEXT: st.param.b32 [func_retval0], %r3;
+; COMMON-NEXT: ret;
%r = trunc <2 x i32> %a to <2 x i16>
ret <2 x i16> %r
}
-; COMMON-LABEL: test_trunc_2xi64(
-; COMMON: ld.param.v2.u64 {[[A0:%rd[0-9]+]], [[A1:%rd[0-9]+]]}, [test_trunc_2xi64_param_0];
-; COMMON-DAG: cvt.u16.u64 [[R0:%rs[0-9]+]], [[A0]];
-; COMMON-DAG: cvt.u16.u64 [[R1:%rs[0-9]+]], [[A1]];
-; COMMON: mov.b32 [[R:%r[0-9]+]], {[[R0]], [[R1]]}
-; COMMON: st.param.b32 [func_retval0], [[R]];
-; COMMON: ret;
define <2 x i16> @test_trunc_2xi64(<2 x i64> %a) #0 {
+; COMMON-LABEL: test_trunc_2xi64(
+; COMMON: {
+; COMMON-NEXT: .reg .b16 %rs<3>;
+; COMMON-NEXT: .reg .b32 %r<2>;
+; COMMON-NEXT: .reg .b64 %rd<3>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.v2.u64 {%rd1, %rd2}, [test_trunc_2xi64_param_0];
+; COMMON-NEXT: cvt.u16.u64 %rs1, %rd2;
+; COMMON-NEXT: cvt.u16.u64 %rs2, %rd1;
+; COMMON-NEXT: mov.b32 %r1, {%rs2, %rs1};
+; COMMON-NEXT: st.param.b32 [func_retval0], %r1;
+; COMMON-NEXT: ret;
%r = trunc <2 x i64> %a to <2 x i16>
ret <2 x i16> %r
}
-; COMMON-LABEL: test_zext_2xi32(
-; COMMON: ld.param.u32 [[A:%r[0-9]+]], [test_zext_2xi32_param_0];
-; COMMON: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; COMMON-DAG: cvt.u32.u16 [[R0:%r[0-9]+]], [[A0]];
-; COMMON-DAG: cvt.u32.u16 [[R1:%r[0-9]+]], [[A1]];
-; COMMON-NEXT: st.param.v2.b32 [func_retval0], {[[R0]], [[R1]]};
-; COMMON: ret;
define <2 x i32> @test_zext_2xi32(<2 x i16> %a) #0 {
+; COMMON-LABEL: test_zext_2xi32(
+; COMMON: {
+; COMMON-NEXT: .reg .b16 %rs<3>;
+; COMMON-NEXT: .reg .b32 %r<4>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u32 %r1, [test_zext_2xi32_param_0];
+; COMMON-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; COMMON-NEXT: cvt.u32.u16 %r2, %rs1;
+; COMMON-NEXT: cvt.u32.u16 %r3, %rs2;
+; COMMON-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r3};
+; COMMON-NEXT: ret;
%r = zext <2 x i16> %a to <2 x i32>
ret <2 x i32> %r
}
-; COMMON-LABEL: test_zext_2xi64(
-; COMMON: ld.param.u32 [[A:%r[0-9]+]], [test_zext_2xi64_param_0];
-; COMMON: mov.b32 {[[A0:%rs[0-9]+]], [[A1:%rs[0-9]+]]}, [[A]]
-; COMMON-DAG: cvt.u64.u16 [[R0:%rd[0-9]+]], [[A0]];
-; COMMON-DAG: cvt.u64.u16 [[R1:%rd[0-9]+]], [[A1]];
-; COMMON-NEXT: st.param.v2.b64 [func_retval0], {[[R0]], [[R1]]};
-; COMMON: ret;
define <2 x i64> @test_zext_2xi64(<2 x i16> %a) #0 {
+; COMMON-LABEL: test_zext_2xi64(
+; COMMON: {
+; COMMON-NEXT: .reg .b16 %rs<3>;
+; COMMON-NEXT: .reg .b32 %r<2>;
+; COMMON-NEXT: .reg .b64 %rd<3>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u32 %r1, [test_zext_2xi64_param_0];
+; COMMON-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; COMMON-NEXT: cvt.u64.u16 %rd1, %rs2;
+; COMMON-NEXT: cvt.u64.u16 %rd2, %rs1;
+; COMMON-NEXT: st.param.v2.b64 [func_retval0], {%rd2, %rd1};
+; COMMON-NEXT: ret;
%r = zext <2 x i16> %a to <2 x i64>
ret <2 x i64> %r
}
-; COMMON-LABEL: test_bitcast_i32_to_2xi16(
-; COMMON: ld.param.u32 [[R:%r[0-9]+]], [test_bitcast_i32_to_2xi16_param_0];
-; COMMON: st.param.b32 [func_retval0], [[R]];
-; COMMON: ret;
define <2 x i16> @test_bitcast_i32_to_2xi16(i32 %a) #0 {
+; COMMON-LABEL: test_bitcast_i32_to_2xi16(
+; COMMON: {
+; COMMON-NEXT: .reg .b32 %r<3>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u32 %r1, [test_bitcast_i32_to_2xi16_param_0];
+; COMMON-NEXT: st.param.b32 [func_retval0], %r1;
+; COMMON-NEXT: ret;
%r = bitcast i32 %a to <2 x i16>
ret <2 x i16> %r
}
-; COMMON-LABEL: test_bitcast_2xi16_to_i32(
-; COMMON: ld.param.u32 [[R:%r[0-9]+]], [test_bitcast_2xi16_to_i32_param_0];
-; COMMON: st.param.b32 [func_retval0], [[R]];
-; COMMON: ret;
define i32 @test_bitcast_2xi16_to_i32(<2 x i16> %a) #0 {
+; COMMON-LABEL: test_bitcast_2xi16_to_i32(
+; COMMON: {
+; COMMON-NEXT: .reg .b32 %r<3>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u32 %r2, [test_bitcast_2xi16_to_i32_param_0];
+; COMMON-NEXT: st.param.b32 [func_retval0], %r2;
+; COMMON-NEXT: ret;
%r = bitcast <2 x i16> %a to i32
ret i32 %r
}
-; COMMON-LABEL: test_bitcast_2xi16_to_2xhalf(
-; COMMON: ld.param.u16 [[RS1:%rs[0-9]+]], [test_bitcast_2xi16_to_2xhalf_param_0];
-; COMMON: mov.u16 [[RS2:%rs[0-9]+]], 5;
-; COMMON: mov.b32 [[R:%r[0-9]+]], {[[RS1]], [[RS2]]};
-; COMMON: st.param.b32 [func_retval0], [[R]];
-; COMMON: ret;
define <2 x half> @test_bitcast_2xi16_to_2xhalf(i16 %a) #0 {
+; COMMON-LABEL: test_bitcast_2xi16_to_2xhalf(
+; COMMON: {
+; COMMON-NEXT: .reg .b16 %rs<3>;
+; COMMON-NEXT: .reg .b32 %r<3>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u16 %rs1, [test_bitcast_2xi16_to_2xhalf_param_0];
+; COMMON-NEXT: mov.u16 %rs2, 5;
+; COMMON-NEXT: mov.b32 %r1, {%rs1, %rs2};
+; COMMON-NEXT: st.param.b32 [func_retval0], %r1;
+; COMMON-NEXT: ret;
%ins.0 = insertelement <2 x i16> undef, i16 %a, i32 0
%ins.1 = insertelement <2 x i16> %ins.0, i16 5, i32 1
%r = bitcast <2 x i16> %ins.1 to <2 x half>
@@ -655,43 +919,71 @@ define <2 x half> @test_bitcast_2xi16_to_2xhalf(i16 %a) #0 {
}
-; COMMON-LABEL: test_shufflevector(
-; COMMON: ld.param.u32 [[R:%r[0-9]+]], [test_shufflevector_param_0];
-; COMMON: mov.b32 {[[RS0:%rs[0-9]+]], [[RS1:%rs[0-9]+]]}, [[R]];
-; COMMON: mov.b32 [[R1:%r[0-9]+]], {[[RS1]], [[RS0]]};
-; COMMON: st.param.b32 [func_retval0], [[R1]];
-; COMMON: ret;
define <2 x i16> @test_shufflevector(<2 x i16> %a) #0 {
+; COMMON-LABEL: test_shufflevector(
+; COMMON: {
+; COMMON-NEXT: .reg .b16 %rs<3>;
+; COMMON-NEXT: .reg .b32 %r<3>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u32 %r1, [test_shufflevector_param_0];
+; COMMON-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; COMMON-NEXT: mov.b32 %r2, {%rs2, %rs1};
+; COMMON-NEXT: st.param.b32 [func_retval0], %r2;
+; COMMON-NEXT: ret;
%s = shufflevector <2 x i16> %a, <2 x i16> undef, <2 x i32> <i32 1, i32 0>
ret <2 x i16> %s
}
-; COMMON-LABEL: test_insertelement(
-; COMMON: ld.param.u16 [[B:%rs[0-9]+]], [test_insertelement_param_1];
-; COMMON: ld.param.u32 [[A:%r[0-9]+]], [test_insertelement_param_0];
-; COMMON: { .reg .b16 tmp; mov.b32 {[[R0:%rs[0-9]+]], tmp}, [[A]]; }
-; COMMON: mov.b32 [[R1:%r[0-9]+]], {[[R0]], [[B]]};
-; COMMON: st.param.b32 [func_retval0], [[R1]];
-; COMMON: ret;
define <2 x i16> @test_insertelement(<2 x i16> %a, i16 %x) #0 {
+; COMMON-LABEL: test_insertelement(
+; COMMON: {
+; COMMON-NEXT: .reg .b16 %rs<3>;
+; COMMON-NEXT: .reg .b32 %r<3>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.u16 %rs1, [test_insertelement_param_1];
+; COMMON-NEXT: ld.param.u32 %r1, [test_insertelement_param_0];
+; COMMON-NEXT: { .reg .b16 tmp; mov.b32 {%rs2, tmp}, %r1; }
+; COMMON-NEXT: mov.b32 %r2, {%rs2, %rs1};
+; COMMON-NEXT: st.param.b32 [func_retval0], %r2;
+; COMMON-NEXT: ret;
%i = insertelement <2 x i16> %a, i16 %x, i64 1
ret <2 x i16> %i
}
-; COMMON-LABEL: test_fptosi_2xhalf_to_2xi16(
-; COMMON: cvt.rzi.s16.f16
-; COMMON: cvt.rzi.s16.f16
-; COMMON: ret;
define <2 x i16> @test_fptosi_2xhalf_to_2xi16(<2 x half> %a) #0 {
+; COMMON-LABEL: test_fptosi_2xhalf_to_2xi16(
+; COMMON: {
+; COMMON-NEXT: .reg .b16 %rs<5>;
+; COMMON-NEXT: .reg .b32 %r<3>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.b32 %r1, [test_fptosi_2xhalf_to_2xi16_param_0];
+; COMMON-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; COMMON-NEXT: cvt.rzi.s16.f16 %rs3, %rs2;
+; COMMON-NEXT: cvt.rzi.s16.f16 %rs4, %rs1;
+; COMMON-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; COMMON-NEXT: st.param.b32 [func_retval0], %r2;
+; COMMON-NEXT: ret;
%r = fptosi <2 x half> %a to <2 x i16>
ret <2 x i16> %r
}
-; COMMON-LABEL: test_fptoui_2xhalf_to_2xi16(
-; COMMON: cvt.rzi.u16.f16
-; COMMON: cvt.rzi.u16.f16
-; COMMON: ret;
define <2 x i16> @test_fptoui_2xhalf_to_2xi16(<2 x half> %a) #0 {
+; COMMON-LABEL: test_fptoui_2xhalf_to_2xi16(
+; COMMON: {
+; COMMON-NEXT: .reg .b16 %rs<5>;
+; COMMON-NEXT: .reg .b32 %r<3>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.b32 %r1, [test_fptoui_2xhalf_to_2xi16_param_0];
+; COMMON-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; COMMON-NEXT: cvt.rzi.u16.f16 %rs3, %rs2;
+; COMMON-NEXT: cvt.rzi.u16.f16 %rs4, %rs1;
+; COMMON-NEXT: mov.b32 %r2, {%rs4, %rs3};
+; COMMON-NEXT: st.param.b32 [func_retval0], %r2;
+; COMMON-NEXT: ret;
%r = fptoui <2 x half> %a to <2 x i16>
ret <2 x i16> %r
}
diff --git a/llvm/test/CodeGen/NVPTX/i8x2-instructions.ll b/llvm/test/CodeGen/NVPTX/i8x2-instructions.ll
index df9c3e59b0e6ba..e9662dd8a7fa36 100644
--- a/llvm/test/CodeGen/NVPTX/i8x2-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/i8x2-instructions.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_90 -mattr=+ptx80 -asm-verbose=false \
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=nvptx64-nvidia-cuda -mcpu=sm_90 -mattr=+ptx80 \
; RUN: -O0 -disable-post-ra -frame-pointer=all -verify-machineinstrs \
; RUN: | FileCheck %s
; RUN: %if ptxas %{ \
@@ -9,25 +10,37 @@
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
-; CHECK-LABEL: test_bitcast_2xi8_i16(
-; CHECK: ld.param.u32 %r1, [test_bitcast_2xi8_i16_param_0];
-; CHECK: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK: shl.b16 %rs3, %rs2, 8;
-; CHECK: and.b16 %rs4, %rs1, 255;
-; CHECK: or.b16 %rs5, %rs4, %rs3;
-; CHECK: cvt.u32.u16 %r2, %rs5;
-; CHECK: st.param.b32 [func_retval0], %r2;
define i16 @test_bitcast_2xi8_i16(<2 x i8> %a) {
+; CHECK-LABEL: test_bitcast_2xi8_i16(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<6>;
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.u32 %r1, [test_bitcast_2xi8_i16_param_0];
+; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: shl.b16 %rs3, %rs2, 8;
+; CHECK-NEXT: and.b16 %rs4, %rs1, 255;
+; CHECK-NEXT: or.b16 %rs5, %rs4, %rs3;
+; CHECK-NEXT: cvt.u32.u16 %r2, %rs5;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
%res = bitcast <2 x i8> %a to i16
ret i16 %res
}
-; CHECK-LABEL: test_bitcast_i16_2xi8(
-; CHECK: ld.param.u16 %rs1, [test_bitcast_i16_2xi8_param_0];
-; CHECK: shr.u16 %rs2, %rs1, 8;
-; CHECK: mov.b32 %r1, {%rs1, %rs2};
-; CHECK: st.param.b32 [func_retval0], %r1;
define <2 x i8> @test_bitcast_i16_2xi8(i16 %a) {
+; CHECK-LABEL: test_bitcast_i16_2xi8(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<3>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.u16 %rs1, [test_bitcast_i16_2xi8_param_0];
+; CHECK-NEXT: shr.u16 %rs2, %rs1, 8;
+; CHECK-NEXT: mov.b32 %r1, {%rs1, %rs2};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
%res = bitcast i16 %a to <2 x i8>
ret <2 x i8> %res
}
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