[llvm] 9d70265 - [RISCV] Correct the precedence in isVRegClass (#116579)

[via llvm-commits]

Author: Brandon Wu
Date: 2024-11-18T18:12:57+08:00
New Revision: 9d7026500df1023cee67c5bd10119e1ca9805241

URL: https://github.com/llvm/llvm-project/commit/9d7026500df1023cee67c5bd10119e1ca9805241
DIFF: https://github.com/llvm/llvm-project/commit/9d7026500df1023cee67c5bd10119e1ca9805241.diff

LOG: [RISCV] Correct the precedence in isVRegClass (#116579)

Right shift has higher precedence than bitwise and, so it should be
parentheses around & operator. This case works as expected because
IsVRegClassShift is 0, other cases will fail.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVRegisterInfo.h

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
index 6ddb1eb9c14d5e..3ab79694e175c8 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.h
@@ -39,7 +39,7 @@ enum {
 
 /// \returns the IsVRegClass for the register class.
 static inline bool isVRegClass(uint64_t TSFlags) {
-  return TSFlags & IsVRegClassShiftMask >> IsVRegClassShift;
+  return (TSFlags & IsVRegClassShiftMask) >> IsVRegClassShift;
 }
 
 /// \returns the LMUL for the register class.