[llvm] [RISCV][MachineVerifier] Use RegUnit for register liveness checking (PR #115980)

[Piyou Chen via llvm-commits]

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@@ -3035,6 +3035,13 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
 
             if (llvm::is_contained(TRI->subregs(MOP.getReg()), Reg))
               Bad = false;
+
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BeMg wrote:

Yes, thanks for the reminder. Dropped.


https://github.com/llvm/llvm-project/pull/115980