[llvm] [AArch64][FEAT_CMPBR] Codegen for Armv9.6-a compare-and-branch (PR #116465)

[David Tellenbach via llvm-commits]

dtellenbach wrote:

> Could this be done without introducing new pseudo instructions? They often have a higher cost than you would expect and I'm not sure it makes sense to define the instructions in the way they are currently specified.

The problem is the restricted set of conditions CB supports, which uses a very different encoding than the standard 4-bit condition codes. A number of conditions are expressed by either swapping register operands, e.g. there is no encoding for `cble` but you use `cbge` with swapped operands, or by incrementing/decrementing immediate operands. Now, if you don't use pseudos you have to be careful if you want to invert a condition which happens in a number of places all over the backend. I think it makes sense to reason about the conditions on a more abstract level in terms of standard Arm conditions and then lower them to the real encodings.

Also, I think given the numbers of conditions + instruction variants for CB it makes more sense to treat the conditions as operands and not as part of the instructions, just as we do with `b.<cc>` vs. what we do with `tbz/tbnz` or `cbz/cbnz`.




https://github.com/llvm/llvm-project/pull/116465