[llvm] eed9af9 - [RISCV][GISel] Make loads/stores with s16 register type and s16 memory type legal.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 17 11:40:36 PST 2024
Author: Craig Topper
Date: 2024-11-17T11:39:59-08:00
New Revision: eed9af95e6133e94449c7be585bc3b5fad8ad769
URL: https://github.com/llvm/llvm-project/commit/eed9af95e6133e94449c7be585bc3b5fad8ad769
DIFF: https://github.com/llvm/llvm-project/commit/eed9af95e6133e94449c7be585bc3b5fad8ad769.diff
LOG: [RISCV][GISel] Make loads/stores with s16 register type and s16 memory type legal.
This is needed to support Zfh loads/stores.
This requires supporting extends from sext/zext form i16 and s16
G_FREEZE to support the current tests we have.
Added:
Modified:
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVGISel.td
llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-load-store.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 82b6dcdcd34bc7..f8a13433a1484b 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -154,9 +154,10 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.clampScalar(0, sXLen, sXLen);
getActionDefinitionsBuilder({G_ZEXT, G_SEXT, G_ANYEXT})
+ .legalFor({{sXLen, s16}})
+ .legalFor(ST.is64Bit(), {{s64, s32}})
.legalIf(all(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST),
typeIsLegalIntOrFPVec(1, IntOrFPVecTys, ST)))
- .legalFor(ST.is64Bit(), {{sXLen, s32}})
.customIf(typeIsLegalBoolVec(1, BoolVecTys, ST))
.maxScalar(0, sXLen);
@@ -234,8 +235,18 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.clampScalar(0, sXLen, sXLen);
// TODO: transform illegal vector types into legal vector type
+ getActionDefinitionsBuilder(G_FREEZE)
+ .legalFor({s16, s32, p0})
+ .legalFor(ST.is64Bit(), {s64})
+ .legalIf(typeIsLegalBoolVec(0, BoolVecTys, ST))
+ .legalIf(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST))
+ .widenScalarToNextPow2(0)
+ .clampScalar(0, s16, sXLen);
+
+ // TODO: transform illegal vector types into legal vector type
+ // TODO: Merge with G_FREEZE?
getActionDefinitionsBuilder(
- {G_IMPLICIT_DEF, G_CONSTANT_FOLD_BARRIER, G_FREEZE})
+ {G_IMPLICIT_DEF, G_CONSTANT_FOLD_BARRIER})
.legalFor({s32, sXLen, p0})
.legalIf(typeIsLegalBoolVec(0, BoolVecTys, ST))
.legalIf(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST))
@@ -271,12 +282,14 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
};
LoadActions.legalForTypesWithMemDesc(
- {{s32, p0, s8, getScalarMemAlign(8)},
+ {{s16, p0, s16, getScalarMemAlign(16)},
+ {s32, p0, s8, getScalarMemAlign(8)},
{s32, p0, s16, getScalarMemAlign(16)},
{s32, p0, s32, getScalarMemAlign(32)},
{p0, p0, sXLen, getScalarMemAlign(XLen)}});
StoreActions.legalForTypesWithMemDesc(
- {{s32, p0, s8, getScalarMemAlign(8)},
+ {{s16, p0, s16, getScalarMemAlign(16)},
+ {s32, p0, s8, getScalarMemAlign(8)},
{s32, p0, s16, getScalarMemAlign(16)},
{s32, p0, s32, getScalarMemAlign(32)},
{p0, p0, sXLen, getScalarMemAlign(XLen)}});
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 6ec7f9ab78c0d4..3977816ebdd49c 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -523,6 +523,8 @@ def FeatureStdExtZbkb
def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
AssemblerPredicate<(all_of FeatureStdExtZbkb),
"'Zbkb' (Bitmanip instructions for Cryptography)">;
+def NoStdExtZbkb : Predicate<"!Subtarget->hasStdExtZbkb()">,
+ AssemblerPredicate<(all_of (not FeatureStdExtZbkb))>;
def FeatureStdExtZbkx
: RISCVExtension<"zbkx", 1, 0,
diff --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index 5130bb4c28ccc8..8d1196c4765d47 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -200,14 +200,42 @@ def : Pat<(i32 (trunc GPR:$src)), (COPY GPR:$src)>;
def : Pat<(zext_is_sext (i32 GPR:$src)), (ADDIW GPR:$src, 0)>;
}
-let Predicates = [IsRV64, NotHasStdExtZba] in {
+let Predicates = [IsRV64, NotHasStdExtZba] in
def : Pat<(zext (i32 GPR:$src)), (SRLI (i64 (SLLI GPR:$src, 32)), 32)>;
-}
+
+let Predicates = [IsRV32, NoStdExtZbb, NoStdExtZbkb] in
+def : Pat<(XLenVT (zext (i16 GPR:$src))),
+ (SRLI (XLenVT (SLLI GPR:$src, 16)), 16)>;
+
+let Predicates = [IsRV64, NoStdExtZbb, NoStdExtZbkb] in
+def : Pat<(i64 (zext (i16 GPR:$src))),
+ (SRLI (XLenVT (SLLI GPR:$src, 48)), 48)>;
+
+let Predicates = [IsRV32, NoStdExtZbb] in
+def : Pat<(XLenVT (sext (i16 GPR:$src))),
+ (SRAI (XLenVT (SLLI GPR:$src, 16)), 16)>;
+
+let Predicates = [IsRV64, NoStdExtZbb] in
+def : Pat<(i64 (sext (i16 GPR:$src))),
+ (SRAI (XLenVT (SLLI GPR:$src, 48)), 48)>;
//===----------------------------------------------------------------------===//
-// Zb* RV64 i32 patterns not used by SelectionDAG.
+// Zb* RV64 patterns not used by SelectionDAG.
//===----------------------------------------------------------------------===//
let Predicates = [HasStdExtZba, IsRV64] in {
def : Pat<(zext (i32 GPR:$src)), (ADD_UW GPR:$src, (XLenVT X0))>;
}
+
+let Predicates= [HasStdExtZbb] in
+def : Pat<(XLenVT (sext (i16 GPR:$rs))), (SEXT_H GPR:$rs)>;
+
+let Predicates = [HasStdExtZbb, IsRV32] in
+def : Pat<(i32 (zext (i16 GPR:$rs))), (ZEXT_H_RV32 GPR:$rs)>;
+let Predicates = [HasStdExtZbb, IsRV64] in
+def : Pat<(i64 (zext (i16 GPR:$rs))), (ZEXT_H_RV64 GPR:$rs)>;
+
+let Predicates = [HasStdExtZbkb, NoStdExtZbb, IsRV32] in
+def : Pat<(i32 (zext (i16 GPR:$rs))), (PACK GPR:$rs, (XLenVT X0))>;
+let Predicates = [HasStdExtZbkb, NoStdExtZbb, IsRV64] in
+def : Pat<(i64 (zext (i16 GPR:$rs))), (PACKW GPR:$rs, (XLenVT X0))>;
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll b/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
index d6ba3ab5b817b9..72f0ab159f0a17 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/freeze.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=riscv32 -mattr=+f,+d,+zfh,+m,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV32
-; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+zfh,+m,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,RV64
+; RUN: llc -mtriple=riscv32 -mattr=+f,+d,+zfh,+m,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+f,+d,+zfh,+m,+v -global-isel -global-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
define i32 @freeze_int(i32 %x) {
; CHECK-LABEL: freeze_int:
@@ -130,9 +130,8 @@ define i32 @freeze_anonstruct2(ptr %p) {
; RV32: # %bb.0:
; RV32-NEXT: lh a1, 4(a0)
; RV32-NEXT: lw a0, 0(a0)
-; RV32-NEXT: lui a2, 16
-; RV32-NEXT: addi a2, a2, -1
-; RV32-NEXT: and a1, a1, a2
+; RV32-NEXT: slli a1, a1, 16
+; RV32-NEXT: srli a1, a1, 16
; RV32-NEXT: add a0, a0, a1
; RV32-NEXT: ret
;
@@ -140,9 +139,8 @@ define i32 @freeze_anonstruct2(ptr %p) {
; RV64: # %bb.0:
; RV64-NEXT: lh a1, 4(a0)
; RV64-NEXT: lw a0, 0(a0)
-; RV64-NEXT: lui a2, 16
-; RV64-NEXT: addiw a2, a2, -1
-; RV64-NEXT: and a1, a1, a2
+; RV64-NEXT: slli a1, a1, 48
+; RV64-NEXT: srli a1, a1, 48
; RV64-NEXT: add a0, a0, a1
; RV64-NEXT: ret
%s = load {i32, i16}, ptr %p
@@ -154,6 +152,33 @@ define i32 @freeze_anonstruct2(ptr %p) {
ret i32 %t1
}
+define i32 @freeze_anonstruct2_sext(ptr %p) {
+; RV32-LABEL: freeze_anonstruct2_sext:
+; RV32: # %bb.0:
+; RV32-NEXT: lh a1, 4(a0)
+; RV32-NEXT: lw a0, 0(a0)
+; RV32-NEXT: slli a1, a1, 16
+; RV32-NEXT: srai a1, a1, 16
+; RV32-NEXT: add a0, a0, a1
+; RV32-NEXT: ret
+;
+; RV64-LABEL: freeze_anonstruct2_sext:
+; RV64: # %bb.0:
+; RV64-NEXT: lh a1, 4(a0)
+; RV64-NEXT: lw a0, 0(a0)
+; RV64-NEXT: slli a1, a1, 48
+; RV64-NEXT: srai a1, a1, 48
+; RV64-NEXT: add a0, a0, a1
+; RV64-NEXT: ret
+ %s = load {i32, i16}, ptr %p
+ %y1 = freeze {i32, i16} %s
+ %v1 = extractvalue {i32, i16} %y1, 0
+ %v2 = extractvalue {i32, i16} %y1, 1
+ %z2 = sext i16 %v2 to i32
+ %t1 = add i32 %v1, %z2
+ ret i32 %t1
+}
+
define i32 @freeze_array(ptr %p) nounwind {
; CHECK-LABEL: freeze_array:
; CHECK: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-load-store.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-load-store.mir
index 5441d7c6673bc7..b137b64584f1c1 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-load-store.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/fp-load-store.mir
@@ -1,8 +1,8 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -run-pass=instruction-select %s -o - \
-# RUN: -disable-gisel-legality-check | FileCheck %s
+# RUN: | FileCheck %s
# RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -run-pass=instruction-select %s -o - \
-# RUN: -disable-gisel-legality-check | FileCheck %s
+# RUN: | FileCheck %s
---
name: fp_store_f32
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
index aa7a0e4ad9f3be..73311ae287e7db 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
@@ -143,7 +143,6 @@
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
# DEBUG-NEXT: G_FREEZE (opcode {{[0-9]+}}): 1 type index, 0 imm indices
-# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir
index 3260725ac6f5d3..caa7a775e54a34 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv32.mir
@@ -64,16 +64,18 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
- ; CHECK-NEXT: $x10 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16))
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s16)
+ ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: PseudoRET implicit $x10
;
; UNALIGNED-LABEL: name: load_i16
; UNALIGNED: liveins: $x10
; UNALIGNED-NEXT: {{ $}}
; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
- ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
- ; UNALIGNED-NEXT: $x10 = COPY [[LOAD]](s32)
+ ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16))
+ ; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s16)
+ ; UNALIGNED-NEXT: $x10 = COPY [[ANYEXT]](s32)
; UNALIGNED-NEXT: PseudoRET implicit $x10
%0:_(p0) = COPY $x10
%1:_(s16) = G_LOAD %0(p0) :: (load (s16))
@@ -240,8 +242,9 @@ body: |
; UNALIGNED: liveins: $x10
; UNALIGNED-NEXT: {{ $}}
; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
- ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16), align 1)
- ; UNALIGNED-NEXT: $x10 = COPY [[LOAD]](s32)
+ ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16), align 1)
+ ; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s16)
+ ; UNALIGNED-NEXT: $x10 = COPY [[ANYEXT]](s32)
; UNALIGNED-NEXT: PseudoRET implicit $x10
%0:_(p0) = COPY $x10
%1:_(s16) = G_LOAD %0(p0) :: (load (s16), align 1)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir
index a8584f963f5fdb..40897b845ede70 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-load-rv64.mir
@@ -66,8 +66,8 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
- ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
- ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16))
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s16)
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
;
@@ -75,8 +75,8 @@ body: |
; UNALIGNED: liveins: $x10
; UNALIGNED-NEXT: {{ $}}
; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
- ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16))
- ; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
+ ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16))
+ ; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s16)
; UNALIGNED-NEXT: $x10 = COPY [[ANYEXT]](s64)
; UNALIGNED-NEXT: PseudoRET implicit $x10
%0:_(p0) = COPY $x10
@@ -286,8 +286,8 @@ body: |
; UNALIGNED: liveins: $x10
; UNALIGNED-NEXT: {{ $}}
; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
- ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s16), align 1)
- ; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s32)
+ ; UNALIGNED-NEXT: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[COPY]](p0) :: (load (s16), align 1)
+ ; UNALIGNED-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LOAD]](s16)
; UNALIGNED-NEXT: $x10 = COPY [[ANYEXT]](s64)
; UNALIGNED-NEXT: PseudoRET implicit $x10
%0:_(p0) = COPY $x10
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir
index 30b9e75a58ea39..29466839089bff 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv32.mir
@@ -64,16 +64,18 @@ body: |
; CHECK: liveins: $x10, $x11
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
- ; CHECK-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s16))
+ ; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s16))
; CHECK-NEXT: PseudoRET
;
; UNALIGNED-LABEL: name: store_i16
; UNALIGNED: liveins: $x10, $x11
; UNALIGNED-NEXT: {{ $}}
; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
- ; UNALIGNED-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s16))
+ ; UNALIGNED-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s16))
; UNALIGNED-NEXT: PseudoRET
%2:_(s32) = COPY $x10
%0:_(s16) = G_TRUNC %2(s32)
@@ -241,8 +243,9 @@ body: |
; UNALIGNED: liveins: $x10, $x11
; UNALIGNED-NEXT: {{ $}}
; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
- ; UNALIGNED-NEXT: G_STORE [[COPY]](s32), [[COPY1]](p0) :: (store (s16), align 1)
+ ; UNALIGNED-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s16), align 1)
; UNALIGNED-NEXT: PseudoRET
%2:_(s32) = COPY $x10
%0:_(s16) = G_TRUNC %2(s32)
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir
index f441c614d88670..280b3add093301 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-store-rv64.mir
@@ -66,18 +66,18 @@ body: |
; CHECK: liveins: $x10, $x11
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
- ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s16))
+ ; CHECK-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s16))
; CHECK-NEXT: PseudoRET
;
; UNALIGNED-LABEL: name: store_i16
; UNALIGNED: liveins: $x10, $x11
; UNALIGNED-NEXT: {{ $}}
; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
- ; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; UNALIGNED-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s16))
+ ; UNALIGNED-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s16))
; UNALIGNED-NEXT: PseudoRET
%2:_(s64) = COPY $x10
%0:_(s16) = G_TRUNC %2(s64)
@@ -276,9 +276,9 @@ body: |
; UNALIGNED: liveins: $x10, $x11
; UNALIGNED-NEXT: {{ $}}
; UNALIGNED-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s64)
; UNALIGNED-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x11
- ; UNALIGNED-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
- ; UNALIGNED-NEXT: G_STORE [[TRUNC]](s32), [[COPY1]](p0) :: (store (s16), align 1)
+ ; UNALIGNED-NEXT: G_STORE [[TRUNC]](s16), [[COPY1]](p0) :: (store (s16), align 1)
; UNALIGNED-NEXT: PseudoRET
%2:_(s64) = COPY $x10
%0:_(s16) = G_TRUNC %2(s64)
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