[llvm] 206ee71 - [RISCV] Change vector tuple type's TypeSize to scalable (#114329)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 17 02:52:53 PST 2024
Author: Brandon Wu
Date: 2024-11-17T18:52:49+08:00
New Revision: 206ee7191834186ae78bf57fcf21d29dd7ce24cf
URL: https://github.com/llvm/llvm-project/commit/206ee7191834186ae78bf57fcf21d29dd7ce24cf
DIFF: https://github.com/llvm/llvm-project/commit/206ee7191834186ae78bf57fcf21d29dd7ce24cf.diff
LOG: [RISCV] Change vector tuple type's TypeSize to scalable (#114329)
Vector tuple is basically multiple grouped vector, so its size is also
determined by vscale, we need not to model it as a vector type but its
size need to be scalable.
Added:
Modified:
llvm/include/llvm/CodeGenTypes/MachineValueType.h
llvm/lib/CodeGen/ValueTypes.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGenTypes/MachineValueType.h b/llvm/include/llvm/CodeGenTypes/MachineValueType.h
index 5c47ad4824a791..c14abca027350d 100644
--- a/llvm/include/llvm/CodeGenTypes/MachineValueType.h
+++ b/llvm/include/llvm/CodeGenTypes/MachineValueType.h
@@ -124,7 +124,7 @@ namespace llvm {
/// Return true if this is a custom target type that has a scalable size.
bool isScalableTargetExtVT() const {
- return SimpleTy == MVT::aarch64svcount;
+ return SimpleTy == MVT::aarch64svcount || isRISCVVectorTuple();
}
/// Return true if the type is a scalable type.
@@ -308,7 +308,8 @@ namespace llvm {
TypeSize getSizeInBits() const {
static constexpr TypeSize SizeTable[] = {
#define GET_VT_ATTR(Ty, N, Sz, Any, Int, FP, Vec, Sc, Tup, NF, NElem, EltTy) \
- TypeSize(Sz, Sc || Ty == aarch64svcount /* FIXME: Not in the td. */),
+ TypeSize(Sz, Sc || Tup || Ty == aarch64svcount /* FIXME: Not in the td. \
+ */),
#include "llvm/CodeGen/GenVT.inc"
#undef GET_VT_ATTR
};
diff --git a/llvm/lib/CodeGen/ValueTypes.cpp b/llvm/lib/CodeGen/ValueTypes.cpp
index e3c746b274dde1..2c80eee7c904c1 100644
--- a/llvm/lib/CodeGen/ValueTypes.cpp
+++ b/llvm/lib/CodeGen/ValueTypes.cpp
@@ -163,7 +163,7 @@ std::string EVT::getEVTString() const {
switch (V.SimpleTy) {
default:
if (isRISCVVectorTuple()) {
- unsigned Sz = getSizeInBits();
+ unsigned Sz = getSizeInBits().getKnownMinValue();
unsigned NF = getRISCVVectorTupleNumFields();
unsigned MinNumElts = Sz / (NF * 8);
return "riscv_nxv" + utostr(MinNumElts) + "i8x" + utostr(NF);
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 267a349d298df7..5f970ffe671c63 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2411,8 +2411,9 @@ unsigned RISCVTargetLowering::getSubregIndexByMVT(MVT VT, unsigned Index) {
unsigned RISCVTargetLowering::getRegClassIDForVecVT(MVT VT) {
if (VT.isRISCVVectorTuple()) {
unsigned NF = VT.getRISCVVectorTupleNumFields();
- unsigned RegsPerField = std::max(1U, (unsigned)VT.getSizeInBits() /
- (NF * RISCV::RVVBitsPerBlock));
+ unsigned RegsPerField =
+ std::max(1U, (unsigned)VT.getSizeInBits().getKnownMinValue() /
+ (NF * RISCV::RVVBitsPerBlock));
switch (RegsPerField) {
case 1:
if (NF == 2)
@@ -7036,7 +7037,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
SDLoc DL(Op);
MVT XLenVT = Subtarget.getXLenVT();
unsigned NF = VecTy.getRISCVVectorTupleNumFields();
- unsigned Sz = VecTy.getSizeInBits();
+ unsigned Sz = VecTy.getSizeInBits().getKnownMinValue();
unsigned NumElts = Sz / (NF * 8);
int Log2LMUL = Log2_64(NumElts) - 3;
@@ -7079,7 +7080,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
SDLoc DL(Op);
MVT XLenVT = Subtarget.getXLenVT();
unsigned NF = VecTy.getRISCVVectorTupleNumFields();
- unsigned Sz = VecTy.getSizeInBits();
+ unsigned Sz = VecTy.getSizeInBits().getKnownMinValue();
unsigned NumElts = Sz / (NF * 8);
int Log2LMUL = Log2_64(NumElts) - 3;
@@ -21372,6 +21373,27 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
return true;
}
+ if (ValueVT.isRISCVVectorTuple() && PartVT.isRISCVVectorTuple()) {
+#ifndef NDEBUG
+ unsigned ValNF = ValueVT.getRISCVVectorTupleNumFields();
+ [[maybe_unused]] unsigned ValLMUL =
+ divideCeil(ValueVT.getSizeInBits().getKnownMinValue(),
+ ValNF * RISCV::RVVBitsPerBlock);
+ unsigned PartNF = PartVT.getRISCVVectorTupleNumFields();
+ [[maybe_unused]] unsigned PartLMUL =
+ divideCeil(PartVT.getSizeInBits().getKnownMinValue(),
+ PartNF * RISCV::RVVBitsPerBlock);
+ assert(ValNF == PartNF && ValLMUL == PartLMUL &&
+ "RISC-V vector tuple type only accepts same register class type "
+ "TUPLE_INSERT");
+#endif
+
+ Val = DAG.getNode(RISCVISD::TUPLE_INSERT, DL, PartVT, DAG.getUNDEF(PartVT),
+ Val, DAG.getVectorIdxConstant(0, DL));
+ Parts[0] = Val;
+ return true;
+ }
+
if (ValueVT.isScalableVector() && PartVT.isScalableVector()) {
LLVMContext &Context = *DAG.getContext();
EVT ValueEltVT = ValueVT.getVectorElementType();
@@ -21407,22 +21429,6 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
}
}
- if (ValueVT.isRISCVVectorTuple() && PartVT.isRISCVVectorTuple()) {
- unsigned ValNF = ValueVT.getRISCVVectorTupleNumFields();
- [[maybe_unused]] unsigned ValLMUL =
- divideCeil(ValueVT.getSizeInBits(), ValNF * RISCV::RVVBitsPerBlock);
- unsigned PartNF = PartVT.getRISCVVectorTupleNumFields();
- [[maybe_unused]] unsigned PartLMUL =
- divideCeil(PartVT.getSizeInBits(), PartNF * RISCV::RVVBitsPerBlock);
- assert(ValNF == PartNF && ValLMUL == PartLMUL &&
- "RISC-V vector tuple type only accepts same register class type "
- "TUPLE_INSERT");
-
- Val = DAG.getNode(RISCVISD::TUPLE_INSERT, DL, PartVT, DAG.getUNDEF(PartVT),
- Val, DAG.getVectorIdxConstant(0, DL));
- Parts[0] = Val;
- return true;
- }
return false;
}
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