[llvm] 935d753 - [AArch64][GlobalISel] Add test coverage fir ld1r combines. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sat Nov 16 10:36:19 PST 2024
Author: David Green
Date: 2024-11-16T18:36:14Z
New Revision: 935d753c6dca0cd9bc5ea14fde5b00386ebcc5be
URL: https://github.com/llvm/llvm-project/commit/935d753c6dca0cd9bc5ea14fde5b00386ebcc5be
DIFF: https://github.com/llvm/llvm-project/commit/935d753c6dca0cd9bc5ea14fde5b00386ebcc5be.diff
LOG: [AArch64][GlobalISel] Add test coverage fir ld1r combines. NFC
Added:
Modified:
llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
llvm/test/CodeGen/AArch64/neon-vector-splat.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll b/llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
index 336f2b3bf4a207..7d87be0ce8e1ca 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-simd-ldst-one.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
%struct.uint8x16x2_t = type { [2 x <16 x i8>] }
@@ -295,12 +296,18 @@ entry:
define <1 x i64> @testDUP.v1i64(ptr %a, ptr %b) #0 {
; As there is a store operation depending on %1, LD1R pattern can't be selected.
; So LDR and FMOV should be emitted.
-; CHECK-LABEL: testDUP.v1i64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr x8, [x0]
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: str x8, [x1]
-; CHECK-NEXT: ret
+; CHECK-GI-LABEL: testDUP.v1i64:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr x8, [x0]
+; CHECK-GI-NEXT: fmov d0, x8
+; CHECK-GI-NEXT: str x8, [x1]
+; CHECK-GI-NEXT: ret
+;
+; CHECK-SD-LABEL: testDUP.v1i64:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr d0, [x0]
+; CHECK-SD-NEXT: str d0, [x1]
+; CHECK-SD-NEXT: ret
%1 = load i64, ptr %a, align 8
store i64 %1, ptr %b, align 8
%vecinit.i = insertelement <1 x i64> undef, i64 %1, i32 0
@@ -322,10 +329,16 @@ define <1 x double> @testDUP.v1f64(ptr %a, ptr %b) #0 {
}
define <16 x i8> @test_vld1q_lane_s8(ptr %a, <16 x i8> %b) {
-; CHECK-LABEL: test_vld1q_lane_s8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ld1 { v0.b }[15], [x0]
-; CHECK-NEXT: ret
+; CHECK-GI-LABEL: test_vld1q_lane_s8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: ld1 { v0.b }[15], [x0]
+; CHECK-GI-NEXT: ret
+;
+; CHECK-SD-LABEL: test_vld1q_lane_s8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ldr b1, [x0]
+; CHECK-SD-NEXT: mov v0.b[15], v1.b[0]
+; CHECK-SD-NEXT: ret
entry:
%0 = load i8, ptr %a, align 1
%vld1_lane = insertelement <16 x i8> %b, i8 %0, i32 15
@@ -388,12 +401,20 @@ entry:
}
define <8 x i8> @test_vld1_lane_s8(ptr %a, <8 x i8> %b) {
-; CHECK-LABEL: test_vld1_lane_s8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: ld1 { v0.b }[7], [x0]
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: ret
+; CHECK-GI-LABEL: test_vld1_lane_s8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: ld1 { v0.b }[7], [x0]
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
+;
+; CHECK-SD-LABEL: test_vld1_lane_s8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ldr b1, [x0]
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: mov v0.b[7], v1.b[0]
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: ret
entry:
%0 = load i8, ptr %a, align 1
%vld1_lane = insertelement <8 x i8> %b, i8 %0, i32 7
@@ -607,11 +628,16 @@ entry:
}
define void @test_vst1_lane0_s16(ptr %a, <4 x i16> %b) {
-; CHECK-LABEL: test_vst1_lane0_s16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: str h0, [x0]
-; CHECK-NEXT: ret
+; CHECK-GI-LABEL: test_vst1_lane0_s16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: str h0, [x0]
+; CHECK-GI-NEXT: ret
+;
+; CHECK-SD-LABEL: test_vst1_lane0_s16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: str h0, [x0]
+; CHECK-SD-NEXT: ret
entry:
%0 = extractelement <4 x i16> %b, i32 0
store i16 %0, ptr %a, align 2
@@ -631,11 +657,16 @@ entry:
}
define void @test_vst1_lane0_s32(ptr %a, <2 x i32> %b) {
-; CHECK-LABEL: test_vst1_lane0_s32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: str s0, [x0]
-; CHECK-NEXT: ret
+; CHECK-GI-LABEL: test_vst1_lane0_s32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: str s0, [x0]
+; CHECK-GI-NEXT: ret
+;
+; CHECK-SD-LABEL: test_vst1_lane0_s32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: str s0, [x0]
+; CHECK-SD-NEXT: ret
entry:
%0 = extractelement <2 x i32> %b, i32 0
store i32 %0, ptr %a, align 4
@@ -643,11 +674,16 @@ entry:
}
define void @test_vst1_lane_s64(ptr %a, <1 x i64> %b) {
-; CHECK-LABEL: test_vst1_lane_s64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: str d0, [x0]
-; CHECK-NEXT: ret
+; CHECK-GI-LABEL: test_vst1_lane_s64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: str d0, [x0]
+; CHECK-GI-NEXT: ret
+;
+; CHECK-SD-LABEL: test_vst1_lane_s64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: str d0, [x0]
+; CHECK-SD-NEXT: ret
entry:
%0 = extractelement <1 x i64> %b, i32 0
store i64 %0, ptr %a, align 8
@@ -667,11 +703,16 @@ entry:
}
define void @test_vst1_lane0_f32(ptr %a, <2 x float> %b) {
-; CHECK-LABEL: test_vst1_lane0_f32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: str s0, [x0]
-; CHECK-NEXT: ret
+; CHECK-GI-LABEL: test_vst1_lane0_f32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: str s0, [x0]
+; CHECK-GI-NEXT: ret
+;
+; CHECK-SD-LABEL: test_vst1_lane0_f32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: str s0, [x0]
+; CHECK-SD-NEXT: ret
entry:
%0 = extractelement <2 x float> %b, i32 0
store float %0, ptr %a, align 4
diff --git a/llvm/test/CodeGen/AArch64/neon-vector-splat.ll b/llvm/test/CodeGen/AArch64/neon-vector-splat.ll
index ea5fff67b53fe3..1a253aa2761040 100644
--- a/llvm/test/CodeGen/AArch64/neon-vector-splat.ll
+++ b/llvm/test/CodeGen/AArch64/neon-vector-splat.ll
@@ -1,11 +1,20 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -global-isel=1 -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+; CHECK-GI: warning: Instruction selection used fallback path for shuffle8
define <2 x i32> @shuffle(ptr %P) {
-; CHECK-LABEL: shuffle:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ld1r { v0.2s }, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: shuffle:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ld1r { v0.2s }, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shuffle:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: dup v0.2s, v0.s[0]
+; CHECK-GI-NEXT: ret
%lv2i32 = load <2 x i32>, ptr %P
%B = shufflevector <2 x i32> %lv2i32, <2 x i32> undef, <2 x i32> zeroinitializer
ret <2 x i32> %B
@@ -22,13 +31,21 @@ define <4 x i32> @shuffle2(ptr %P) {
}
define <4 x i32> @shuffle2_multiuse(ptr %P) {
-; CHECK-LABEL: shuffle2_multiuse:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ldr q0, [x0]
-; CHECK-NEXT: dup v1.4s, v0.s[0]
-; CHECK-NEXT: dup v0.4s, v0.s[1]
-; CHECK-NEXT: add v0.4s, v1.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: shuffle2_multiuse:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ldr q0, [x0]
+; CHECK-SD-NEXT: dup v1.4s, v0.s[0]
+; CHECK-SD-NEXT: dup v0.4s, v0.s[1]
+; CHECK-SD-NEXT: add v0.4s, v1.4s, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shuffle2_multiuse:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr q0, [x0]
+; CHECK-GI-NEXT: ld1r { v1.4s }, [x0]
+; CHECK-GI-NEXT: dup v0.4s, v0.s[1]
+; CHECK-GI-NEXT: add v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: ret
%lv2i32 = load <4 x i32>, ptr %P
%B = shufflevector <4 x i32> %lv2i32, <4 x i32> undef, <4 x i32> zeroinitializer
%C = shufflevector <4 x i32> %lv2i32, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
@@ -37,10 +54,16 @@ define <4 x i32> @shuffle2_multiuse(ptr %P) {
}
define <4 x i16> @shuffle3(ptr %P) {
-; CHECK-LABEL: shuffle3:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ld1r { v0.4h }, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: shuffle3:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ld1r { v0.4h }, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shuffle3:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: dup v0.4h, v0.h[0]
+; CHECK-GI-NEXT: ret
%lv4i16 = load <4 x i16>, ptr %P
%sv4i16 = shufflevector <4 x i16> %lv4i16, <4 x i16> undef, <4 x i32> zeroinitializer
ret <4 x i16> %sv4i16
@@ -57,10 +80,16 @@ define <8 x i16> @shuffle4(ptr %P) {
}
define <8 x i8> @shuffle5(ptr %P) {
-; CHECK-LABEL: shuffle5:
-; CHECK: // %bb.0:
-; CHECK-NEXT: ld1r { v0.8b }, [x0]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: shuffle5:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: ld1r { v0.8b }, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: shuffle5:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: ldr d0, [x0]
+; CHECK-GI-NEXT: dup v0.8b, v0.b[0]
+; CHECK-GI-NEXT: ret
%lv8i8 = load <8 x i8>, ptr %P
%sv8i8 = shufflevector <8 x i8> %lv8i8, <8 x i8> undef, <8 x i32> zeroinitializer
ret <8 x i8> %sv8i8
@@ -95,3 +124,35 @@ define <2 x ptr> @shuffle8(ptr %P) {
%sv2ptr = shufflevector <2 x ptr> %lv2ptr, <2 x ptr> undef, <2 x i32> zeroinitializer
ret <2 x ptr> %sv2ptr
}
+
+define <4 x i32> @multiblock_aliasing(ptr %P, i1 %c) {
+; CHECK-SD-LABEL: multiblock_aliasing:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: ldr q0, [x0]
+; CHECK-SD-NEXT: tbz w1, #0, .LBB9_2
+; CHECK-SD-NEXT: // %bb.1: // %then
+; CHECK-SD-NEXT: stp xzr, xzr, [x0]
+; CHECK-SD-NEXT: .LBB9_2: // %else
+; CHECK-SD-NEXT: dup v0.4s, v0.s[0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: multiblock_aliasing:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: tbz w1, #0, .LBB9_2
+; CHECK-GI-NEXT: // %bb.1: // %then
+; CHECK-GI-NEXT: stp xzr, xzr, [x0]
+; CHECK-GI-NEXT: .LBB9_2: // %else
+; CHECK-GI-NEXT: ld1r { v0.4s }, [x0]
+; CHECK-GI-NEXT: ret
+entry:
+ %lv2ptr = load <4 x i32>, ptr %P
+ br i1 %c, label %then, label %else
+
+then:
+ store <4 x i32> zeroinitializer, ptr %P
+ br label %else
+
+else:
+ %sv2ptr = shufflevector <4 x i32> %lv2ptr, <4 x i32> undef, <4 x i32> zeroinitializer
+ ret <4 x i32> %sv2ptr
+}
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