[llvm] [AArch64][FEAT_CMPBR] Codegen for Armv9.6-a compare-and-branch (PR #116465)
David Tellenbach via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 15 19:30:41 PST 2024
https://github.com/dtellenbach updated https://github.com/llvm/llvm-project/pull/116465
>From 42e7ad6315999030b126fad0b00889e64b55d58b Mon Sep 17 00:00:00 2001
From: David Tellenbach <dtellenbach at apple.com>
Date: Thu, 14 Nov 2024 23:36:34 -0800
Subject: [PATCH] [AArch64][FEAT_CMPBR] Codegen for Armv9.6-a
compare-and-branch
This patch adds codegen for all Arm9.6-a compare-and-branch
instructions, that operate on full w or x registers. The instruction
variants operating on half-words (cbh) and bytes (cbb) are added in a
subsequent patch.
Since CB doesn't use standard 4-bit Arm condition codes but a reduced
set of conditions, encoded in 3 bits, some conditions are expressed
by modifying operands, namely incrementing or decrementing immediate
operands and swapping register operands. To invert a CB instruction
it's therefore not enough to just modify the condition code which
doesn't play particularly well with how the backend is currently
organized. We therefore introduce a number of pseudos which operate on
the standard 4-bit condition codes and lower them late during codegen.
---
llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp | 154 +++++++
.../Target/AArch64/AArch64ISelLowering.cpp | 24 ++
llvm/lib/Target/AArch64/AArch64ISelLowering.h | 4 +
.../lib/Target/AArch64/AArch64InstrFormats.td | 19 +
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 96 ++++-
llvm/lib/Target/AArch64/AArch64InstrInfo.h | 4 +
llvm/lib/Target/AArch64/AArch64InstrInfo.td | 25 ++
.../Target/AArch64/Utils/AArch64BaseInfo.h | 20 +
.../AArch64/cmpbr-branch-relaxation.mir | 156 +++++++
.../CodeGen/AArch64/cmpbr-early-ifcvt.mir | 116 +++++
.../CodeGen/AArch64/cmpbr-reg-imm-bounds.ll | 66 +++
llvm/test/CodeGen/AArch64/cmpbr-reg-imm.ll | 402 +++++++++++++++++
llvm/test/CodeGen/AArch64/cmpbr-reg-reg.ll | 405 ++++++++++++++++++
13 files changed, 1490 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/AArch64/cmpbr-branch-relaxation.mir
create mode 100644 llvm/test/CodeGen/AArch64/cmpbr-early-ifcvt.mir
create mode 100644 llvm/test/CodeGen/AArch64/cmpbr-reg-imm-bounds.ll
create mode 100644 llvm/test/CodeGen/AArch64/cmpbr-reg-imm.ll
create mode 100644 llvm/test/CodeGen/AArch64/cmpbr-reg-reg.ll
diff --git a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
index af26fc62292377..cd655e6d6c58f9 100644
--- a/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -181,6 +181,9 @@ class AArch64AsmPrinter : public AsmPrinter {
/// pseudo instructions.
bool lowerPseudoInstExpansion(const MachineInstr *MI, MCInst &Inst);
+ // Emit expansion of Compare-and-branch pseudo instructions
+ void emitCBPseudoExpansion(const MachineInstr *MI);
+
void EmitToStreamer(MCStreamer &S, const MCInst &Inst);
void EmitToStreamer(const MCInst &Inst) {
EmitToStreamer(*OutStreamer, Inst);
@@ -2427,6 +2430,150 @@ AArch64AsmPrinter::lowerBlockAddressConstant(const BlockAddress &BA) {
return BAE;
}
+void AArch64AsmPrinter::emitCBPseudoExpansion(const MachineInstr *MI) {
+ bool IsImm = false;
+ bool Is32Bit = false;
+
+ switch (MI->getOpcode()) {
+ default:
+ llvm_unreachable("This is not a CB pseudo instruction");
+ case AArch64::CBWPrr:
+ IsImm = false;
+ Is32Bit = true;
+ break;
+ case AArch64::CBXPrr:
+ IsImm = false;
+ Is32Bit = false;
+ break;
+ case AArch64::CBWPri:
+ IsImm = true;
+ Is32Bit = true;
+ break;
+ case AArch64::CBXPri:
+ IsImm = true;
+ Is32Bit = false;
+ break;
+ }
+
+ AArch64CC::CondCode CC =
+ static_cast<AArch64CC::CondCode>(MI->getOperand(0).getImm());
+ bool NeedsRegSwap = false;
+ bool NeedsImmDec = false;
+ bool NeedsImmInc = false;
+
+ unsigned MCOpC;
+ switch (CC) {
+ default:
+ llvm_unreachable("Invalid CB condition code");
+ case AArch64CC::EQ:
+ MCOpC = IsImm ? (Is32Bit ? AArch64::CBEQWri : AArch64::CBEQXri)
+ : (Is32Bit ? AArch64::CBEQWrr : AArch64::CBEQXrr);
+ NeedsRegSwap = false;
+ NeedsImmDec = false;
+ NeedsImmInc = false;
+ break;
+ case AArch64CC::NE:
+ MCOpC = IsImm ? (Is32Bit ? AArch64::CBNEWri : AArch64::CBNEXri)
+ : (Is32Bit ? AArch64::CBNEWrr : AArch64::CBNEXrr);
+ NeedsRegSwap = false;
+ NeedsImmDec = false;
+ NeedsImmInc = false;
+ break;
+ case AArch64CC::HS:
+ MCOpC = IsImm ? (Is32Bit ? AArch64::CBHIWri : AArch64::CBHIXri)
+ : (Is32Bit ? AArch64::CBHSWrr : AArch64::CBHSXrr);
+ NeedsRegSwap = false;
+ NeedsImmDec = true;
+ NeedsImmInc = false;
+ break;
+ case AArch64CC::LO:
+ MCOpC = IsImm ? (Is32Bit ? AArch64::CBLOWri : AArch64::CBLOXri)
+ : (Is32Bit ? AArch64::CBHIWrr : AArch64::CBHIXrr);
+ NeedsRegSwap = true;
+ NeedsImmDec = false;
+ NeedsImmInc = false;
+ break;
+ case AArch64CC::HI:
+ MCOpC = IsImm ? (Is32Bit ? AArch64::CBHIWri : AArch64::CBHIXri)
+ : (Is32Bit ? AArch64::CBHIWrr : AArch64::CBHIXrr);
+ NeedsRegSwap = false;
+ NeedsImmDec = false;
+ NeedsImmInc = false;
+ break;
+ case AArch64CC::LS:
+ MCOpC = IsImm ? (Is32Bit ? AArch64::CBLOWri : AArch64::CBLOXri)
+ : (Is32Bit ? AArch64::CBHSWrr : AArch64::CBHSXrr);
+ NeedsRegSwap = !IsImm;
+ NeedsImmDec = false;
+ NeedsImmInc = IsImm;
+ break;
+ case AArch64CC::GE:
+ MCOpC = IsImm ? (Is32Bit ? AArch64::CBGTWri : AArch64::CBGTXri)
+ : (Is32Bit ? AArch64::CBGEWrr : AArch64::CBGEXrr);
+ NeedsRegSwap = false;
+ NeedsImmDec = IsImm;
+ NeedsImmInc = false;
+ break;
+ case AArch64CC::LT:
+ MCOpC = IsImm ? (Is32Bit ? AArch64::CBLTWri : AArch64::CBLTXri)
+ : (Is32Bit ? AArch64::CBGTWrr : AArch64::CBGTXrr);
+ NeedsRegSwap = !IsImm;
+ NeedsImmDec = false;
+ NeedsImmInc = false;
+ break;
+ case AArch64CC::GT:
+ MCOpC = IsImm ? (Is32Bit ? AArch64::CBGTWri : AArch64::CBGTXri)
+ : (Is32Bit ? AArch64::CBGTWrr : AArch64::CBGTXrr);
+ NeedsRegSwap = false;
+ NeedsImmDec = false;
+ NeedsImmInc = false;
+ break;
+ case AArch64CC::LE:
+ MCOpC = IsImm ? (Is32Bit ? AArch64::CBLTWri : AArch64::CBLTXri)
+ : (Is32Bit ? AArch64::CBGEWrr : AArch64::CBGEXrr);
+ NeedsRegSwap = !IsImm;
+ NeedsImmDec = false;
+ NeedsImmInc = IsImm;
+ break;
+ }
+
+ MCInst Inst;
+ Inst.setOpcode(MCOpC);
+
+ MCOperand Lhs, Rhs, Trgt;
+ lowerOperand(MI->getOperand(1), Lhs);
+ lowerOperand(MI->getOperand(2), Rhs);
+ lowerOperand(MI->getOperand(3), Trgt);
+
+ if (NeedsRegSwap) {
+ assert(
+ !IsImm &&
+ "Unexpected register swap for CB instruction with immediate operand");
+ assert(Lhs.isReg() && "Expected register operand for CB");
+ assert(Rhs.isReg() && "Expected register operand for CB");
+ // Swap register operands
+ Inst.addOperand(Rhs);
+ Inst.addOperand(Lhs);
+ } else if (IsImm && NeedsImmDec) {
+ assert(IsImm && "Unexpected immediate decrement for CB instruction with "
+ "reg-reg operands");
+ Rhs.setImm(Rhs.getImm() - 1);
+ Inst.addOperand(Lhs);
+ Inst.addOperand(Rhs);
+ } else if (NeedsImmInc) {
+ assert(IsImm && "Unexpected immediate increment for CB instruction with "
+ "reg-reg operands");
+ Rhs.setImm(Rhs.getImm() + 1);
+ Inst.addOperand(Lhs);
+ Inst.addOperand(Rhs);
+ } else {
+ Inst.addOperand(Lhs);
+ Inst.addOperand(Rhs);
+ }
+ Inst.addOperand(Trgt);
+ EmitToStreamer(*OutStreamer, Inst);
+}
+
// Simple pseudo-instructions have their lowering (with expansion to real
// instructions) auto-generated.
#include "AArch64GenMCPseudoLowering.inc"
@@ -2948,6 +3095,13 @@ void AArch64AsmPrinter::emitInstruction(const MachineInstr *MI) {
TS->emitARM64WinCFISaveAnyRegQPX(MI->getOperand(0).getImm(),
-MI->getOperand(2).getImm());
return;
+
+ case AArch64::CBWPri:
+ case AArch64::CBXPri:
+ case AArch64::CBWPrr:
+ case AArch64::CBXPrr:
+ emitCBPseudoExpansion(MI);
+ return;
}
// Finally, do the automated lowerings for everything else.
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 9d1c3d4eddc880..3e35a85d4fe806 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -2954,6 +2954,8 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
MAKE_CASE(AArch64ISD::CTTZ_ELTS)
MAKE_CASE(AArch64ISD::CALL_ARM64EC_TO_X64)
MAKE_CASE(AArch64ISD::URSHR_I_PRED)
+ MAKE_CASE(AArch64ISD::CBRR)
+ MAKE_CASE(AArch64ISD::CBRI)
}
#undef MAKE_CASE
return nullptr;
@@ -10396,6 +10398,28 @@ SDValue AArch64TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
DAG.getConstant(SignBitPos, dl, MVT::i64), Dest);
}
+ // Try to emit Armv9.6 CB instructions. We prefer tb{n}z/cb{n}z due to their
+ // larger branch displacement but do prefer CB over cmp + br.
+ if (Subtarget->hasCMPBR() &&
+ AArch64CC::isValidCBCond(changeIntCCToAArch64CC(CC)) &&
+ ProduceNonFlagSettingCondBr) {
+ AArch64CC::CondCode ACC = changeIntCCToAArch64CC(CC);
+ unsigned Opc = AArch64ISD::CBRR;
+ if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(RHS)) {
+ APInt NewImm = Imm->getAPIntValue();
+ if (ACC == AArch64CC::GE || ACC == AArch64CC::HS)
+ NewImm = Imm->getAPIntValue() - 1;
+ else if (ACC == AArch64CC::LE || ACC == AArch64CC::LS)
+ NewImm = Imm->getAPIntValue() + 1;
+
+ if (NewImm.uge(0) && NewImm.ult(64))
+ Opc = AArch64ISD::CBRI;
+ }
+
+ SDValue Cond = DAG.getTargetConstant(ACC, dl, MVT::i32);
+ return DAG.getNode(Opc, dl, MVT::Other, Chain, Cond, LHS, RHS, Dest);
+ }
+
SDValue CCVal;
SDValue Cmp = getAArch64Cmp(LHS, RHS, CC, CCVal, DAG, dl);
return DAG.getNode(AArch64ISD::BRCOND, dl, MVT::Other, Chain, Dest, CCVal,
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index d11da64d3f84eb..7de5f4490e78db 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -520,6 +520,10 @@ enum NodeType : unsigned {
MOPS_MEMSET_TAGGING,
MOPS_MEMCOPY,
MOPS_MEMMOVE,
+
+ // Compare-and-branch
+ CBRR,
+ CBRI,
};
} // end namespace AArch64ISD
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 15d4e93b915c14..ca2bfae8d7e8a0 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -13065,6 +13065,7 @@ class BaseCmpBranchRegister<RegisterClass regtype, bit sf, bits<3> cc,
Sched<[WriteBr]> {
let isBranch = 1;
let isTerminator = 1;
+ let isCompare = 1;
bits<5> Rm;
bits<5> Rt;
@@ -13091,6 +13092,7 @@ class BaseCmpBranchImmediate<RegisterClass regtype, bit sf, bits<3> cc,
Sched<[WriteBr]> {
let isBranch = 1;
let isTerminator = 1;
+ let isCompare = 1;
bits<5> Rt;
bits<6> imm;
@@ -13131,6 +13133,23 @@ multiclass CmpBranchRegisterAlias<string mnemonic, string insn> {
def : InstAlias<mnemonic # "\t$Rt, $Rm, $target",
(!cast<Instruction>(insn # "Xrr") GPR64:$Rm, GPR64:$Rt, am_brcmpcond:$target), 0>;
}
+
+class CmpBranchRegisterPseudo<RegisterClass regtype>
+ : Pseudo<(outs), (ins ccode:$Cond, regtype:$Rt, regtype:$Rm, am_brcmpcond:$Target), []>,
+ Sched<[WriteBr]> {
+ let isBranch = 1;
+ let isTerminator = 1;
+ let isCompare = 1;
+}
+
+class CmpBranchImmediatePseudo<RegisterClass regtype, ImmLeaf imtype>
+ : Pseudo<(outs), (ins ccode:$Cond, regtype:$Rt, imtype:$Imm, am_brcmpcond:$Target), []>,
+ Sched<[WriteBr]> {
+ let isBranch = true;
+ let isTerminator = true;
+ let isCompare = true;
+}
+
//----------------------------------------------------------------------------
// Allow the size specifier tokens to be upper case, not just lower.
def : TokenAlias<".4B", ".4b">; // Add dot product
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index a470c03efd5eb4..73cc235982c392 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -62,6 +62,10 @@ using namespace llvm;
#define GET_INSTRINFO_CTOR_DTOR
#include "AArch64GenInstrInfo.inc"
+static cl::opt<unsigned>
+ CBDisplacementBits("aarch64-cb-offset-bits", cl::Hidden, cl::init(9),
+ cl::desc("Restrict range of CB instructions (DEBUG)"));
+
static cl::opt<unsigned> TBZDisplacementBits(
"aarch64-tbz-offset-bits", cl::Hidden, cl::init(14),
cl::desc("Restrict range of TB[N]Z instructions (DEBUG)"));
@@ -216,6 +220,17 @@ static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
Cond.push_back(LastInst->getOperand(0));
Cond.push_back(LastInst->getOperand(1));
+ break;
+ case AArch64::CBWPri:
+ case AArch64::CBXPri:
+ case AArch64::CBWPrr:
+ case AArch64::CBXPrr:
+ Target = LastInst->getOperand(3).getMBB();
+ Cond.push_back(MachineOperand::CreateImm(-1));
+ Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
+ Cond.push_back(LastInst->getOperand(0));
+ Cond.push_back(LastInst->getOperand(1));
+ Cond.push_back(LastInst->getOperand(2));
}
}
@@ -237,6 +252,11 @@ static unsigned getBranchDisplacementBits(unsigned Opc) {
return CBZDisplacementBits;
case AArch64::Bcc:
return BCCDisplacementBits;
+ case AArch64::CBWPri:
+ case AArch64::CBXPri:
+ case AArch64::CBWPrr:
+ case AArch64::CBXPrr:
+ return CBDisplacementBits;
}
}
@@ -266,6 +286,11 @@ AArch64InstrInfo::getBranchDestBlock(const MachineInstr &MI) const {
case AArch64::CBNZX:
case AArch64::Bcc:
return MI.getOperand(1).getMBB();
+ case AArch64::CBWPri:
+ case AArch64::CBXPri:
+ case AArch64::CBWPrr:
+ case AArch64::CBXPrr:
+ return MI.getOperand(3).getMBB();
}
}
@@ -543,6 +568,17 @@ bool AArch64InstrInfo::reverseBranchCondition(
case AArch64::TBNZX:
Cond[1].setImm(AArch64::TBZX);
break;
+
+ // Cond is { -1, Opcode, CC, Op0, Op1 }
+ case AArch64::CBWPri:
+ case AArch64::CBXPri:
+ case AArch64::CBWPrr:
+ case AArch64::CBXPrr: {
+ // Pseudos using standard 4bit Arm condition codes
+ AArch64CC::CondCode CC =
+ static_cast<AArch64CC::CondCode>(Cond[2].getImm());
+ Cond[2].setImm(AArch64CC::getInvertedCondCode(CC));
+ } break;
}
}
@@ -593,10 +629,19 @@ void AArch64InstrInfo::instantiateCondBranch(
} else {
// Folded compare-and-branch
// Note that we use addOperand instead of addReg to keep the flags.
+
+ // cbz, cbnz
const MachineInstrBuilder MIB =
BuildMI(&MBB, DL, get(Cond[1].getImm())).add(Cond[2]);
+
+ // tbz/tbnz
if (Cond.size() > 3)
- MIB.addImm(Cond[3].getImm());
+ MIB.add(Cond[3]);
+
+ // cb
+ if (Cond.size() > 4)
+ MIB.add(Cond[4]);
+
MIB.addMBB(TBB);
}
}
@@ -842,6 +887,51 @@ void AArch64InstrInfo::insertSelect(MachineBasicBlock &MBB,
AArch64_AM::encodeLogicalImmediate(1ull << Cond[3].getImm(), 64));
break;
}
+ case 5: { // cb
+ // We must insert a cmp, that is a subs
+ // 0 1 2 3 4
+ // Cond is { -1, Opcode, CC, Op0, Op1 }
+ unsigned SUBSOpC, SUBSDestReg;
+ bool IsImm = false;
+ switch (Cond[1].getImm()) {
+ default:
+ llvm_unreachable("Unknown branch opcode in Cond");
+ case AArch64::CBWPri:
+ SUBSOpC = AArch64::SUBSWri;
+ SUBSDestReg = AArch64::WZR;
+ IsImm = true;
+ CC = static_cast<AArch64CC::CondCode>(Cond[2].getImm());
+ break;
+ case AArch64::CBXPri:
+ SUBSOpC = AArch64::SUBSXri;
+ SUBSDestReg = AArch64::XZR;
+ IsImm = true;
+ CC = static_cast<AArch64CC::CondCode>(Cond[2].getImm());
+ break;
+ case AArch64::CBWPrr:
+ SUBSOpC = AArch64::SUBSWrr;
+ SUBSDestReg = AArch64::WZR;
+ IsImm = false;
+ CC = static_cast<AArch64CC::CondCode>(Cond[2].getImm());
+ break;
+ case AArch64::CBXPrr:
+ SUBSOpC = AArch64::SUBSXrr;
+ SUBSDestReg = AArch64::XZR;
+ IsImm = false;
+ CC = static_cast<AArch64CC::CondCode>(Cond[2].getImm());
+ break;
+ }
+
+ if (IsImm)
+ BuildMI(MBB, I, DL, get(SUBSOpC), SUBSDestReg)
+ .addReg(Cond[3].getReg())
+ .addImm(Cond[4].getImm())
+ .addImm(0);
+ else
+ BuildMI(MBB, I, DL, get(SUBSOpC), SUBSDestReg)
+ .addReg(Cond[3].getReg())
+ .addReg(Cond[4].getReg());
+ }
}
unsigned Opc = 0;
@@ -8393,6 +8483,10 @@ bool AArch64InstrInfo::optimizeCondBranch(MachineInstr &MI) const {
default:
llvm_unreachable("Unknown branch instruction?");
case AArch64::Bcc:
+ case AArch64::CBWPri:
+ case AArch64::CBXPri:
+ case AArch64::CBWPrr:
+ case AArch64::CBXPrr:
return false;
case AArch64::CBZW:
case AArch64::CBZX:
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index e37f70f7d985de..151e397edd6195 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -693,6 +693,10 @@ static inline bool isCondBranchOpcode(int Opc) {
case AArch64::TBZX:
case AArch64::TBNZW:
case AArch64::TBNZX:
+ case AArch64::CBWPri:
+ case AArch64::CBXPri:
+ case AArch64::CBWPrr:
+ case AArch64::CBXPrr:
return true;
default:
return false;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index e4ad27d4bcfc00..67efe50bc1f5f3 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -508,6 +508,9 @@ def SDT_AArch64TBL : SDTypeProfile<1, 2, [
SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisInt<2>
]>;
+def SDT_AArch64cbrr : SDTypeProfile<0, 4, [SDTCisVT<0, i32>, SDTCisInt<1>, SDTCisSameAs<1, 2>, SDTCisVT<3, OtherVT>]>;
+def SDT_AArch64cbri : SDTypeProfile<0, 4, [SDTCisVT<0, i32>, SDTCisInt<1>, SDTCisInt<2>, SDTCisVT<3, OtherVT>]>;
+
// non-extending masked load fragment.
def nonext_masked_load :
PatFrag<(ops node:$ptr, node:$pred, node:$def),
@@ -684,6 +687,8 @@ def topbitsallzero64: PatLeaf<(i64 GPR64:$src), [{
}]>;
// Node definitions.
+def AArch64CBrr : SDNode<"AArch64ISD::CBRR", SDT_AArch64cbrr, [SDNPHasChain]>;
+def AArch64CBri : SDNode<"AArch64ISD::CBRI", SDT_AArch64cbri, [SDNPHasChain]>;
def AArch64adrp : SDNode<"AArch64ISD::ADRP", SDTIntUnaryOp, []>;
def AArch64adr : SDNode<"AArch64ISD::ADR", SDTIntUnaryOp, []>;
def AArch64addlow : SDNode<"AArch64ISD::ADDlow", SDTIntBinOp, []>;
@@ -10481,6 +10486,10 @@ defm : PromoteBinaryv8f16Tov4f32<any_fdiv, FDIVv4f32>;
defm : PromoteBinaryv8f16Tov4f32<any_fmul, FMULv4f32>;
defm : PromoteBinaryv8f16Tov4f32<any_fsub, FSUBv4f32>;
+//===----------------------------------------------------------------------===//
+// Compare and Branch (FEAT_CMPBR)
+//===----------------------------------------------------------------------===//
+
let Predicates = [HasCMPBR] in {
defm CBGT : CmpBranchRegister<0b000, "cbgt">;
defm CBGE : CmpBranchRegister<0b001, "cbge">;
@@ -10529,6 +10538,22 @@ let Predicates = [HasCMPBR] in {
defm : CmpBranchWRegisterAlias<"cbhlo", "CBHHI">;
defm : CmpBranchWRegisterAlias<"cbhls", "CBHHS">;
defm : CmpBranchWRegisterAlias<"cbhlt", "CBHGT">;
+
+ // Pseudos for codegen
+ def CBWPrr : CmpBranchRegisterPseudo<GPR32>;
+ def CBXPrr : CmpBranchRegisterPseudo<GPR64>;
+ def CBWPri : CmpBranchImmediatePseudo<GPR32, uimm6_32b>;
+ def CBXPri : CmpBranchImmediatePseudo<GPR64, uimm6_64b>;
+
+def : Pat<(AArch64CBrr i32:$Cond, GPR32:$Rn, GPR32:$Rt, bb:$Target),
+ (CBWPrr ccode:$Cond, GPR32:$Rn, GPR32:$Rt, am_brcmpcond:$Target)>;
+def : Pat<(AArch64CBrr i32:$Cond, GPR64:$Rn, GPR64:$Rt, bb:$Target),
+ (CBXPrr ccode:$Cond, GPR64:$Rn, GPR64:$Rt, am_brcmpcond:$Target)>;
+def : Pat<(AArch64CBri i32:$Cond, GPR32:$Rn, i32:$Imm, bb:$Target),
+ (CBWPri ccode:$Cond, GPR32:$Rn, uimm6_32b:$Imm, am_brcmpcond:$Target)>;
+def : Pat<(AArch64CBri i32:$Cond, GPR64:$Rn, i64:$Imm, bb:$Target),
+ (CBXPri ccode:$Cond, GPR64:$Rn, uimm6_64b:$Imm, am_brcmpcond:$Target)>;
+
} // HasCMPBR
diff --git a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
index 8f34cf054fe286..417c152eebf24a 100644
--- a/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
+++ b/llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h
@@ -332,6 +332,26 @@ inline static unsigned getNZCVToSatisfyCondCode(CondCode Code) {
}
}
+/// True, if a given condition code can be used in a fused compare-and-branch
+/// instructions, false otherwise.
+inline static bool isValidCBCond(AArch64CC::CondCode Code) {
+ switch (Code) {
+ default:
+ return false;
+ case AArch64CC::EQ:
+ case AArch64CC::NE:
+ case AArch64CC::HS:
+ case AArch64CC::LO:
+ case AArch64CC::HI:
+ case AArch64CC::LS:
+ case AArch64CC::GE:
+ case AArch64CC::LT:
+ case AArch64CC::GT:
+ case AArch64CC::LE:
+ return true;
+ }
+}
+
} // end namespace AArch64CC
struct SysAlias {
diff --git a/llvm/test/CodeGen/AArch64/cmpbr-branch-relaxation.mir b/llvm/test/CodeGen/AArch64/cmpbr-branch-relaxation.mir
new file mode 100644
index 00000000000000..5fccb452e9642b
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/cmpbr-branch-relaxation.mir
@@ -0,0 +1,156 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple arm64-apple-ios -mattr +cmpbr -o - -aarch64-cb-offset-bits=3 \
+# RUN: -run-pass=branch-relaxation -verify-machineinstrs -simplify-mir %s | \
+# RUN: FileCheck -check-prefix=RELAX %s
+# RUN: llc -mtriple arm64-apple-ios -mattr +cmpbr -o - -aarch64-cb-offset-bits=9 \
+# RUN: -run-pass=branch-relaxation -verify-machineinstrs -simplify-mir %s | \
+# RUN: FileCheck -check-prefix=NO-RELAX %s
+---
+name: relax_cb
+registers:
+ - { id: 0, class: gpr32 }
+ - { id: 1, class: gpr32 }
+liveins:
+ - { reg: '$w0', virtual-reg: '%0' }
+ - { reg: '$w1', virtual-reg: '%1' }
+body: |
+ ; RELAX-LABEL: name: relax_cb
+ ; RELAX: bb.0:
+ ; RELAX-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+ ; RELAX-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; RELAX-NEXT: CBWPrr 1, [[COPY]], [[COPY1]], %bb.1
+ ; RELAX-NEXT: B %bb.2
+ ; RELAX-NEXT: {{ $}}
+ ; RELAX-NEXT: bb.1:
+ ; RELAX-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
+ ; RELAX-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr]], [[COPY1]]
+ ; RELAX-NEXT: [[ADDWrr2:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr1]], [[ADDWrr]]
+ ; RELAX-NEXT: [[ADDWrr3:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr2]], [[ADDWrr1]]
+ ; RELAX-NEXT: [[ADDWrr4:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr3]], [[ADDWrr2]]
+ ; RELAX-NEXT: $w0 = ADDWrr [[ADDWrr4]], [[ADDWrr3]]
+ ; RELAX-NEXT: {{ $}}
+ ; RELAX-NEXT: bb.2:
+ ; RELAX-NEXT: RET_ReallyLR implicit $w0
+ ;
+ ; NO-RELAX-LABEL: name: relax_cb
+ ; NO-RELAX: bb.0:
+ ; NO-RELAX-NEXT: successors: %bb.1, %bb.2
+ ; NO-RELAX-NEXT: {{ $}}
+ ; NO-RELAX-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+ ; NO-RELAX-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; NO-RELAX-NEXT: CBWPrr 0, [[COPY]], [[COPY1]], %bb.2
+ ; NO-RELAX-NEXT: {{ $}}
+ ; NO-RELAX-NEXT: bb.1:
+ ; NO-RELAX-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
+ ; NO-RELAX-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr]], [[COPY1]]
+ ; NO-RELAX-NEXT: [[ADDWrr2:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr1]], [[ADDWrr]]
+ ; NO-RELAX-NEXT: [[ADDWrr3:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr2]], [[ADDWrr1]]
+ ; NO-RELAX-NEXT: [[ADDWrr4:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr3]], [[ADDWrr2]]
+ ; NO-RELAX-NEXT: $w0 = ADDWrr [[ADDWrr4]], [[ADDWrr3]]
+ ; NO-RELAX-NEXT: {{ $}}
+ ; NO-RELAX-NEXT: bb.2:
+ ; NO-RELAX-NEXT: RET_ReallyLR implicit $w0
+ bb.0:
+ successors: %bb.1, %bb.2
+ %0:gpr32 = COPY $w0
+ %1:gpr32 = COPY $w1
+ CBWPrr 0, %0, %1, %bb.2
+
+ bb.1:
+ successors: %bb.2
+ %2:gpr32 = ADDWrr %0, %1
+ %3:gpr32 = ADDWrr %2, %1
+ %4:gpr32 = ADDWrr %3, %2
+ %5:gpr32 = ADDWrr %4, %3
+ %6:gpr32 = ADDWrr %5, %4
+ $w0 = ADDWrr %6, %5
+
+ bb.2:
+ RET_ReallyLR implicit $w0
+...
+---
+name: relax_and_split_block
+tracksRegLiveness: true
+registers:
+ - { id: 0, class: gpr32 }
+ - { id: 1, class: gpr32 }
+liveins:
+ - { reg: '$w0', virtual-reg: '%0' }
+ - { reg: '$w1', virtual-reg: '%1' }
+body: |
+ ; RELAX-LABEL: name: relax_and_split_block
+ ; RELAX: bb.0:
+ ; RELAX-NEXT: liveins: $w0, $w1
+ ; RELAX-NEXT: {{ $}}
+ ; RELAX-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+ ; RELAX-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; RELAX-NEXT: CBWPrr 1, [[COPY]], [[COPY1]], %bb.3
+ ; RELAX-NEXT: B %bb.2
+ ; RELAX-NEXT: {{ $}}
+ ; RELAX-NEXT: bb.3:
+ ; RELAX-NEXT: liveins: $w0, $w1
+ ; RELAX-NEXT: {{ $}}
+ ; RELAX-NEXT: CBWPrr 0, [[COPY]], [[COPY1]], %bb.1
+ ; RELAX-NEXT: B %bb.2
+ ; RELAX-NEXT: {{ $}}
+ ; RELAX-NEXT: bb.1:
+ ; RELAX-NEXT: liveins: $w0, $w1
+ ; RELAX-NEXT: {{ $}}
+ ; RELAX-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
+ ; RELAX-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr]], [[COPY1]]
+ ; RELAX-NEXT: [[ADDWrr2:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr1]], [[ADDWrr]]
+ ; RELAX-NEXT: [[ADDWrr3:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr2]], [[ADDWrr1]]
+ ; RELAX-NEXT: [[ADDWrr4:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr3]], [[ADDWrr2]]
+ ; RELAX-NEXT: $w0 = ADDWrr [[ADDWrr4]], [[ADDWrr3]]
+ ; RELAX-NEXT: {{ $}}
+ ; RELAX-NEXT: bb.2:
+ ; RELAX-NEXT: liveins: $w0, $w1
+ ; RELAX-NEXT: {{ $}}
+ ; RELAX-NEXT: RET_ReallyLR implicit $w0
+ ;
+ ; NO-RELAX-LABEL: name: relax_and_split_block
+ ; NO-RELAX: bb.0:
+ ; NO-RELAX-NEXT: successors: %bb.1, %bb.2
+ ; NO-RELAX-NEXT: liveins: $w0, $w1
+ ; NO-RELAX-NEXT: {{ $}}
+ ; NO-RELAX-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
+ ; NO-RELAX-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
+ ; NO-RELAX-NEXT: CBWPrr 0, [[COPY]], [[COPY1]], %bb.2
+ ; NO-RELAX-NEXT: CBWPrr 1, [[COPY]], [[COPY1]], %bb.2
+ ; NO-RELAX-NEXT: {{ $}}
+ ; NO-RELAX-NEXT: bb.1:
+ ; NO-RELAX-NEXT: liveins: $w0, $w1
+ ; NO-RELAX-NEXT: {{ $}}
+ ; NO-RELAX-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]]
+ ; NO-RELAX-NEXT: [[ADDWrr1:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr]], [[COPY1]]
+ ; NO-RELAX-NEXT: [[ADDWrr2:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr1]], [[ADDWrr]]
+ ; NO-RELAX-NEXT: [[ADDWrr3:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr2]], [[ADDWrr1]]
+ ; NO-RELAX-NEXT: [[ADDWrr4:%[0-9]+]]:gpr32 = ADDWrr [[ADDWrr3]], [[ADDWrr2]]
+ ; NO-RELAX-NEXT: $w0 = ADDWrr [[ADDWrr4]], [[ADDWrr3]]
+ ; NO-RELAX-NEXT: {{ $}}
+ ; NO-RELAX-NEXT: bb.2:
+ ; NO-RELAX-NEXT: liveins: $w0, $w1
+ ; NO-RELAX-NEXT: {{ $}}
+ ; NO-RELAX-NEXT: RET_ReallyLR implicit $w0
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $w0, $w1
+ %0:gpr32 = COPY $w0
+ %1:gpr32 = COPY $w1
+ CBWPrr 0, %0, %1, %bb.2
+ CBWPrr 1, %0, %1, %bb.2
+
+ bb.1:
+ successors: %bb.2
+ liveins: $w0, $w1
+ %2:gpr32 = ADDWrr %0, %1
+ %3:gpr32 = ADDWrr %2, %1
+ %4:gpr32 = ADDWrr %3, %2
+ %5:gpr32 = ADDWrr %4, %3
+ %6:gpr32 = ADDWrr %5, %4
+ $w0 = ADDWrr %6, %5
+
+ bb.2:
+ liveins: $w0, $w1
+ RET_ReallyLR implicit $w0
+...
diff --git a/llvm/test/CodeGen/AArch64/cmpbr-early-ifcvt.mir b/llvm/test/CodeGen/AArch64/cmpbr-early-ifcvt.mir
new file mode 100644
index 00000000000000..f162f5aa9d324c
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/cmpbr-early-ifcvt.mir
@@ -0,0 +1,116 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=arm64-apple-ios -mattr +cmpbr -run-pass=early-ifcvt -simplify-mir -o - %s | FileCheck %s
+# CHECK: cbnz_diamond
+---
+name: cbnz_diamond
+alignment: 4
+tracksRegLiveness: true
+noPhis: false
+isSSA: true
+noVRegs: false
+hasFakeUses: false
+registers:
+ - { id: 0, class: gpr64 }
+ - { id: 1, class: gpr64 }
+ - { id: 2, class: gpr64 }
+ - { id: 3, class: gpr64 }
+ - { id: 4, class: gpr64 }
+ - { id: 5, class: gpr64 }
+liveins:
+ - { reg: '$x0', virtual-reg: '%0' }
+ - { reg: '$x1', virtual-reg: '%1' }
+frameInfo:
+ maxAlignment: 1
+ maxCallFrameSize: 0
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: cbnz_diamond
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY1]], $xzr
+ ; CHECK-NEXT: $xzr = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
+ ; CHECK-NEXT: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[ADDXrr]], [[MADDXrrr]], 11, implicit $nzcv
+ ; CHECK-NEXT: [[ADDXrr1:%[0-9]+]]:gpr64 = ADDXrr killed [[CSELXr]], [[COPY]]
+ ; CHECK-NEXT: $x0 = COPY [[ADDXrr1]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1
+
+ %0:gpr64 = COPY $x0
+ %1:gpr64 = COPY $x1
+ CBXPrr 11, %0, %1, %bb.1
+ B %bb.2
+
+ bb.1:
+ successors: %bb.3
+ %2:gpr64 = ADDXrr %0, %1
+ B %bb.3
+
+ bb.2:
+ successors: %bb.3
+ %3:gpr64 = MADDXrrr %0, %1, $xzr
+ B %bb.3
+
+ bb.3:
+ %4:gpr64 = PHI %2, %bb.1, %3, %bb.2
+ %5:gpr64 = ADDXrr killed %4, %0
+ $x0 = COPY %5
+ RET_ReallyLR implicit $x0
+...
+---
+name: cbnz_triangle
+alignment: 4
+tracksRegLiveness: true
+noPhis: false
+isSSA: true
+noVRegs: false
+hasFakeUses: false
+registers:
+ - { id: 0, class: gpr64 }
+ - { id: 1, class: gpr64 }
+ - { id: 2, class: gpr64 }
+ - { id: 3, class: gpr64 }
+ - { id: 4, class: gpr64 }
+liveins:
+ - { reg: '$x0', virtual-reg: '%0' }
+ - { reg: '$x1', virtual-reg: '%1' }
+frameInfo:
+ maxAlignment: 1
+ maxCallFrameSize: 0
+machineFunctionInfo: {}
+body: |
+ ; CHECK-LABEL: name: cbnz_triangle
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
+ ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $xzr = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
+ ; CHECK-NEXT: [[CSELXr:%[0-9]+]]:gpr64 = CSELXr [[COPY1]], [[ADDXrr]], 10, implicit $nzcv
+ ; CHECK-NEXT: [[ADDXrr1:%[0-9]+]]:gpr64 = ADDXrr killed [[CSELXr]], [[COPY]]
+ ; CHECK-NEXT: $x0 = COPY [[ADDXrr1]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $x0
+ bb.0:
+ successors: %bb.1, %bb.2
+ liveins: $x0, $x1
+
+ %0:gpr64 = COPY $x0
+ %1:gpr64 = COPY $x1
+ CBXPrr 10, %0, %1, %bb.2
+
+ bb.1:
+ successors: %bb.2
+ %2:gpr64 = ADDXrr %0, %1
+
+ bb.2:
+ %3:gpr64 = PHI %1, %bb.0, %2, %bb.1
+ %4:gpr64 = ADDXrr killed %3, %0
+ $x0 = COPY %4
+ RET_ReallyLR implicit $x0
+...
diff --git a/llvm/test/CodeGen/AArch64/cmpbr-reg-imm-bounds.ll b/llvm/test/CodeGen/AArch64/cmpbr-reg-imm-bounds.ll
new file mode 100644
index 00000000000000..b70c05c8f31f2f
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/cmpbr-reg-imm-bounds.ll
@@ -0,0 +1,66 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple arm64-apple-ios -mattr +cmpbr -verify-machineinstrs -o - < %s | FileCheck %s
+
+define void @cbge_out_of_upper_bound(i32 %a) {
+; CHECK-LABEL: cbge_out_of_upper_bound:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: mov w8, #71 ; =0x47
+; CHECK-NEXT: cbge w0, w8, LBB0_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB0_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp sgt i32 %a, 70
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbge_out_of_lower_bound(i32 %a) {
+; CHECK-LABEL: cbge_out_of_lower_bound:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: mov w8, #-10 ; =0xfffffff6
+; CHECK-NEXT: cbge w0, w8, LBB1_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB1_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp sge i32 %a, -10
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+; This should trigger a register swap.
+define void @cble_out_of_lower_bound(i32 %a) {
+; CHECK-LABEL: cble_out_of_lower_bound:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: mov w8, #-10 ; =0xfffffff6
+; CHECK-NEXT: cbhs w8, w0, LBB2_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB2_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp ule i32 %a, -10
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
diff --git a/llvm/test/CodeGen/AArch64/cmpbr-reg-imm.ll b/llvm/test/CodeGen/AArch64/cmpbr-reg-imm.ll
new file mode 100644
index 00000000000000..1b20e5d0430305
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/cmpbr-reg-imm.ll
@@ -0,0 +1,402 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple arm64-apple-ios -mattr +cmpbr -verify-machineinstrs -o - < %s | FileCheck %s
+
+define void @cbgt.i32(i32 %a) {
+; CHECK-LABEL: cbgt.i32:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbgt w0, #10, LBB0_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB0_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp sgt i32 %a, 10
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cblt.i32(i32 %a) {
+; CHECK-LABEL: cblt.i32:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cblt w0, #10, LBB1_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB1_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp slt i32 %a, 10
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbhi.i32(i32 %a) {
+; CHECK-LABEL: cbhi.i32:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbhi w0, #10, LBB2_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB2_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp ugt i32 %a, 10
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cblo.i32(i32 %a) {
+; CHECK-LABEL: cblo.i32:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cblo w0, #10, LBB3_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB3_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp ult i32 %a, 10
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbeq.i32(i32 %a) {
+; CHECK-LABEL: cbeq.i32:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbeq w0, #10, LBB4_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB4_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp eq i32 %a, 10
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbne.i32(i32 %a) {
+; CHECK-LABEL: cbne.i32:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbne w0, #10, LBB5_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB5_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp ne i32 %a, 10
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbge_gt_dec.i32(i32 %a) {
+; CHECK-LABEL: cbge_gt_dec.i32:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbgt w0, #9, LBB6_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB6_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp sge i32 %a, 10
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbhs_hi_dec.i32(i32 %a) {
+; CHECK-LABEL: cbhs_hi_dec.i32:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbhi w0, #9, LBB7_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB7_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp uge i32 %a, 10
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cble_lt_inc.i32(i32 %a) {
+; CHECK-LABEL: cble_lt_inc.i32:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cblt w0, #11, LBB8_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB8_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp sle i32 %a, 10
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbls_lo_inc.i32(i32 %a) {
+; CHECK-LABEL: cbls_lo_inc.i32:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cblo w0, #11, LBB9_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB9_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp ule i32 %a, 10
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbgt.i64(i64 %a) {
+; CHECK-LABEL: cbgt.i64:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbgt x0, #10, LBB10_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB10_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp sgt i64 %a, 10
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cblt.i64(i64 %a) {
+; CHECK-LABEL: cblt.i64:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cblt x0, #10, LBB11_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB11_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp slt i64 %a, 10
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbhi.i64(i64 %a) {
+; CHECK-LABEL: cbhi.i64:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbhi x0, #10, LBB12_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB12_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp ugt i64 %a, 10
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cblo.i64(i64 %a) {
+; CHECK-LABEL: cblo.i64:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cblo x0, #10, LBB13_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB13_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp ult i64 %a, 10
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbeq.i64(i64 %a) {
+; CHECK-LABEL: cbeq.i64:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbeq x0, #10, LBB14_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB14_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp eq i64 %a, 10
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbne.i64(i64 %a) {
+; CHECK-LABEL: cbne.i64:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbne x0, #10, LBB15_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB15_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp ne i64 %a, 10
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbge_gt_dec.i64(i64 %a) {
+; CHECK-LABEL: cbge_gt_dec.i64:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbgt x0, #9, LBB16_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB16_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp sge i64 %a, 10
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbhs_hi_dec.i64(i64 %a) {
+; CHECK-LABEL: cbhs_hi_dec.i64:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbhi x0, #9, LBB17_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB17_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp uge i64 %a, 10
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cble_lt_inc.i64(i64 %a) {
+; CHECK-LABEL: cble_lt_inc.i64:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cblt x0, #11, LBB18_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB18_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp sle i64 %a, 10
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbls_lo_inc.i64(i64 %a) {
+; CHECK-LABEL: cbls_lo_inc.i64:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cblo x0, #11, LBB19_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB19_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp ule i64 %a, 10
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
diff --git a/llvm/test/CodeGen/AArch64/cmpbr-reg-reg.ll b/llvm/test/CodeGen/AArch64/cmpbr-reg-reg.ll
new file mode 100644
index 00000000000000..9790f5dd5678fd
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/cmpbr-reg-reg.ll
@@ -0,0 +1,405 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple arm64-apple-ios -mattr +cmpbr -verify-machineinstrs -o - < %s | FileCheck %s
+
+
+define void @cbgt.i32(i32 %a, i32 %b) {
+; CHECK-LABEL: cbgt.i32:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbgt w0, w1, LBB0_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB0_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp sgt i32 %a, %b
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbge.i32(i32 %a, i32 %b) {
+; CHECK-LABEL: cbge.i32:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbge w0, w1, LBB1_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB1_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp sge i32 %a, %b
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+
+define void @cbhi.i32(i32 %a, i32 %b) {
+; CHECK-LABEL: cbhi.i32:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbhi w0, w1, LBB2_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB2_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp ugt i32 %a, %b
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbhs.i32(i32 %a, i32 %b) {
+; CHECK-LABEL: cbhs.i32:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbhs w0, w1, LBB3_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB3_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp uge i32 %a, %b
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbeq.i32(i32 %a, i32 %b) {
+; CHECK-LABEL: cbeq.i32:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbeq w0, w1, LBB4_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB4_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp eq i32 %a, %b
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbne.i32(i32 %a, i32 %b) {
+; CHECK-LABEL: cbne.i32:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbne w0, w1, LBB5_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB5_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp ne i32 %a, %b
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cble_ge_swap.i32(i32 %a, i32 %b) {
+; CHECK-LABEL: cble_ge_swap.i32:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbge w1, w0, LBB6_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB6_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp sle i32 %a, %b
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cblo_hi_swap.i32(i32 %a, i32 %b) {
+; CHECK-LABEL: cblo_hi_swap.i32:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbhi w1, w0, LBB7_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB7_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp ult i32 %a, %b
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbls_hs_swap.i32(i32 %a, i32 %b) {
+; CHECK-LABEL: cbls_hs_swap.i32:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbhs w1, w0, LBB8_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB8_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp ule i32 %a, %b
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cblt_gt_swap.i32(i32 %a, i32 %b) {
+; CHECK-LABEL: cblt_gt_swap.i32:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbgt w1, w0, LBB9_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB9_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp slt i32 %a, %b
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbgt.i64(i64 %a, i64 %b) {
+; CHECK-LABEL: cbgt.i64:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbgt x0, x1, LBB10_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB10_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp sgt i64 %a, %b
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbge.i64(i64 %a, i64 %b) {
+; CHECK-LABEL: cbge.i64:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbge x0, x1, LBB11_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB11_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp sge i64 %a, %b
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+
+define void @cbhi.i64(i64 %a, i64 %b) {
+; CHECK-LABEL: cbhi.i64:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbhi x0, x1, LBB12_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB12_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp ugt i64 %a, %b
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbhs.i64(i64 %a, i64 %b) {
+; CHECK-LABEL: cbhs.i64:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbhs x0, x1, LBB13_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB13_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp uge i64 %a, %b
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbeq.i64(i64 %a, i64 %b) {
+; CHECK-LABEL: cbeq.i64:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbeq x0, x1, LBB14_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB14_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp eq i64 %a, %b
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbne.i64(i64 %a, i64 %b) {
+; CHECK-LABEL: cbne.i64:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbne x0, x1, LBB15_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB15_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp ne i64 %a, %b
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cble_ge_swap.i64(i64 %a, i64 %b) {
+; CHECK-LABEL: cble_ge_swap.i64:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbge x1, x0, LBB16_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB16_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp sle i64 %a, %b
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cblo_hi_swap.i64(i64 %a, i64 %b) {
+; CHECK-LABEL: cblo_hi_swap.i64:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbhi x1, x0, LBB17_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB17_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp ult i64 %a, %b
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cbls_hs_swap.i64(i64 %a, i64 %b) {
+; CHECK-LABEL: cbls_hs_swap.i64:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbhs x1, x0, LBB18_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB18_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp ule i64 %a, %b
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
+
+define void @cblt_gt_swap.i64(i64 %a, i64 %b) {
+; CHECK-LABEL: cblt_gt_swap.i64:
+; CHECK: ; %bb.0: ; %entry
+; CHECK-NEXT: cbgt x1, x0, LBB19_2
+; CHECK-NEXT: ; %bb.1: ; %if.end
+; CHECK-NEXT: ret
+; CHECK-NEXT: LBB19_2: ; %if.then
+; CHECK-NEXT: brk #0x1
+entry:
+ %cmp = icmp slt i64 %a, %b
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then:
+ tail call void @llvm.trap()
+ unreachable
+
+if.end:
+ ret void
+}
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