[llvm] [RISCV] Enable bidirectional postra scheduling (PR #115864)

[Min-Yih Hsu via llvm-commits]

mshockwave wrote:

> I got some results on different platforms.
> 
> 1. Coremark with 60000 iterations on GEM5: `-O3 -march=rv64gc` (use this configuration so there are more instructions to schedule and GEM5 has a better support)
> 
> * RiscvO3CPU
> 
> Baseline	TopDown	BottomUp	Bidirectional
> Cycles	33140248616	33031782179	33173323700	33063777692
> IPC	1.381871	1.386409	1.380822	1.383095
> * RiscvAtomicSimpleCPU
> 
> Baseline	TopDown	BottomUp	Bidirectional
> Cycles	30563561357	30935303916	30898754397	30563777692
> IPC	0.879774	0.869409	0.870437	0.879768
> 2. Coremark on Spacemit-X60 (`-O3 -mcpu=spacemit-x60`):
> 
> Baseline	TopDown	BottomUp	Bidirectional
> Iterations/Sec	4763.71	4993.34	4730.50	4853.86
> The results differ on different platforms so it is really hard to determine a default value. I will make it a target feature and leave the default value to be `Bidirectional` (this can be debated).

I have no objection making it into a tuning feature.

https://github.com/llvm/llvm-project/pull/115864