[llvm] 798a894 - [SystemZ] Fix address operand parsing incompatibilities with GAS
Ulrich Weigand via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 15 08:39:20 PST 2024
Author: Ulrich Weigand
Date: 2024-11-15T17:39:04+01:00
New Revision: 798a8941824dc2f83a169812e0edf7971d5f772b
URL: https://github.com/llvm/llvm-project/commit/798a8941824dc2f83a169812e0edf7971d5f772b
DIFF: https://github.com/llvm/llvm-project/commit/798a8941824dc2f83a169812e0edf7971d5f772b.diff
LOG: [SystemZ] Fix address operand parsing incompatibilities with GAS
The LLVM AsmParser showed different behavior compared to GAS when
parsing address operands in the following two ways:
- If the address operand only has a single register (no comma),
it is always interpreted as base register by GAS, even in the
vector-index case (vgef etc.) This means the following is
actually incorrect usage, as the base cannot be a vector
register: vgef %v0, 0(%v1), 0.
- GAS allows specifying a missing base register by using a
comma after the first register, e.g. vgef %v0, 0(%v1,), 0.
Added:
Modified:
llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
llvm/test/MC/SystemZ/insn-bad-z13.s
llvm/test/MC/SystemZ/insn-good-z13.s
llvm/test/MC/SystemZ/insn-good.s
llvm/test/MC/SystemZ/tokens.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
index b8469a6ba70eaf..e4aefc42d860f2 100644
--- a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
+++ b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
@@ -1071,9 +1071,16 @@ bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1,
if (getLexer().is(AsmToken::Integer)) {
if (parseIntegerRegister(Reg2, RegGR))
return true;
- } else {
- if (isParsingGNU() && parseRegister(Reg2, /*RequirePercent=*/true))
- return true;
+ } else if (isParsingGNU()) {
+ if (Parser.getTok().is(AsmToken::Percent)) {
+ if (parseRegister(Reg2, /*RequirePercent=*/true))
+ return true;
+ } else {
+ // GAS allows ",)" to indicate a missing base register.
+ Reg2.Num = 0;
+ Reg2.Group = RegGR;
+ Reg2.StartLoc = Reg2.EndLoc = Parser.getTok().getLoc();
+ }
}
}
@@ -1186,6 +1193,10 @@ ParseStatus SystemZAsmParser::parseAddress(OperandVector &Operands,
if (!HaveReg1 || Reg1.Group != RegV)
return Error(StartLoc, "vector index required in address");
Index = SystemZMC::VR128Regs[Reg1.Num];
+ // In GAS mode, we must have Reg2, since a single register would be
+ // interpreted as base register, which cannot be a vector register.
+ if (isParsingGNU() && !HaveReg2)
+ return Error(Reg1.StartLoc, "invalid use of vector addressing");
// If we have Reg2, it must be an address register.
if (HaveReg2) {
if (parseAddressRegister(Reg2))
diff --git a/llvm/test/MC/SystemZ/insn-bad-z13.s b/llvm/test/MC/SystemZ/insn-bad-z13.s
index 46aebc75e4fabd..5cce8a3b28cb49 100644
--- a/llvm/test/MC/SystemZ/insn-bad-z13.s
+++ b/llvm/test/MC/SystemZ/insn-bad-z13.s
@@ -1470,6 +1470,10 @@
#CHECK: vgef %v0, 0(%r1), 0
#CHECK: error: vector index required
#CHECK: vgef %v0, 0(%r2,%r1), 0
+#CHECK: error: invalid use of vector addressing
+#CHECK: vgef %v0, 0(%v1), 0
+#CHECK: error: vector index required
+#CHECK: vgef %v0, 0(,%v1), 0
#CHECK: error: invalid operand
#CHECK: vgef %v0, 0(%v0,%r1), -1
#CHECK: error: invalid operand
@@ -1481,6 +1485,8 @@
vgef %v0, 0(%r1), 0
vgef %v0, 0(%r2,%r1), 0
+ vgef %v0, 0(%v1), 0
+ vgef %v0, 0(,%v1), 0
vgef %v0, 0(%v0,%r1), -1
vgef %v0, 0(%v0,%r1), 4
vgef %v0, -1(%v0,%r1), 0
@@ -1490,6 +1496,10 @@
#CHECK: vgeg %v0, 0(%r1), 0
#CHECK: error: vector index required
#CHECK: vgeg %v0, 0(%r2,%r1), 0
+#CHECK: error: invalid use of vector addressing
+#CHECK: vgeg %v0, 0(%v1), 0
+#CHECK: error: vector index required
+#CHECK: vgeg %v0, 0(,%v1), 0
#CHECK: error: invalid operand
#CHECK: vgeg %v0, 0(%v0,%r1), -1
#CHECK: error: invalid operand
@@ -1501,6 +1511,8 @@
vgeg %v0, 0(%r1), 0
vgeg %v0, 0(%r2,%r1), 0
+ vgeg %v0, 0(%v1), 0
+ vgeg %v0, 0(,%v1), 0
vgeg %v0, 0(%v0,%r1), -1
vgeg %v0, 0(%v0,%r1), 2
vgeg %v0, -1(%v0,%r1), 0
@@ -2282,6 +2294,10 @@
#CHECK: vscef %v0, 0(%r1), 0
#CHECK: error: vector index required
#CHECK: vscef %v0, 0(%r2,%r1), 0
+#CHECK: error: invalid use of vector addressing
+#CHECK: vscef %v0, 0(%v1), 0
+#CHECK: error: vector index required
+#CHECK: vscef %v0, 0(,%v1), 0
#CHECK: error: invalid operand
#CHECK: vscef %v0, 0(%v0,%r1), -1
#CHECK: error: invalid operand
@@ -2293,6 +2309,8 @@
vscef %v0, 0(%r1), 0
vscef %v0, 0(%r2,%r1), 0
+ vscef %v0, 0(%v1), 0
+ vscef %v0, 0(,%v1), 0
vscef %v0, 0(%v0,%r1), -1
vscef %v0, 0(%v0,%r1), 4
vscef %v0, -1(%v0,%r1), 0
@@ -2302,6 +2320,10 @@
#CHECK: vsceg %v0, 0(%r1), 0
#CHECK: error: vector index required
#CHECK: vsceg %v0, 0(%r2,%r1), 0
+#CHECK: error: invalid use of vector addressing
+#CHECK: vsceg %v0, 0(%v1), 0
+#CHECK: error: vector index required
+#CHECK: vsceg %v0, 0(,%v1), 0
#CHECK: error: invalid operand
#CHECK: vsceg %v0, 0(%v0,%r1), -1
#CHECK: error: invalid operand
@@ -2313,6 +2335,8 @@
vsceg %v0, 0(%r1), 0
vsceg %v0, 0(%r2,%r1), 0
+ vsceg %v0, 0(%v1), 0
+ vsceg %v0, 0(,%v1), 0
vsceg %v0, 0(%v0,%r1), -1
vsceg %v0, 0(%v0,%r1), 2
vsceg %v0, -1(%v0,%r1), 0
diff --git a/llvm/test/MC/SystemZ/insn-good-z13.s b/llvm/test/MC/SystemZ/insn-good-z13.s
index 709a95512c5211..1c16cf8ec0b459 100644
--- a/llvm/test/MC/SystemZ/insn-good-z13.s
+++ b/llvm/test/MC/SystemZ/insn-good-z13.s
@@ -2918,6 +2918,7 @@
vgbm %v31, 0
vgbm %v17, 0x1234
+#CHECK: vgef %v0, 0(%v0,0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x13]
#CHECK: vgef %v0, 0(%v0,0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x13]
#CHECK: vgef %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x13]
#CHECK: vgef %v0, 0(%v0,%r1), 3 # encoding: [0xe7,0x00,0x10,0x00,0x30,0x13]
@@ -2943,7 +2944,8 @@
#CHECK: vgef %v31, 0(%v0,%r1), 0 # encoding: [0xe7,0xf0,0x10,0x00,0x08,0x13]
#CHECK: vgef %v10, 1000(%v19,%r7), 1 # encoding: [0xe7,0xa3,0x73,0xe8,0x14,0x13]
- vgef %v0, 0(%v0), 0
+ vgef %v0, 0(%v0,), 0
+ vgef %v0, 0(%v0,0), 0
vgef %v0, 0(%v0,%r1), 0
vgef %v0, 0(%v0,%r1), 3
vgef %v0, 0(%v0,%r15), 0
@@ -2957,7 +2959,7 @@
vgef %v0, 0(%v0,1), 3
vgef %v0, 0(0,%r15), 0
vgef %v0, 0(%v15,1), 0
- vgef 0, 0(0), 0
+ vgef 0, 0(0,), 0
vgef 0, 0(0,1), 0
vgef 0, 0(0,1), 3
vgef 0, 0(0,15), 0
@@ -2968,6 +2970,7 @@
vgef 31, 0(0,1), 0
vgef 10, 1000(19,7), 1
+#CHECK: vgeg %v0, 0(%v0,0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x12]
#CHECK: vgeg %v0, 0(%v0,0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x12]
#CHECK: vgeg %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x12]
#CHECK: vgeg %v0, 0(%v0,%r1), 1 # encoding: [0xe7,0x00,0x10,0x00,0x10,0x12]
@@ -2993,7 +2996,8 @@
#CHECK: vgeg %v31, 0(%v0,%r1), 0 # encoding: [0xe7,0xf0,0x10,0x00,0x08,0x12]
#CHECK: vgeg %v10, 1000(%v19,%r7), 1 # encoding: [0xe7,0xa3,0x73,0xe8,0x14,0x12]
- vgeg %v0, 0(%v0), 0
+ vgeg %v0, 0(%v0,), 0
+ vgeg %v0, 0(%v0,0), 0
vgeg %v0, 0(%v0,%r1), 0
vgeg %v0, 0(%v0,%r1), 1
vgeg %v0, 0(%v0,%r15), 0
@@ -3007,7 +3011,7 @@
vgeg %v0, 0(%v0,1), 1
vgeg %v0, 0(0,%r15), 0
vgeg %v0, 0(%v15,1), 0
- vgeg 0, 0(0), 0
+ vgeg 0, 0(0,), 0
vgeg 0, 0(0,1), 0
vgeg 0, 0(0,1), 1
vgeg 0, 0(0,15), 0
@@ -5950,6 +5954,7 @@
vscbiq %v31, %v0, %v0
vscbiq %v18, %v3, %v20
+#CHECK: vscef %v0, 0(%v0,0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x1b]
#CHECK: vscef %v0, 0(%v0,0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x1b]
#CHECK: vscef %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x1b]
#CHECK: vscef %v0, 0(%v0,%r1), 3 # encoding: [0xe7,0x00,0x10,0x00,0x30,0x1b]
@@ -5961,7 +5966,8 @@
#CHECK: vscef %v31, 0(%v0,%r1), 0 # encoding: [0xe7,0xf0,0x10,0x00,0x08,0x1b]
#CHECK: vscef %v10, 1000(%v19,%r7), 1 # encoding: [0xe7,0xa3,0x73,0xe8,0x14,0x1b]
- vscef %v0, 0(%v0), 0
+ vscef %v0, 0(%v0,), 0
+ vscef %v0, 0(%v0,0), 0
vscef %v0, 0(%v0,%r1), 0
vscef %v0, 0(%v0,%r1), 3
vscef %v0, 0(%v0,%r15), 0
@@ -5972,6 +5978,7 @@
vscef %v31, 0(%v0,%r1), 0
vscef %v10, 1000(%v19,%r7), 1
+#CHECK: vsceg %v0, 0(%v0,0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x1a]
#CHECK: vsceg %v0, 0(%v0,0), 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x1a]
#CHECK: vsceg %v0, 0(%v0,%r1), 0 # encoding: [0xe7,0x00,0x10,0x00,0x00,0x1a]
#CHECK: vsceg %v0, 0(%v0,%r1), 1 # encoding: [0xe7,0x00,0x10,0x00,0x10,0x1a]
@@ -5983,7 +5990,8 @@
#CHECK: vsceg %v31, 0(%v0,%r1), 0 # encoding: [0xe7,0xf0,0x10,0x00,0x08,0x1a]
#CHECK: vsceg %v10, 1000(%v19,%r7), 1 # encoding: [0xe7,0xa3,0x73,0xe8,0x14,0x1a]
- vsceg %v0, 0(%v0), 0
+ vsceg %v0, 0(%v0,), 0
+ vsceg %v0, 0(%v0,0), 0
vsceg %v0, 0(%v0,%r1), 0
vsceg %v0, 0(%v0,%r1), 1
vsceg %v0, 0(%v0,%r15), 0
diff --git a/llvm/test/MC/SystemZ/insn-good.s b/llvm/test/MC/SystemZ/insn-good.s
index 90f06dc0b9a9a7..09f55049546c21 100644
--- a/llvm/test/MC/SystemZ/insn-good.s
+++ b/llvm/test/MC/SystemZ/insn-good.s
@@ -8918,6 +8918,8 @@
#CHECK: l %r0, 0(%r15,0) # encoding: [0x58,0x0f,0x00,0x00]
#CHECK: l %r0, 0(%r1,0) # encoding: [0x58,0x01,0x00,0x00]
#CHECK: l %r0, 0(%r15,0) # encoding: [0x58,0x0f,0x00,0x00]
+#CHECK: l %r0, 0(%r1,0) # encoding: [0x58,0x01,0x00,0x00]
+#CHECK: l %r0, 0(%r15,0) # encoding: [0x58,0x0f,0x00,0x00]
#CHECK: l %r0, 4095(%r15) # encoding: [0x58,0x00,0xff,0xff]
#CHECK: l %r0, 4095(%r1,%r15) # encoding: [0x58,0x01,0xff,0xff]
#CHECK: l %r0, 4095(%r15,0) # encoding: [0x58,0x0f,0x0f,0xff]
@@ -8937,6 +8939,8 @@
l %r0, 0(%r0,%r15)
l %r0, 0(0,%r1)
l %r0, 0(0,%r15)
+ l %r0, 0(%r1,)
+ l %r0, 0(%r15,)
l %r0, 0(%r1,0)
l %r0, 0(%r15,0)
l %r0, 0(%r1,%r0)
diff --git a/llvm/test/MC/SystemZ/tokens.s b/llvm/test/MC/SystemZ/tokens.s
index bf8c4e9067856c..6dca865e763ad8 100644
--- a/llvm/test/MC/SystemZ/tokens.s
+++ b/llvm/test/MC/SystemZ/tokens.s
@@ -7,7 +7,7 @@
#CHECK: foo 100(, 200
#CHECK: error: invalid instruction
#CHECK: foo 100(200), 300
-#CHECK: error: register expected
+#CHECK: error: invalid instruction
#CHECK: foo 100(200,), 300
#CHECK: error: invalid instruction
#CHECK: foo 100(200,%r1), 300
@@ -59,7 +59,7 @@
#CHECK: foo {, 200
#CHECK: error: invalid instruction
#CHECK: foo 100(15), 300
-#CHECK: error: register expected
+#CHECK: error: invalid instruction
#CHECK: foo 100(15,), 300
#CHECK: error: invalid instruction
#CHECK: foo 100(15,%r1), 300
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