[llvm] 35710ab - [SystemZ] Fix wrong register class for some DFP instructions
Ulrich Weigand via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 15 05:52:45 PST 2024
Author: Ulrich Weigand
Date: 2024-11-15T14:52:29+01:00
New Revision: 35710ab392b50c815765f03c12409147502dfb86
URL: https://github.com/llvm/llvm-project/commit/35710ab392b50c815765f03c12409147502dfb86
DIFF: https://github.com/llvm/llvm-project/commit/35710ab392b50c815765f03c12409147502dfb86.diff
LOG: [SystemZ] Fix wrong register class for some DFP instructions
Certain DFP instructions have GPR arguments, which are currently
incorrectly treated as FPR registers. Since we do not use DFP
in codegen, this only affects the assembler and disassembler.
Added:
Modified:
llvm/lib/Target/SystemZ/SystemZInstrDFP.td
llvm/test/MC/Disassembler/SystemZ/insns.txt
llvm/test/MC/SystemZ/insn-bad.s
llvm/test/MC/SystemZ/insn-good.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrDFP.td b/llvm/lib/Target/SystemZ/SystemZInstrDFP.td
index 8d7a773ff4d9dd..3db076899d7358 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrDFP.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrDFP.td
@@ -129,12 +129,12 @@ let Uses = [FPC] in {
}
// Extract biased exponent.
-def EEDTR : UnaryRRE<"eedtr", 0xB3E5, null_frag, FP64, FP64>;
-def EEXTR : UnaryRRE<"eextr", 0xB3ED, null_frag, FP128, FP128>;
+def EEDTR : UnaryRRE<"eedtr", 0xB3E5, null_frag, GR64, FP64>;
+def EEXTR : UnaryRRE<"eextr", 0xB3ED, null_frag, GR64, FP128>;
// Extract significance.
-def ESDTR : UnaryRRE<"esdtr", 0xB3E7, null_frag, FP64, FP64>;
-def ESXTR : UnaryRRE<"esxtr", 0xB3EF, null_frag, FP128, FP128>;
+def ESDTR : UnaryRRE<"esdtr", 0xB3E7, null_frag, GR64, FP64>;
+def ESXTR : UnaryRRE<"esxtr", 0xB3EF, null_frag, GR64, FP128>;
//===----------------------------------------------------------------------===//
@@ -193,8 +193,8 @@ let Uses = [FPC] in {
// Reround.
let Uses = [FPC] in {
- def RRDTR : TernaryRRFb<"rrdtr", 0xB3F7, FP64, FP64, FP64>;
- def RRXTR : TernaryRRFb<"rrxtr", 0xB3FF, FP128, FP128, FP128>;
+ def RRDTR : TernaryRRFb<"rrdtr", 0xB3F7, FP64, GR32, FP64>;
+ def RRXTR : TernaryRRFb<"rrxtr", 0xB3FF, FP128, GR32, FP128>;
}
// Shift significand left/right.
@@ -204,8 +204,8 @@ def SRDT : BinaryRXF<"srdt", 0xED41, null_frag, FP64, FP64, null_frag, 0>;
def SRXT : BinaryRXF<"srxt", 0xED49, null_frag, FP128, FP128, null_frag, 0>;
// Insert biased exponent.
-def IEDTR : BinaryRRFb<"iedtr", 0xB3F6, null_frag, FP64, FP64, FP64>;
-def IEXTR : BinaryRRFb<"iextr", 0xB3FE, null_frag, FP128, FP128, FP128>;
+def IEDTR : BinaryRRFb<"iedtr", 0xB3F6, null_frag, FP64, GR64, FP64>;
+def IEXTR : BinaryRRFb<"iextr", 0xB3FE, null_frag, FP128, GR64, FP128>;
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/Disassembler/SystemZ/insns.txt b/llvm/test/MC/Disassembler/SystemZ/insns.txt
index 392993d4e2a36a..07a1ff6d183885 100644
--- a/llvm/test/MC/Disassembler/SystemZ/insns.txt
+++ b/llvm/test/MC/Disassembler/SystemZ/insns.txt
@@ -6439,28 +6439,28 @@
# CHECK: edmk 0(256,%r15), 0
0xdf 0xff 0xf0 0x00 0x00 0x00
-# CHECK: eedtr %f0, %f9
+# CHECK: eedtr %r0, %f9
0xb3 0xe5 0x00 0x09
-# CHECK: eedtr %f0, %f15
+# CHECK: eedtr %r0, %f15
0xb3 0xe5 0x00 0x0f
-# CHECK: eedtr %f15, %f0
+# CHECK: eedtr %r15, %f0
0xb3 0xe5 0x00 0xf0
-# CHECK: eedtr %f15, %f9
+# CHECK: eedtr %r15, %f9
0xb3 0xe5 0x00 0xf9
-# CHECK: eextr %f0, %f8
+# CHECK: eextr %r0, %f8
0xb3 0xed 0x00 0x08
-# CHECK: eextr %f0, %f13
+# CHECK: eextr %r0, %f13
0xb3 0xed 0x00 0x0d
-# CHECK: eextr %f13, %f0
+# CHECK: eextr %r13, %f0
0xb3 0xed 0x00 0xd0
-# CHECK: eextr %f13, %f9
+# CHECK: eextr %r13, %f9
0xb3 0xed 0x00 0xd9
# CHECK: efpc %r0
@@ -6556,16 +6556,16 @@
# CHECK: esair %r15
0xb9 0x9b 0x00 0xf0
-# CHECK: esdtr %f0, %f9
+# CHECK: esdtr %r0, %f9
0xb3 0xe7 0x00 0x09
-# CHECK: esdtr %f0, %f15
+# CHECK: esdtr %r0, %f15
0xb3 0xe7 0x00 0x0f
-# CHECK: esdtr %f15, %f0
+# CHECK: esdtr %r15, %f0
0xb3 0xe7 0x00 0xf0
-# CHECK: esdtr %f15, %f9
+# CHECK: esdtr %r15, %f9
0xb3 0xe7 0x00 0xf9
# CHECK: esea %r0
@@ -6589,16 +6589,16 @@
# CHECK: esta %r6, %r8
0xb2 0x4a 0x00 0x68
-# CHECK: esxtr %f0, %f8
+# CHECK: esxtr %r0, %f8
0xb3 0xef 0x00 0x08
-# CHECK: esxtr %f0, %f13
+# CHECK: esxtr %r0, %f13
0xb3 0xef 0x00 0x0d
-# CHECK: esxtr %f13, %f0
+# CHECK: esxtr %r13, %f0
0xb3 0xef 0x00 0xd0
-# CHECK: esxtr %f13, %f9
+# CHECK: esxtr %r13, %f9
0xb3 0xef 0x00 0xd9
# CHECK: etnd %r0
@@ -7000,40 +7000,40 @@
# CHECK: idte %r4, %r5, %r6, 7
0xb9 0x8e 0x57 0x46
-# CHECK: iedtr %f0, %f0, %f0
+# CHECK: iedtr %f0, %f0, %r0
0xb3 0xf6 0x00 0x00
-# CHECK: iedtr %f0, %f0, %f15
+# CHECK: iedtr %f0, %f0, %r15
0xb3 0xf6 0x00 0x0f
-# CHECK: iedtr %f0, %f15, %f0
+# CHECK: iedtr %f0, %f15, %r0
0xb3 0xf6 0xf0 0x00
-# CHECK: iedtr %f15, %f0, %f0
+# CHECK: iedtr %f15, %f0, %r0
0xb3 0xf6 0x00 0xf0
-# CHECK: iedtr %f1, %f2, %f3
+# CHECK: iedtr %f1, %f2, %r3
0xb3 0xf6 0x20 0x13
-# CHECK: iedtr %f15, %f15, %f15
+# CHECK: iedtr %f15, %f15, %r15
0xb3 0xf6 0xf0 0xff
-# CHECK: iextr %f0, %f0, %f0
+# CHECK: iextr %f0, %f0, %r0
0xb3 0xfe 0x00 0x00
-# CHECK: iextr %f0, %f0, %f13
+# CHECK: iextr %f0, %f0, %r13
0xb3 0xfe 0x00 0x0d
-# CHECK: iextr %f0, %f13, %f0
+# CHECK: iextr %f0, %f13, %r0
0xb3 0xfe 0xd0 0x00
-# CHECK: iextr %f13, %f0, %f0
+# CHECK: iextr %f13, %f0, %r0
0xb3 0xfe 0x00 0xd0
-# CHECK: iextr %f1, %f8, %f4
+# CHECK: iextr %f1, %f8, %r4
0xb3 0xfe 0x80 0x14
-# CHECK: iextr %f13, %f13, %f13
+# CHECK: iextr %f13, %f13, %r13
0xb3 0xfe 0xd0 0xdd
# CHECK: iihf %r0, 0
@@ -14220,40 +14220,40 @@
# CHECK: rrbm %r15, %r15
0xb9 0xae 0x00 0xff
-# CHECK: rrdtr %f0, %f0, %f0, 0
+# CHECK: rrdtr %f0, %f0, %r0, 0
0xb3 0xf7 0x00 0x00
-# CHECK: rrdtr %f0, %f0, %f0, 15
+# CHECK: rrdtr %f0, %f0, %r0, 15
0xb3 0xf7 0x0f 0x00
-# CHECK: rrdtr %f0, %f0, %f15, 0
+# CHECK: rrdtr %f0, %f0, %r15, 0
0xb3 0xf7 0x00 0x0f
-# CHECK: rrdtr %f0, %f15, %f0, 0
+# CHECK: rrdtr %f0, %f15, %r0, 0
0xb3 0xf7 0xf0 0x00
-# CHECK: rrdtr %f4, %f5, %f6, 7
+# CHECK: rrdtr %f4, %f5, %r6, 7
0xb3 0xf7 0x57 0x46
-# CHECK: rrdtr %f15, %f0, %f0, 0
+# CHECK: rrdtr %f15, %f0, %r0, 0
0xb3 0xf7 0x00 0xf0
-# CHECK: rrxtr %f0, %f0, %f0, 0
+# CHECK: rrxtr %f0, %f0, %r0, 0
0xb3 0xff 0x00 0x00
-# CHECK: rrxtr %f0, %f0, %f0, 15
+# CHECK: rrxtr %f0, %f0, %r0, 15
0xb3 0xff 0x0f 0x00
-# CHECK: rrxtr %f0, %f0, %f13, 0
+# CHECK: rrxtr %f0, %f0, %r13, 0
0xb3 0xff 0x00 0x0d
-# CHECK: rrxtr %f0, %f13, %f0, 0
+# CHECK: rrxtr %f0, %f13, %r0, 0
0xb3 0xff 0xd0 0x00
-# CHECK: rrxtr %f8, %f8, %f8, 8
+# CHECK: rrxtr %f8, %f8, %r8, 8
0xb3 0xff 0x88 0x88
-# CHECK: rrxtr %f13, %f0, %f0, 0
+# CHECK: rrxtr %f13, %f0, %r0, 0
0xb3 0xff 0x00 0xd0
# CHECK: rsch
diff --git a/llvm/test/MC/SystemZ/insn-bad.s b/llvm/test/MC/SystemZ/insn-bad.s
index f81278610c73a6..6e1ceb7a4914fb 100644
--- a/llvm/test/MC/SystemZ/insn-bad.s
+++ b/llvm/test/MC/SystemZ/insn-bad.s
@@ -2794,12 +2794,9 @@
edmk 0(-), 0
#CHECK: error: invalid register pair
-#CHECK: eextr %f0, %f2
-#CHECK: error: invalid register pair
-#CHECK: eextr %f2, %f0
+#CHECK: eextr %r0, %f2
- eextr %f0, %f2
- eextr %f2, %f0
+ eextr %r0, %f2
#CHECK: error: invalid register pair
#CHECK: esta %r1, %r0
@@ -2807,12 +2804,9 @@
esta %r1, %r0
#CHECK: error: invalid register pair
-#CHECK: esxtr %f0, %f2
-#CHECK: error: invalid register pair
-#CHECK: esxtr %f2, %f0
+#CHECK: esxtr %r0, %f2
- esxtr %f0, %f2
- esxtr %f2, %f0
+ esxtr %r0, %f2
#CHECK: error: invalid operand
#CHECK: ex %r0, -1
@@ -2981,15 +2975,12 @@
idte %r0, %r0, %r0, 16
#CHECK: error: invalid register pair
-#CHECK: iextr %f0, %f0, %f2
+#CHECK: iextr %f0, %f2, %r0
#CHECK: error: invalid register pair
-#CHECK: iextr %f0, %f2, %f0
-#CHECK: error: invalid register pair
-#CHECK: iextr %f2, %f0, %f0
+#CHECK: iextr %f2, %f0, %r0
- iextr %f0, %f0, %f2
- iextr %f0, %f2, %f0
- iextr %f2, %f0, %f0
+ iextr %f0, %f2, %r0
+ iextr %f2, %f0, %r0
#CHECK: error: invalid operand
#CHECK: iihf %r0, -1
@@ -5688,29 +5679,26 @@
rrbm %r0, %r0
#CHECK: error: invalid operand
-#CHECK: rrdtr %f0, %f0, %f0, -1
+#CHECK: rrdtr %f0, %f0, %r0, -1
#CHECK: error: invalid operand
-#CHECK: rrdtr %f0, %f0, %f0, 16
+#CHECK: rrdtr %f0, %f0, %r0, 16
- rrdtr %f0, %f0, %f0, -1
- rrdtr %f0, %f0, %f0, 16
+ rrdtr %f0, %f0, %r0, -1
+ rrdtr %f0, %f0, %r0, 16
#CHECK: error: invalid operand
-#CHECK: rrxtr %f0, %f0, %f0, -1
+#CHECK: rrxtr %f0, %f0, %r0, -1
#CHECK: error: invalid operand
-#CHECK: rrxtr %f0, %f0, %f0, 16
-#CHECK: error: invalid register pair
-#CHECK: rrxtr %f0, %f0, %f2, 0
+#CHECK: rrxtr %f0, %f0, %r0, 16
#CHECK: error: invalid register pair
-#CHECK: rrxtr %f0, %f2, %f0, 0
+#CHECK: rrxtr %f0, %f2, %r0, 0
#CHECK: error: invalid register pair
-#CHECK: rrxtr %f2, %f0, %f0, 0
+#CHECK: rrxtr %f2, %f0, %r0, 0
- rrxtr %f0, %f0, %f0, -1
- rrxtr %f0, %f0, %f0, 16
- rrxtr %f0, %f0, %f2, 0
- rrxtr %f0, %f2, %f0, 0
- rrxtr %f2, %f0, %f0, 0
+ rrxtr %f0, %f0, %r0, -1
+ rrxtr %f0, %f0, %r0, 16
+ rrxtr %f0, %f2, %r0, 0
+ rrxtr %f2, %f0, %r0, 0
#CHECK: error: invalid operand
#CHECK: rxsbg %r0,%r0,0,-1,0
diff --git a/llvm/test/MC/SystemZ/insn-good.s b/llvm/test/MC/SystemZ/insn-good.s
index 553c1b281eb4d3..90f06dc0b9a9a7 100644
--- a/llvm/test/MC/SystemZ/insn-good.s
+++ b/llvm/test/MC/SystemZ/insn-good.s
@@ -8200,25 +8200,25 @@
edmk 0(256,%r1), 0
edmk 0(256,%r15), 0
-#CHECK: eedtr %f0, %f9 # encoding: [0xb3,0xe5,0x00,0x09]
-#CHECK: eedtr %f0, %f15 # encoding: [0xb3,0xe5,0x00,0x0f]
-#CHECK: eedtr %f15, %f0 # encoding: [0xb3,0xe5,0x00,0xf0]
-#CHECK: eedtr %f15, %f9 # encoding: [0xb3,0xe5,0x00,0xf9]
-
- eedtr %f0,%f9
- eedtr %f0,%f15
- eedtr %f15,%f0
- eedtr %f15,%f9
-
-#CHECK: eextr %f0, %f8 # encoding: [0xb3,0xed,0x00,0x08]
-#CHECK: eextr %f0, %f13 # encoding: [0xb3,0xed,0x00,0x0d]
-#CHECK: eextr %f13, %f0 # encoding: [0xb3,0xed,0x00,0xd0]
-#CHECK: eextr %f13, %f9 # encoding: [0xb3,0xed,0x00,0xd9]
-
- eextr %f0,%f8
- eextr %f0,%f13
- eextr %f13,%f0
- eextr %f13,%f9
+#CHECK: eedtr %r0, %f9 # encoding: [0xb3,0xe5,0x00,0x09]
+#CHECK: eedtr %r0, %f15 # encoding: [0xb3,0xe5,0x00,0x0f]
+#CHECK: eedtr %r15, %f0 # encoding: [0xb3,0xe5,0x00,0xf0]
+#CHECK: eedtr %r15, %f9 # encoding: [0xb3,0xe5,0x00,0xf9]
+
+ eedtr %r0,%f9
+ eedtr %r0,%f15
+ eedtr %r15,%f0
+ eedtr %r15,%f9
+
+#CHECK: eextr %r0, %f8 # encoding: [0xb3,0xed,0x00,0x08]
+#CHECK: eextr %r0, %f13 # encoding: [0xb3,0xed,0x00,0x0d]
+#CHECK: eextr %r13, %f0 # encoding: [0xb3,0xed,0x00,0xd0]
+#CHECK: eextr %r13, %f9 # encoding: [0xb3,0xed,0x00,0xd9]
+
+ eextr %r0,%f8
+ eextr %r0,%f13
+ eextr %r13,%f0
+ eextr %r13,%f9
#CHECK: efpc %r0 # encoding: [0xb3,0x8c,0x00,0x00]
#CHECK: efpc %r1 # encoding: [0xb3,0x8c,0x00,0x10]
@@ -8300,15 +8300,15 @@
esair %r1
esair %r15
-#CHECK: esdtr %f0, %f9 # encoding: [0xb3,0xe7,0x00,0x09]
-#CHECK: esdtr %f0, %f15 # encoding: [0xb3,0xe7,0x00,0x0f]
-#CHECK: esdtr %f15, %f0 # encoding: [0xb3,0xe7,0x00,0xf0]
-#CHECK: esdtr %f15, %f9 # encoding: [0xb3,0xe7,0x00,0xf9]
+#CHECK: esdtr %r0, %f9 # encoding: [0xb3,0xe7,0x00,0x09]
+#CHECK: esdtr %r0, %f15 # encoding: [0xb3,0xe7,0x00,0x0f]
+#CHECK: esdtr %r15, %f0 # encoding: [0xb3,0xe7,0x00,0xf0]
+#CHECK: esdtr %r15, %f9 # encoding: [0xb3,0xe7,0x00,0xf9]
- esdtr %f0,%f9
- esdtr %f0,%f15
- esdtr %f15,%f0
- esdtr %f15,%f9
+ esdtr %r0,%f9
+ esdtr %r0,%f15
+ esdtr %r15,%f0
+ esdtr %r15,%f9
#CHECK: esea %r0 # encoding: [0xb9,0x9d,0x00,0x00]
#CHECK: esea %r1 # encoding: [0xb9,0x9d,0x00,0x10]
@@ -8328,15 +8328,15 @@
esta %r14,%r0
esta %r6,%r8
-#CHECK: esxtr %f0, %f8 # encoding: [0xb3,0xef,0x00,0x08]
-#CHECK: esxtr %f0, %f13 # encoding: [0xb3,0xef,0x00,0x0d]
-#CHECK: esxtr %f13, %f0 # encoding: [0xb3,0xef,0x00,0xd0]
-#CHECK: esxtr %f13, %f9 # encoding: [0xb3,0xef,0x00,0xd9]
+#CHECK: esxtr %r0, %f8 # encoding: [0xb3,0xef,0x00,0x08]
+#CHECK: esxtr %r0, %f13 # encoding: [0xb3,0xef,0x00,0x0d]
+#CHECK: esxtr %r13, %f0 # encoding: [0xb3,0xef,0x00,0xd0]
+#CHECK: esxtr %r13, %f9 # encoding: [0xb3,0xef,0x00,0xd9]
- esxtr %f0,%f8
- esxtr %f0,%f13
- esxtr %f13,%f0
- esxtr %f13,%f9
+ esxtr %r0,%f8
+ esxtr %r0,%f13
+ esxtr %r13,%f0
+ esxtr %r13,%f9
#CHECK: ex %r0, 0 # encoding: [0x44,0x00,0x00,0x00]
#CHECK: ex %r0, 4095 # encoding: [0x44,0x00,0x0f,0xff]
@@ -8639,33 +8639,33 @@
idte %r0, %r0, %r0, 15
idte %r4, %r5, %r6, 7
-#CHECK: iedtr %f0, %f0, %f0 # encoding: [0xb3,0xf6,0x00,0x00]
-#CHECK: iedtr %f0, %f0, %f15 # encoding: [0xb3,0xf6,0x00,0x0f]
-#CHECK: iedtr %f0, %f15, %f0 # encoding: [0xb3,0xf6,0xf0,0x00]
-#CHECK: iedtr %f15, %f0, %f0 # encoding: [0xb3,0xf6,0x00,0xf0]
-#CHECK: iedtr %f1, %f2, %f3 # encoding: [0xb3,0xf6,0x20,0x13]
-#CHECK: iedtr %f15, %f15, %f15 # encoding: [0xb3,0xf6,0xf0,0xff]
-
- iedtr %f0, %f0, %f0
- iedtr %f0, %f0, %f15
- iedtr %f0, %f15, %f0
- iedtr %f15, %f0, %f0
- iedtr %f1, %f2, %f3
- iedtr %f15, %f15, %f15
-
-#CHECK: iextr %f0, %f0, %f0 # encoding: [0xb3,0xfe,0x00,0x00]
-#CHECK: iextr %f0, %f0, %f13 # encoding: [0xb3,0xfe,0x00,0x0d]
-#CHECK: iextr %f0, %f13, %f0 # encoding: [0xb3,0xfe,0xd0,0x00]
-#CHECK: iextr %f13, %f0, %f0 # encoding: [0xb3,0xfe,0x00,0xd0]
-#CHECK: iextr %f1, %f8, %f4 # encoding: [0xb3,0xfe,0x80,0x14]
-#CHECK: iextr %f13, %f13, %f13 # encoding: [0xb3,0xfe,0xd0,0xdd]
-
- iextr %f0, %f0, %f0
- iextr %f0, %f0, %f13
- iextr %f0, %f13, %f0
- iextr %f13, %f0, %f0
- iextr %f1, %f8, %f4
- iextr %f13, %f13, %f13
+#CHECK: iedtr %f0, %f0, %r0 # encoding: [0xb3,0xf6,0x00,0x00]
+#CHECK: iedtr %f0, %f0, %r15 # encoding: [0xb3,0xf6,0x00,0x0f]
+#CHECK: iedtr %f0, %f15, %r0 # encoding: [0xb3,0xf6,0xf0,0x00]
+#CHECK: iedtr %f15, %f0, %r0 # encoding: [0xb3,0xf6,0x00,0xf0]
+#CHECK: iedtr %f1, %f2, %r3 # encoding: [0xb3,0xf6,0x20,0x13]
+#CHECK: iedtr %f15, %f15, %r15 # encoding: [0xb3,0xf6,0xf0,0xff]
+
+ iedtr %f0, %f0, %r0
+ iedtr %f0, %f0, %r15
+ iedtr %f0, %f15, %r0
+ iedtr %f15, %f0, %r0
+ iedtr %f1, %f2, %r3
+ iedtr %f15, %f15, %r15
+
+#CHECK: iextr %f0, %f0, %r0 # encoding: [0xb3,0xfe,0x00,0x00]
+#CHECK: iextr %f0, %f0, %r13 # encoding: [0xb3,0xfe,0x00,0x0d]
+#CHECK: iextr %f0, %f13, %r0 # encoding: [0xb3,0xfe,0xd0,0x00]
+#CHECK: iextr %f13, %f0, %r0 # encoding: [0xb3,0xfe,0x00,0xd0]
+#CHECK: iextr %f1, %f8, %r4 # encoding: [0xb3,0xfe,0x80,0x14]
+#CHECK: iextr %f13, %f13, %r13 # encoding: [0xb3,0xfe,0xd0,0xdd]
+
+ iextr %f0, %f0, %r0
+ iextr %f0, %f0, %r13
+ iextr %f0, %f13, %r0
+ iextr %f13, %f0, %r0
+ iextr %f1, %f8, %r4
+ iextr %f13, %f13, %r13
#CHECK: iihf %r0, 0 # encoding: [0xc0,0x08,0x00,0x00,0x00,0x00]
#CHECK: iihf %r0, 4294967295 # encoding: [0xc0,0x08,0xff,0xff,0xff,0xff]
@@ -13839,33 +13839,33 @@
rrbe %r7,%r8
rrbe %r15,%r15
-#CHECK: rrdtr %f0, %f0, %f0, 0 # encoding: [0xb3,0xf7,0x00,0x00]
-#CHECK: rrdtr %f0, %f0, %f0, 15 # encoding: [0xb3,0xf7,0x0f,0x00]
-#CHECK: rrdtr %f0, %f0, %f15, 0 # encoding: [0xb3,0xf7,0x00,0x0f]
-#CHECK: rrdtr %f0, %f15, %f0, 0 # encoding: [0xb3,0xf7,0xf0,0x00]
-#CHECK: rrdtr %f4, %f5, %f6, 7 # encoding: [0xb3,0xf7,0x57,0x46]
-#CHECK: rrdtr %f15, %f0, %f0, 0 # encoding: [0xb3,0xf7,0x00,0xf0]
-
- rrdtr %f0, %f0, %f0, 0
- rrdtr %f0, %f0, %f0, 15
- rrdtr %f0, %f0, %f15, 0
- rrdtr %f0, %f15, %f0, 0
- rrdtr %f4, %f5, %f6, 7
- rrdtr %f15, %f0, %f0, 0
-
-#CHECK: rrxtr %f0, %f0, %f0, 0 # encoding: [0xb3,0xff,0x00,0x00]
-#CHECK: rrxtr %f0, %f0, %f0, 15 # encoding: [0xb3,0xff,0x0f,0x00]
-#CHECK: rrxtr %f0, %f0, %f13, 0 # encoding: [0xb3,0xff,0x00,0x0d]
-#CHECK: rrxtr %f0, %f13, %f0, 0 # encoding: [0xb3,0xff,0xd0,0x00]
-#CHECK: rrxtr %f8, %f8, %f8, 8 # encoding: [0xb3,0xff,0x88,0x88]
-#CHECK: rrxtr %f13, %f0, %f0, 0 # encoding: [0xb3,0xff,0x00,0xd0]
-
- rrxtr %f0, %f0, %f0, 0
- rrxtr %f0, %f0, %f0, 15
- rrxtr %f0, %f0, %f13, 0
- rrxtr %f0, %f13, %f0, 0
- rrxtr %f8, %f8, %f8, 8
- rrxtr %f13, %f0, %f0, 0
+#CHECK: rrdtr %f0, %f0, %r0, 0 # encoding: [0xb3,0xf7,0x00,0x00]
+#CHECK: rrdtr %f0, %f0, %r0, 15 # encoding: [0xb3,0xf7,0x0f,0x00]
+#CHECK: rrdtr %f0, %f0, %r15, 0 # encoding: [0xb3,0xf7,0x00,0x0f]
+#CHECK: rrdtr %f0, %f15, %r0, 0 # encoding: [0xb3,0xf7,0xf0,0x00]
+#CHECK: rrdtr %f4, %f5, %r6, 7 # encoding: [0xb3,0xf7,0x57,0x46]
+#CHECK: rrdtr %f15, %f0, %r0, 0 # encoding: [0xb3,0xf7,0x00,0xf0]
+
+ rrdtr %f0, %f0, %r0, 0
+ rrdtr %f0, %f0, %r0, 15
+ rrdtr %f0, %f0, %r15, 0
+ rrdtr %f0, %f15, %r0, 0
+ rrdtr %f4, %f5, %r6, 7
+ rrdtr %f15, %f0, %r0, 0
+
+#CHECK: rrxtr %f0, %f0, %r0, 0 # encoding: [0xb3,0xff,0x00,0x00]
+#CHECK: rrxtr %f0, %f0, %r0, 15 # encoding: [0xb3,0xff,0x0f,0x00]
+#CHECK: rrxtr %f0, %f0, %r13, 0 # encoding: [0xb3,0xff,0x00,0x0d]
+#CHECK: rrxtr %f0, %f13, %r0, 0 # encoding: [0xb3,0xff,0xd0,0x00]
+#CHECK: rrxtr %f8, %f8, %r8, 8 # encoding: [0xb3,0xff,0x88,0x88]
+#CHECK: rrxtr %f13, %f0, %r0, 0 # encoding: [0xb3,0xff,0x00,0xd0]
+
+ rrxtr %f0, %f0, %r0, 0
+ rrxtr %f0, %f0, %r0, 15
+ rrxtr %f0, %f0, %r13, 0
+ rrxtr %f0, %f13, %r0, 0
+ rrxtr %f8, %f8, %r8, 8
+ rrxtr %f13, %f0, %r0, 0
#CHECK: rsch # encoding: [0xb2,0x38,0x00,0x00]
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