[llvm] [RISCV] Change vector tuple type's TypeSize to scalable (PR #114329)

Brandon Wu via llvm-commits llvm-commits at lists.llvm.org
Fri Nov 15 00:10:29 PST 2024


https://github.com/4vtomat updated https://github.com/llvm/llvm-project/pull/114329

>From b00291190f2224394afad2a0576cef49ad4abf50 Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Wed, 30 Oct 2024 16:36:49 -0700
Subject: [PATCH 1/6] [RISCV] Change vector tuple type's TypeSize to scalable

Vector tuple is basically multiple grouped vector, so its size is also
determined by vscale, we need not to model it as a vector type but its
size need to be scalable.
---
 llvm/include/llvm/CodeGen/ValueTypes.td     |  1 +
 llvm/lib/CodeGen/ValueTypes.cpp             |  2 +-
 llvm/lib/CodeGenTypes/LowLevelType.cpp      |  5 +++
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 47 ++++++++++++---------
 4 files changed, 34 insertions(+), 21 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/ValueTypes.td b/llvm/include/llvm/CodeGen/ValueTypes.td
index 6d6b92958b4321..ee1b31703e12b9 100644
--- a/llvm/include/llvm/CodeGen/ValueTypes.td
+++ b/llvm/include/llvm/CodeGen/ValueTypes.td
@@ -63,6 +63,7 @@ class VTVecTup<int size, int nf, ValueType dummy_elt, int value>
   let NF = nf;
   let ElementType = dummy_elt;
   let isRISCVVecTuple = true;
+  let isScalable = true;
 }
 
 defset list<ValueType> ValueTypes = {
diff --git a/llvm/lib/CodeGen/ValueTypes.cpp b/llvm/lib/CodeGen/ValueTypes.cpp
index e3c746b274dde1..2c80eee7c904c1 100644
--- a/llvm/lib/CodeGen/ValueTypes.cpp
+++ b/llvm/lib/CodeGen/ValueTypes.cpp
@@ -163,7 +163,7 @@ std::string EVT::getEVTString() const {
   switch (V.SimpleTy) {
   default:
     if (isRISCVVectorTuple()) {
-      unsigned Sz = getSizeInBits();
+      unsigned Sz = getSizeInBits().getKnownMinValue();
       unsigned NF = getRISCVVectorTupleNumFields();
       unsigned MinNumElts = Sz / (NF * 8);
       return "riscv_nxv" + utostr(MinNumElts) + "i8x" + utostr(NF);
diff --git a/llvm/lib/CodeGenTypes/LowLevelType.cpp b/llvm/lib/CodeGenTypes/LowLevelType.cpp
index 5530a2ea952dd9..a798d8855a4636 100644
--- a/llvm/lib/CodeGenTypes/LowLevelType.cpp
+++ b/llvm/lib/CodeGenTypes/LowLevelType.cpp
@@ -22,6 +22,11 @@ LLT::LLT(MVT VT) {
     init(/*IsPointer=*/false, asVector, /*IsScalar=*/!asVector,
          VT.getVectorElementCount(), VT.getVectorElementType().getSizeInBits(),
          /*AddressSpace=*/0);
+  } else if (VT.isRISCVVectorTuple()) {
+    // TODO: Correctly model RISC-V vector tuple type
+    init(/*IsPointer=*/false, /*IsVector=*/false, /*IsScalar=*/true,
+         ElementCount::getFixed(0), VT.getSizeInBits().getKnownMinValue(),
+         /*AddressSpace=*/0);
   } else if (VT.isValid() && !VT.isScalableTargetExtVT()) {
     // Aggregates are no different from real scalars as far as GlobalISel is
     // concerned.
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index af7a39b2580a37..210657a7481d08 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2416,8 +2416,9 @@ unsigned RISCVTargetLowering::getSubregIndexByMVT(MVT VT, unsigned Index) {
 unsigned RISCVTargetLowering::getRegClassIDForVecVT(MVT VT) {
   if (VT.isRISCVVectorTuple()) {
     unsigned NF = VT.getRISCVVectorTupleNumFields();
-    unsigned RegsPerField = std::max(1U, (unsigned)VT.getSizeInBits() /
-                                             (NF * RISCV::RVVBitsPerBlock));
+    unsigned RegsPerField =
+        std::max(1U, (unsigned)VT.getSizeInBits().getKnownMinValue() /
+                         (NF * RISCV::RVVBitsPerBlock));
     switch (RegsPerField) {
     case 1:
       if (NF == 2)
@@ -7006,7 +7007,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
       SDLoc DL(Op);
       MVT XLenVT = Subtarget.getXLenVT();
       unsigned NF = VecTy.getRISCVVectorTupleNumFields();
-      unsigned Sz = VecTy.getSizeInBits();
+      unsigned Sz = VecTy.getSizeInBits().getKnownMinValue();
       unsigned NumElts = Sz / (NF * 8);
       int Log2LMUL = Log2_64(NumElts) - 3;
 
@@ -7049,7 +7050,7 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
       SDLoc DL(Op);
       MVT XLenVT = Subtarget.getXLenVT();
       unsigned NF = VecTy.getRISCVVectorTupleNumFields();
-      unsigned Sz = VecTy.getSizeInBits();
+      unsigned Sz = VecTy.getSizeInBits().getKnownMinValue();
       unsigned NumElts = Sz / (NF * 8);
       int Log2LMUL = Log2_64(NumElts) - 3;
 
@@ -21309,6 +21310,25 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
     return true;
   }
 
+  if (ValueVT.isRISCVVectorTuple() && PartVT.isRISCVVectorTuple()) {
+    unsigned ValNF = ValueVT.getRISCVVectorTupleNumFields();
+    [[maybe_unused]] unsigned ValLMUL =
+        divideCeil(ValueVT.getSizeInBits().getKnownMinValue(),
+                   ValNF * RISCV::RVVBitsPerBlock);
+    unsigned PartNF = PartVT.getRISCVVectorTupleNumFields();
+    [[maybe_unused]] unsigned PartLMUL =
+        divideCeil(PartVT.getSizeInBits().getKnownMinValue(),
+                   PartNF * RISCV::RVVBitsPerBlock);
+    assert(ValNF == PartNF && ValLMUL == PartLMUL &&
+           "RISC-V vector tuple type only accepts same register class type "
+           "TUPLE_INSERT");
+
+    Val = DAG.getNode(RISCVISD::TUPLE_INSERT, DL, PartVT, DAG.getUNDEF(PartVT),
+                      Val, DAG.getVectorIdxConstant(0, DL));
+    Parts[0] = Val;
+    return true;
+  }
+
   if (ValueVT.isScalableVector() && PartVT.isScalableVector()) {
     LLVMContext &Context = *DAG.getContext();
     EVT ValueEltVT = ValueVT.getVectorElementType();
@@ -21344,22 +21364,6 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
     }
   }
 
-  if (ValueVT.isRISCVVectorTuple() && PartVT.isRISCVVectorTuple()) {
-    unsigned ValNF = ValueVT.getRISCVVectorTupleNumFields();
-    [[maybe_unused]] unsigned ValLMUL =
-        divideCeil(ValueVT.getSizeInBits(), ValNF * RISCV::RVVBitsPerBlock);
-    unsigned PartNF = PartVT.getRISCVVectorTupleNumFields();
-    [[maybe_unused]] unsigned PartLMUL =
-        divideCeil(PartVT.getSizeInBits(), PartNF * RISCV::RVVBitsPerBlock);
-    assert(ValNF == PartNF && ValLMUL == PartLMUL &&
-           "RISC-V vector tuple type only accepts same register class type "
-           "TUPLE_INSERT");
-
-    Val = DAG.getNode(RISCVISD::TUPLE_INSERT, DL, PartVT, DAG.getUNDEF(PartVT),
-                      Val, DAG.getVectorIdxConstant(0, DL));
-    Parts[0] = Val;
-    return true;
-  }
   return false;
 }
 
@@ -21378,6 +21382,9 @@ SDValue RISCVTargetLowering::joinRegisterPartsIntoValue(
     return Val;
   }
 
+  if (ValueVT.isRISCVVectorTuple())
+    return SDValue();
+
   if (ValueVT.isScalableVector() && PartVT.isScalableVector()) {
     LLVMContext &Context = *DAG.getContext();
     SDValue Val = Parts[0];

>From 2abaaf667ab5532152ce3b38a81a388a061e2e5b Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Wed, 30 Oct 2024 17:35:31 -0700
Subject: [PATCH 2/6] fixup! [RISCV] Change vector tuple type's TypeSize to
 scalable

---
 llvm/include/llvm/CodeGen/ValueTypes.h            | 3 ++-
 llvm/include/llvm/CodeGen/ValueTypes.td           | 1 -
 llvm/include/llvm/CodeGenTypes/MachineValueType.h | 4 +++-
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/ValueTypes.h b/llvm/include/llvm/CodeGen/ValueTypes.h
index 4de109739227ad..c24434617f8713 100644
--- a/llvm/include/llvm/CodeGen/ValueTypes.h
+++ b/llvm/include/llvm/CodeGen/ValueTypes.h
@@ -185,7 +185,8 @@ namespace llvm {
 
     /// Return true if the type is a scalable type.
     bool isScalableVT() const {
-      return isScalableVector() || isScalableTargetExtVT();
+      return isScalableVector() || isScalableTargetExtVT() ||
+             isRISCVVectorTuple();
     }
 
     /// Return true if this is a 16-bit vector type.
diff --git a/llvm/include/llvm/CodeGen/ValueTypes.td b/llvm/include/llvm/CodeGen/ValueTypes.td
index ee1b31703e12b9..6d6b92958b4321 100644
--- a/llvm/include/llvm/CodeGen/ValueTypes.td
+++ b/llvm/include/llvm/CodeGen/ValueTypes.td
@@ -63,7 +63,6 @@ class VTVecTup<int size, int nf, ValueType dummy_elt, int value>
   let NF = nf;
   let ElementType = dummy_elt;
   let isRISCVVecTuple = true;
-  let isScalable = true;
 }
 
 defset list<ValueType> ValueTypes = {
diff --git a/llvm/include/llvm/CodeGenTypes/MachineValueType.h b/llvm/include/llvm/CodeGenTypes/MachineValueType.h
index 5c47ad4824a791..8bf83cd6179584 100644
--- a/llvm/include/llvm/CodeGenTypes/MachineValueType.h
+++ b/llvm/include/llvm/CodeGenTypes/MachineValueType.h
@@ -306,12 +306,14 @@ namespace llvm {
     /// be set and the runtime size will be a positive integer multiple of the
     /// base size.
     TypeSize getSizeInBits() const {
+      // clang-format off
       static constexpr TypeSize SizeTable[] = {
 #define GET_VT_ATTR(Ty, N, Sz, Any, Int, FP, Vec, Sc, Tup, NF, NElem, EltTy) \
-    TypeSize(Sz, Sc || Ty == aarch64svcount /* FIXME: Not in the td. */),
+    TypeSize(Sz, Sc || Tup || Ty == aarch64svcount /* FIXME: Not in the td. */),
 #include "llvm/CodeGen/GenVT.inc"
 #undef GET_VT_ATTR
       };
+      // clang-format on
 
       switch (SimpleTy) {
       case INVALID_SIMPLE_VALUE_TYPE:

>From deab61a334758b6f964471a827f280b076e8c018 Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Wed, 30 Oct 2024 20:20:07 -0700
Subject: [PATCH 3/6] fixup! [RISCV] Change vector tuple type's TypeSize to
 scalable

---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 210657a7481d08..508e0724b11af6 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21382,9 +21382,6 @@ SDValue RISCVTargetLowering::joinRegisterPartsIntoValue(
     return Val;
   }
 
-  if (ValueVT.isRISCVVectorTuple())
-    return SDValue();
-
   if (ValueVT.isScalableVector() && PartVT.isScalableVector()) {
     LLVMContext &Context = *DAG.getContext();
     SDValue Val = Parts[0];

>From dc943a8f2b1d3c59d57d613cb8f063aa32aef394 Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Sat, 9 Nov 2024 19:43:53 -0800
Subject: [PATCH 4/6] fixup! [RISCV] Change vector tuple type's TypeSize to
 scalable

---
 llvm/include/llvm/CodeGen/ValueTypes.h            | 3 +--
 llvm/include/llvm/CodeGenTypes/MachineValueType.h | 2 +-
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/llvm/include/llvm/CodeGen/ValueTypes.h b/llvm/include/llvm/CodeGen/ValueTypes.h
index c24434617f8713..4de109739227ad 100644
--- a/llvm/include/llvm/CodeGen/ValueTypes.h
+++ b/llvm/include/llvm/CodeGen/ValueTypes.h
@@ -185,8 +185,7 @@ namespace llvm {
 
     /// Return true if the type is a scalable type.
     bool isScalableVT() const {
-      return isScalableVector() || isScalableTargetExtVT() ||
-             isRISCVVectorTuple();
+      return isScalableVector() || isScalableTargetExtVT();
     }
 
     /// Return true if this is a 16-bit vector type.
diff --git a/llvm/include/llvm/CodeGenTypes/MachineValueType.h b/llvm/include/llvm/CodeGenTypes/MachineValueType.h
index 8bf83cd6179584..acb3b95f355076 100644
--- a/llvm/include/llvm/CodeGenTypes/MachineValueType.h
+++ b/llvm/include/llvm/CodeGenTypes/MachineValueType.h
@@ -124,7 +124,7 @@ namespace llvm {
 
     /// Return true if this is a custom target type that has a scalable size.
     bool isScalableTargetExtVT() const {
-      return SimpleTy == MVT::aarch64svcount;
+      return SimpleTy == MVT::aarch64svcount || isRISCVVectorTuple();
     }
 
     /// Return true if the type is a scalable type.

>From 96d06d5846edf84822aaa4c0284f5ec470c381d5 Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Mon, 11 Nov 2024 18:28:43 -0800
Subject: [PATCH 5/6] fixup! [RISCV] Change vector tuple type's TypeSize to
 scalable

---
 llvm/lib/CodeGenTypes/LowLevelType.cpp | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/llvm/lib/CodeGenTypes/LowLevelType.cpp b/llvm/lib/CodeGenTypes/LowLevelType.cpp
index a798d8855a4636..5530a2ea952dd9 100644
--- a/llvm/lib/CodeGenTypes/LowLevelType.cpp
+++ b/llvm/lib/CodeGenTypes/LowLevelType.cpp
@@ -22,11 +22,6 @@ LLT::LLT(MVT VT) {
     init(/*IsPointer=*/false, asVector, /*IsScalar=*/!asVector,
          VT.getVectorElementCount(), VT.getVectorElementType().getSizeInBits(),
          /*AddressSpace=*/0);
-  } else if (VT.isRISCVVectorTuple()) {
-    // TODO: Correctly model RISC-V vector tuple type
-    init(/*IsPointer=*/false, /*IsVector=*/false, /*IsScalar=*/true,
-         ElementCount::getFixed(0), VT.getSizeInBits().getKnownMinValue(),
-         /*AddressSpace=*/0);
   } else if (VT.isValid() && !VT.isScalableTargetExtVT()) {
     // Aggregates are no different from real scalars as far as GlobalISel is
     // concerned.

>From 495edec839acd49f70fa1b278a21cdd2fcfec961 Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Fri, 15 Nov 2024 00:09:55 -0800
Subject: [PATCH 6/6] fixup! [RISCV] Change vector tuple type's TypeSize to
 scalable

---
 llvm/include/llvm/CodeGenTypes/MachineValueType.h | 5 ++---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp       | 2 ++
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/llvm/include/llvm/CodeGenTypes/MachineValueType.h b/llvm/include/llvm/CodeGenTypes/MachineValueType.h
index acb3b95f355076..c14abca027350d 100644
--- a/llvm/include/llvm/CodeGenTypes/MachineValueType.h
+++ b/llvm/include/llvm/CodeGenTypes/MachineValueType.h
@@ -306,14 +306,13 @@ namespace llvm {
     /// be set and the runtime size will be a positive integer multiple of the
     /// base size.
     TypeSize getSizeInBits() const {
-      // clang-format off
       static constexpr TypeSize SizeTable[] = {
 #define GET_VT_ATTR(Ty, N, Sz, Any, Int, FP, Vec, Sc, Tup, NF, NElem, EltTy) \
-    TypeSize(Sz, Sc || Tup || Ty == aarch64svcount /* FIXME: Not in the td. */),
+    TypeSize(Sz, Sc || Tup || Ty == aarch64svcount /* FIXME: Not in the td.    \
+                                                    */),
 #include "llvm/CodeGen/GenVT.inc"
 #undef GET_VT_ATTR
       };
-      // clang-format on
 
       switch (SimpleTy) {
       case INVALID_SIMPLE_VALUE_TYPE:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 508e0724b11af6..8d96327b36c113 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -21311,6 +21311,7 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
   }
 
   if (ValueVT.isRISCVVectorTuple() && PartVT.isRISCVVectorTuple()) {
+#ifndef NDEBUG
     unsigned ValNF = ValueVT.getRISCVVectorTupleNumFields();
     [[maybe_unused]] unsigned ValLMUL =
         divideCeil(ValueVT.getSizeInBits().getKnownMinValue(),
@@ -21322,6 +21323,7 @@ bool RISCVTargetLowering::splitValueIntoRegisterParts(
     assert(ValNF == PartNF && ValLMUL == PartLMUL &&
            "RISC-V vector tuple type only accepts same register class type "
            "TUPLE_INSERT");
+#endif
 
     Val = DAG.getNode(RISCVISD::TUPLE_INSERT, DL, PartVT, DAG.getUNDEF(PartVT),
                       Val, DAG.getVectorIdxConstant(0, DL));



More information about the llvm-commits mailing list