[llvm] [GlobalISel][ARM] Legalize reset_fpmode (PR #115859)

[Serge Pavlov via llvm-commits]

https://github.com/spavloff updated https://github.com/llvm/llvm-project/pull/115859

>From 0dac6d6425b1ddc79d782e9fdc27a2343417d17e Mon Sep 17 00:00:00 2001
From: Serge Pavlov <sepavloff at gmail.com>
Date: Tue, 12 Nov 2024 15:03:59 +0700
Subject: [PATCH 1/3] [GlobalISel][ARM] Legalize reset_fpmode

Implement lowering intrinsic `reset_fpmode` in Global Selector
for ARM target.
---
 llvm/lib/Target/ARM/ARMLegalizerInfo.cpp  | 13 +++++++++++++
 llvm/test/CodeGen/ARM/GlobalISel/fpenv.ll | 17 +++++++++++++++++
 2 files changed, 30 insertions(+)

diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
index 452e908fdad98f..e65ea24c0d23ec 100644
--- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -163,6 +163,7 @@ ARMLegalizerInfo::ARMLegalizerInfo(const ARMSubtarget &ST) : ST(ST) {
         .legalFor({s32});
     getActionDefinitionsBuilder(G_RESET_FPENV).alwaysLegal();
     getActionDefinitionsBuilder(G_SET_FPMODE).customFor({s32});
+    getActionDefinitionsBuilder(G_RESET_FPMODE).custom();
   } else {
     getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV})
         .libcallFor({s32, s64});
@@ -467,6 +468,18 @@ bool ARMLegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
     MIRBuilder.buildSetFPEnv(NewFPSCR);
     break;
   }
+  case G_RESET_FPMODE: {
+    // To get the default FP mode all control bits are cleared:
+    // FPSCR = FPSCR & (FPStatusBits | FPReservedBits)
+    LLT FPEnvTy = LLT::scalar(32);
+    auto FPEnv = MRI.createGenericVirtualRegister(FPEnvTy);
+    MIRBuilder.buildInstr(G_GET_FPENV).addDef({FPEnv});
+    auto NotModeBitMask = MIRBuilder.buildConstant(
+        FPEnvTy, ARM::FPStatusBits | ARM::FPReservedBits);
+    auto NewFPSCR = MIRBuilder.buildAnd(FPEnvTy, FPEnv, NotModeBitMask);
+    MIRBuilder.buildInstr(G_SET_FPENV).addUse(NewFPSCR.getReg(0));
+    break;
+  }
   }
 
   MI.eraseFromParent();
diff --git a/llvm/test/CodeGen/ARM/GlobalISel/fpenv.ll b/llvm/test/CodeGen/ARM/GlobalISel/fpenv.ll
index f8dba64e7a01a9..5aa97dafd94334 100644
--- a/llvm/test/CodeGen/ARM/GlobalISel/fpenv.ll
+++ b/llvm/test/CodeGen/ARM/GlobalISel/fpenv.ll
@@ -165,5 +165,22 @@ entry:
   ret void
 }
 
+define void @reset_fpmode() nounwind {
+; CHECK-LABEL: reset_fpmode:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmrs r0, fpscr
+; CHECK-NEXT:    ldr r1, .LCPI11_0
+; CHECK-NEXT:    and r0, r0, r1
+; CHECK-NEXT:    vmsr fpscr, r0
+; CHECK-NEXT:    mov pc, lr
+; CHECK-NEXT:    .p2align 2
+; CHECK-NEXT:  @ %bb.1:
+; CHECK-NEXT:  .LCPI11_0:
+; CHECK-NEXT:    .long 4160774399 @ 0xf80060ff
+entry:
+  call void @llvm.reset.fpmode()
+  ret void
+}
+
 attributes #0 = { nounwind "use-soft-float"="true" }
 

>From 3920d24a8f487ed69a3474f6f51be6ea4bd72700 Mon Sep 17 00:00:00 2001
From: Serge Pavlov <sepavloff at gmail.com>
Date: Wed, 13 Nov 2024 14:36:59 +0700
Subject: [PATCH 2/3] Address review comments

---
 llvm/lib/Target/ARM/ARMLegalizerInfo.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
index e65ea24c0d23ec..95e6423c2d06e6 100644
--- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -473,11 +473,11 @@ bool ARMLegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
     // FPSCR = FPSCR & (FPStatusBits | FPReservedBits)
     LLT FPEnvTy = LLT::scalar(32);
     auto FPEnv = MRI.createGenericVirtualRegister(FPEnvTy);
-    MIRBuilder.buildInstr(G_GET_FPENV).addDef({FPEnv});
+    MIRBuilder.buildGetFPEnv(FPEnv);
     auto NotModeBitMask = MIRBuilder.buildConstant(
         FPEnvTy, ARM::FPStatusBits | ARM::FPReservedBits);
     auto NewFPSCR = MIRBuilder.buildAnd(FPEnvTy, FPEnv, NotModeBitMask);
-    MIRBuilder.buildInstr(G_SET_FPENV).addUse(NewFPSCR.getReg(0));
+    MIRBuilder.buildSetFPEnv(NewFPSCR);
     break;
   }
   }

>From 53e4e0cfdc8f78f1c40551acb79c0d9b41fd6cb0 Mon Sep 17 00:00:00 2001
From: Serge Pavlov <sepavloff at gmail.com>
Date: Fri, 15 Nov 2024 14:47:33 +0700
Subject: [PATCH 3/3] Simplify code

---
 llvm/lib/Target/ARM/ARMLegalizerInfo.cpp | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
index 95e6423c2d06e6..fc12f050fa5a5f 100644
--- a/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
@@ -472,8 +472,7 @@ bool ARMLegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
     // To get the default FP mode all control bits are cleared:
     // FPSCR = FPSCR & (FPStatusBits | FPReservedBits)
     LLT FPEnvTy = LLT::scalar(32);
-    auto FPEnv = MRI.createGenericVirtualRegister(FPEnvTy);
-    MIRBuilder.buildGetFPEnv(FPEnv);
+    auto FPEnv = MIRBuilder.buildGetFPEnv(FPEnvTy);
     auto NotModeBitMask = MIRBuilder.buildConstant(
         FPEnvTy, ARM::FPStatusBits | ARM::FPReservedBits);
     auto NewFPSCR = MIRBuilder.buildAnd(FPEnvTy, FPEnv, NotModeBitMask);