[llvm] 196d5fd - [RISCV][GISel] Remove most patterns that look for a zext i32->i64 and another integer instruction.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-11-14T14:03:02-08:00
New Revision: 196d5fdff1cb7b600dcf11b5464be4fc72dba675

URL: https://github.com/llvm/llvm-project/commit/196d5fdff1cb7b600dcf11b5464be4fc72dba675
DIFF: https://github.com/llvm/llvm-project/commit/196d5fdff1cb7b600dcf11b5464be4fc72dba675.diff

LOG: [RISCV][GISel] Remove most patterns that look for a zext i32->i64 and another integer instruction.

For the most part integer code should promote G_ZEXT to G_AND now.
The exception may be when the G_ZEXT is fed by a bitcast from FP,
but we don't have any testing of that now.

I had to adjust one test that was looking for G_TRUNC+G_ZEXT instead
of G_AND.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVGISel.td
    llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVGISel.td b/llvm/lib/Target/RISCV/RISCVGISel.td
index d0fbe4d51b7d76..58eb28927251eb 100644
--- a/llvm/lib/Target/RISCV/RISCVGISel.td
+++ b/llvm/lib/Target/RISCV/RISCVGISel.td
@@ -197,11 +197,6 @@ def : Pat<(zext_is_sext GPR:$src), (ADDIW GPR:$src, 0)>;
 
 let Predicates = [IsRV64, NotHasStdExtZba] in {
 def : Pat<(zext GPR:$src), (SRLI (i64 (SLLI GPR:$src, 32)), 32)>;
-
-// If we're shifting a 32-bit zero extended value left by 0-31 bits, use 2
-// shifts instead of 3. This can occur when unsigned is used to index an array.
-def : Pat<(shl (zext GPR:$rs), uimm5:$shamt),
-          (SRLI (i64 (SLLI GPR:$rs, 32)), (ImmSubFrom32 uimm5:$shamt))>;
 }
 
 //===----------------------------------------------------------------------===//
@@ -209,10 +204,5 @@ def : Pat<(shl (zext GPR:$rs), uimm5:$shamt),
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtZba, IsRV64] in {
-def : Pat<(shl (i64 (zext GPR:$rs1)), uimm5:$shamt),
-          (SLLI_UW GPR:$rs1, uimm5:$shamt)>;
-
-def : Pat<(i64 (add_like_non_imm12 (zext GPR:$rs1), GPR:$rs2)),
-          (ADD_UW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(zext GPR:$src), (ADD_UW GPR:$src, (XLenVT X0))>;
 }

diff  --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir
index c4d9e84b279ca7..345dc48d42a3b0 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/zba-rv64.mir
@@ -203,30 +203,6 @@ body:             |
     $x10 = COPY %4(s64)
 ...
 ---
-name:            slli_uw_s32
-legalized:       true
-regBankSelected: true
-tracksRegLiveness: true
-body:             |
-  bb.0.entry:
-    liveins: $x10
-
-    ; CHECK-LABEL: name: slli_uw_s32
-    ; CHECK: liveins: $x10
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
-    ; CHECK-NEXT: [[SLLI_UW:%[0-9]+]]:gpr = SLLI_UW [[COPY]], 7
-    ; CHECK-NEXT: $x10 = COPY [[SLLI_UW]]
-    %0:gprb(s64) = COPY $x10
-    %1:gprb(s32) = G_TRUNC %0(s64)
-
-    %2:gprb(s64) = G_ZEXT %1(s32)
-    %3:gprb(s64) = G_CONSTANT i64 7
-    %4:gprb(s64) = G_SHL %2, %3
-
-    $x10 = COPY %4(s64)
-...
----
 name:            slli_uw_complex
 legalized:       true
 regBankSelected: true
@@ -267,8 +243,8 @@ body:             |
     ; CHECK-NEXT: $x10 = COPY [[ADD_UW]]
     %0:gprb(s64) = COPY $x10
     %1:gprb(s64) = COPY $x11
-    %2:gprb(s32) = G_TRUNC %0
-    %3:gprb(s64) = G_ZEXT %2
+    %2:gprb(s64) = G_CONSTANT i64 4294967295
+    %3:gprb(s64) = G_AND %0, %2
     %4:gprb(s64) = G_ADD %3, %1
     $x10 = COPY %4(s64)
 ...