[llvm] [RISCV][MRI] Account for fixed registers when determining callee saved regs (PR #115756)

[Craig Topper via llvm-commits]

topperc wrote:

> > > The behavior differs from GCC for AArch64, ARM, Hexagon, SPARC, M68k and RISC-V.
> > > In LLVM, different targets have different interfaces to check whether the register was `-ffixed-XXX`. I am proposing that each target migrate to this common interface in follow up patches.
> > > This patch adds the interface, and migrates RISC-V and M68k to that interface, since they are already using the interface.
> > 
> > 
> > How will this interact with AArch64 or other targets calling setCalleeSavedRegisters which will cause `IsUpdatedCSRsInitialized` to get set preventing reaching the new code you added in `getCalleeSavedRegs`
> 
> If a target calls `setCalleeSavedRegs`, then its saying "give me full control of what registers are callee saved regs". If a target calls `setCalleeSavedRegs`, then it is on the target to determine which registers are fixed, in the same way its the target to figure out what registers are callee saved regs.
> 
> If a target calls `getCalleeSavedRegs` and IsUpdatedCSRsInitialized is true, it is prevented from reaching the existing `getTargetRegisterInfo()->getCalleeSavedRegs()` code. How is this any different?

The existing AArch64 code that uses `setCalleeSavedRegs` calls `AArch64RegisterInfo::getCalleeSavedRegs` and then adds some stuff to it. I guess the code you added to getCalleeSavedRegs will need to be copied into `AArch64RegisterInfo::UpdateCustomCalleeSavedRegs` to remove the fixed registers?

I'm just asking questions to make sure you've designed something that covers the use cases of other targets. If you think having AArch64 fix implement their fixed register support in `AArch64RegisterInfo::UpdateCustomCalleeSavedRegs` is the best solution, I'm ok with that.

https://github.com/llvm/llvm-project/pull/115756