[llvm] [AArch64][NFC] Fixup assembler directive tests for SVE/SME (PR #116253)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 14 08:22:53 PST 2024
https://github.com/SpencerAbson created https://github.com/llvm/llvm-project/pull/116253
The assembler directives `.arch` and `.cpu` have been miss-used in tests since [this bug ](https://bugs.llvm.org/show_bug.cgi?id=32873) was fixed ([relevant patch for `.arch`](https://github.com/llvm/llvm-project/commit/a499d675ae163429adff0bc3dc4f8215c12441c7#diff-978708f6b40d44a13bced2d3050ddcd01f4a2423ca34ac0e26fb2ff2a83cc885R6943)).
This patch fixes the existing tests, unifies the file structure for these tests, and adds coverage for `sme-f16f16`, `sme-f8f16`, and `sme-f8f32`.
Tests using `sve-b16b16`/`sme-b16b16` have been moved to the MC/AArch64/SME2 folder, as this is where the relevant instructions are tested.
>From e1f7da048f925bc9cfc8be5d016cac1c76a87f3f Mon Sep 17 00:00:00 2001
From: Spencer Abson <Spencer.Abson at arm.com>
Date: Thu, 14 Nov 2024 15:41:39 +0000
Subject: [PATCH 1/2] [NFC] Fixup assembler directive tests for SVE/SME
---
.../MC/AArch64/FP8/directive-arch-negative.s | 66 ++++++++++--------
llvm/test/MC/AArch64/FP8/directive-arch.s | 21 +++---
.../FP8/directive-arch_extension-negative.s | 68 +++++++++++++++++++
.../MC/AArch64/FP8/directive-arch_extension.s | 50 ++++++++++++++
.../MC/AArch64/FP8/directive-cpu-neagtive.s | 61 +++++++++++++++++
llvm/test/MC/AArch64/FP8/directive-cpu.s | 49 +++++++++++++
.../MC/AArch64/SME/directive-arch-negative.s | 16 +++++
llvm/test/MC/AArch64/SME/directive-arch.s | 15 ++++
.../SME/directive-arch_extension-negative.s | 19 ++++++
.../MC/AArch64/SME/directive-arch_extension.s | 16 +++++
.../MC/AArch64/SME/directive-cpu-negative.s | 16 +++++
llvm/test/MC/AArch64/SME/directive-cpu.s | 15 ++++
.../test/MC/AArch64/SME/directives-negative.s | 37 ----------
llvm/test/MC/AArch64/SME/directives.s | 35 ----------
.../MC/AArch64/SME2/directive-arch-negative.s | 22 ++++++
llvm/test/MC/AArch64/SME2/directive-arch.s | 15 +++-
.../SME2/directive-arch_extension-negative.s | 27 ++++++++
.../AArch64/SME2/directive-arch_extension.s | 18 +++++
.../MC/AArch64/SME2/directive-cpu-negative.s | 22 ++++++
llvm/test/MC/AArch64/SME2/directive-cpu.s | 18 +++++
.../AArch64/SME2p1/directive-arch-negative.s | 32 ++++-----
llvm/test/MC/AArch64/SME2p1/directive-arch.s | 6 +-
.../directive-arch_extension-negative.s | 22 ++----
.../AArch64/SME2p1/directive-arch_extension.s | 13 ++--
.../AArch64/SME2p1/directive-cpu-negative.s | 17 +++++
llvm/test/MC/AArch64/SME2p1/directive-cpu.s | 14 ++++
.../AArch64/SME2p2/directive-arch-negative.s | 9 ++-
llvm/test/MC/AArch64/SME2p2/directive-arch.s | 5 ++
.../directive-arch_extension-negative.s | 7 ++
.../AArch64/SME2p2/directive-arch_extension.s | 5 ++
.../AArch64/SME2p2/directive-cpu-negative.s | 9 ++-
llvm/test/MC/AArch64/SME2p2/directive-cpu.s | 5 ++
.../MC/AArch64/SVE2/directive-arch-negative.s | 33 ++++-----
llvm/test/MC/AArch64/SVE2/directive-arch.s | 5 ++
.../SVE2/directive-arch_extension-negative.s | 6 ++
.../AArch64/SVE2/directive-arch_extension.s | 9 +--
.../MC/AArch64/SVE2/directive-cpu-negative.s | 30 ++++----
llvm/test/MC/AArch64/SVE2/directive-cpu.s | 5 ++
.../AArch64/SVE2p1/directive-arch-negative.s | 23 ++++---
llvm/test/MC/AArch64/SVE2p1/directive-arch.s | 5 ++
.../directive-arch_extension-negative.s | 13 +++-
.../AArch64/SVE2p1/directive-arch_extension.s | 5 ++
.../AArch64/SVE2p1/directive-cpu-negative.s | 22 ++++++
llvm/test/MC/AArch64/SVE2p1/directive-cpu.s | 18 +++++
.../AArch64/SVE2p2/directive-arch-negative.s | 9 ++-
llvm/test/MC/AArch64/SVE2p2/directive-arch.s | 5 ++
.../directive-arch_extension-negative.s | 7 ++
.../AArch64/SVE2p2/directive-arch_extension.s | 5 ++
.../AArch64/SVE2p2/directive-cpu-negative.s | 9 ++-
llvm/test/MC/AArch64/SVE2p2/directive-cpu.s | 5 ++
50 files changed, 740 insertions(+), 224 deletions(-)
create mode 100644 llvm/test/MC/AArch64/FP8/directive-arch_extension-negative.s
create mode 100644 llvm/test/MC/AArch64/FP8/directive-arch_extension.s
create mode 100644 llvm/test/MC/AArch64/FP8/directive-cpu-neagtive.s
create mode 100644 llvm/test/MC/AArch64/FP8/directive-cpu.s
create mode 100644 llvm/test/MC/AArch64/SME/directive-arch-negative.s
create mode 100644 llvm/test/MC/AArch64/SME/directive-arch.s
create mode 100644 llvm/test/MC/AArch64/SME/directive-arch_extension-negative.s
create mode 100644 llvm/test/MC/AArch64/SME/directive-arch_extension.s
create mode 100644 llvm/test/MC/AArch64/SME/directive-cpu-negative.s
create mode 100644 llvm/test/MC/AArch64/SME/directive-cpu.s
delete mode 100644 llvm/test/MC/AArch64/SME/directives-negative.s
delete mode 100644 llvm/test/MC/AArch64/SME/directives.s
create mode 100644 llvm/test/MC/AArch64/SME2/directive-arch-negative.s
create mode 100644 llvm/test/MC/AArch64/SME2/directive-arch_extension-negative.s
create mode 100644 llvm/test/MC/AArch64/SME2/directive-arch_extension.s
create mode 100644 llvm/test/MC/AArch64/SME2/directive-cpu-negative.s
create mode 100644 llvm/test/MC/AArch64/SME2/directive-cpu.s
create mode 100644 llvm/test/MC/AArch64/SME2p1/directive-cpu-negative.s
create mode 100644 llvm/test/MC/AArch64/SME2p1/directive-cpu.s
create mode 100644 llvm/test/MC/AArch64/SVE2p1/directive-cpu-negative.s
create mode 100644 llvm/test/MC/AArch64/SVE2p1/directive-cpu.s
diff --git a/llvm/test/MC/AArch64/FP8/directive-arch-negative.s b/llvm/test/MC/AArch64/FP8/directive-arch-negative.s
index 34fdb74fe1f370..6fd9b3a5c20f0d 100644
--- a/llvm/test/MC/AArch64/FP8/directive-arch-negative.s
+++ b/llvm/test/MC/AArch64/FP8/directive-arch-negative.s
@@ -1,55 +1,61 @@
// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
-.arch armv9-a+fp8
-.arch armv9-a+nofp8
+.arch armv9-a+fp8+nofp8
bf1cvtl v0.8h, v0.8b
// CHECK: error: instruction requires: fp8
-// CHECK: bf1cvtl v0.8h, v0.8b
+// CHECK-NEXT: bf1cvtl v0.8h, v0.8b
-.arch armv9-a+faminmax
-.arch armv9-a+nofaminmax
+.arch armv9-a+faminmax+nofaminmax
famax v31.4h, v31.4h, v31.4h
// CHECK: error: instruction requires: faminmax
-// CHECK: famax v31.4h, v31.4h, v31.4h
+// CHECK-NEXT: famax v31.4h, v31.4h, v31.4h
-.arch armv9-a+fp8fma
-.arch armv9-a+nofp8fma
+.arch armv9-a+fp8fma+nofp8fma
fmlalb v0.8h, v0.16b, v0.16b
// CHECK: error: instruction requires: fp8fma
-// CHECK: fmlalb v0.8h, v0.16b, v0.16b
+// CHECK-NEXT: fmlalb v0.8h, v0.16b, v0.16b
-.arch armv9-a+ssve-fp8fma
-.arch armv9-a+nossve-fp8fma
+.arch armv9-a+ssve-fp8fma+nossve-fp8fma
fmlalb z23.h, z13.b, z0.b[7]
// CHECK: error: instruction requires: ssve-fp8fma or (sve2 and fp8fma)
-// CHECK: fmlalb z23.h, z13.b, z0.b[7]
+// CHECK-NEXT: fmlalb z23.h, z13.b, z0.b[7]
-.arch armv9-a+fp8dot2
-.arch armv9-a+nofp8dot2
+.arch armv9-a+fp8dot2+nofp8dot2
fdot v31.4h, v0.8b, v0.8b
// CHECK: error: instruction requires: fp8dot2
-// CHECK: fdot v31.4h, v0.8b, v0.8b
+// CHECK-NEXT: fdot v31.4h, v0.8b, v0.8b
-.arch armv9-a+fp8dot4
-.arch armv9-a+nofp8dot4
+.arch armv9-a+fp8dot4+nofp8dot4
fdot v0.2s, v0.8b, v31.8b
// CHECK: error: instruction requires: fp8dot4
-// CHECK: fdot v0.2s, v0.8b, v31.8b
+// CHECK-NEXT: fdot v0.2s, v0.8b, v31.8b
-.arch armv9-a+lut
-.arch armv9-a+nolut
-luti2 v30.8h, { v20.8h }, v31[7]
+.arch armv9-a+sme-f16f16+nosme-f16f16
+fsub za.h[w10, 5, vgx2], {z10.h, z11.h}
+// CHECK: error: instruction requires: sme-f16f16 or sme-f8f16
+// CHECK-NEXT: fsub za.h[w10, 5, vgx2], {z10.h, z11.h}
+
+.arch armv9-a+sme-f8f32+nosme-f8f32
+fdot za.s[w8, 0, vgx2], {z0.b-z1.b}, z0.b
+// CHECK: error: instruction requires: sme-f8f32
+// CHECK-NEXT: fdot za.s[w8, 0, vgx2], {z0.b-z1.b}, z0.b
+
+.arch armv9-a+sme-f8f16+nosme-f8f16
+fdot za.h[w8, 0, vgx2], {z0.b, z1.b}, z0.b
+// CHECK: error: instruction requires: sme-f8f16
+// CHECK-NEXT: fdot za.h[w8, 0, vgx2], {z0.b, z1.b}, z0.b
+
+.arch armv9-a+lut+nolut
+luti2 v30.8h, {v20.8h}, v31[7]
// CHECK: error: instruction requires: lut
-// CHECK: luti2 v30.8h, { v20.8h }, v31[7]
+// CHECK-NEXT: luti2 v30.8h, {v20.8h}, v31[7]
-.arch armv9-a+sve2+lut
-.arch armv9-a+nosve2+nolut
-luti2 z0.h, { z0.h }, z0[0]
+.arch armv9-a+sve2+lut+nosve2+nolut
+luti2 z0.h, {z0.h}, z0[0]
// CHECK: error: instruction requires: lut sve2 or sme2
-// CHECK: luti2 z0.h, { z0.h }, z0[0]
+// CHECK-NEXT: luti2 z0.h, {z0.h}, z0[0]
-.arch armv9-a+sme-lutv2
-.arch armv9-a+nosme-lutv2
-luti4 { z0.b - z3.b }, zt0, { z0, z1 }
+.arch armv9-a+sme-lutv2+nosme-lutv2
+luti4 {z0.b - z3.b}, zt0, {z0, z1}
// CHECK: error: instruction requires: sme-lutv2
-// CHECK: luti4 { z0.b - z3.b }, zt0, { z0, z1 }
+// CHECK-NEXT: luti4 {z0.b - z3.b}, zt0, {z0, z1}
diff --git a/llvm/test/MC/AArch64/FP8/directive-arch.s b/llvm/test/MC/AArch64/FP8/directive-arch.s
index b9803b79b58ef9..1b986b095bf072 100644
--- a/llvm/test/MC/AArch64/FP8/directive-arch.s
+++ b/llvm/test/MC/AArch64/FP8/directive-arch.s
@@ -3,44 +3,47 @@
.arch armv9-a+fp8
bf1cvtl v0.8h, v0.8b
// CHECK: bf1cvtl v0.8h, v0.8b
-.arch armv9-a+nofp8
.arch armv9-a+faminmax
famax v31.4h, v31.4h, v31.4h
// CHECK: famax v31.4h, v31.4h, v31.4h
-.arch armv9-a+nofaminmax
.arch armv9-a+fp8fma
fmlalb v0.8h, v0.16b, v0.16b
// CHECK: fmlalb v0.8h, v0.16b, v0.16b
-.arch armv9-a+nofp8fma
.arch armv9-a+ssve-fp8fma
fmlalb z23.h, z13.b, z0.b[7]
// CHECK: fmlalb z23.h, z13.b, z0.b[7]
-.arch armv9-a+nossve-fp8fma
.arch armv9-a+fp8dot2
fdot v31.4h, v0.8b, v0.8b
// CHECK: fdot v31.4h, v0.8b, v0.8b
-.arch armv9-a+nofp8dot2
.arch armv9-a+fp8dot4
fdot v0.2s, v0.8b, v31.8b
// CHECK: fdot v0.2s, v0.8b, v31.8b
-.arch armv9-a+nofp8dot4
+
+.arch armv9-a+sme-f16f16
+fsub za.h[w10, 5, vgx2], {z10.h, z11.h}
+// CHECK: fsub za.h[w10, 5, vgx2], { z10.h, z11.h }
+
+.arch armv9-a+sme-f8f32
+fdot za.s[w8, 0, vgx2], {z0.b-z1.b}, z0.b
+// CHECK: fdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b
+
+.arch armv9-a+sme-f8f16
+fdot za.h[w8, 0, vgx2], { z0.b, z1.b }, z0.b
+// CHECK: fdot za.h[w8, 0, vgx2], { z0.b, z1.b }, z0.b
.arch armv9-a+lut
luti2 v30.8h, {v20.8h}, v31[7]
// CHECK: luti2 v30.8h, { v20.8h }, v31[7]
-.arch armv9-a+nolut
.arch armv9-a+sve2+lut
luti2 z0.h, {z0.h}, z0[0]
// CHECK: luti2 z0.h, { z0.h }, z0[0]
-.arch armv9-a+nosve2+nolut
.arch armv9-a+sme2p1+sme-lutv2
luti4 {z0.b-z3.b}, zt0, {z0-z1}
// CHECK: luti4 { z0.b - z3.b }, zt0, { z0, z1 }
-.arch armv9-a+nosme2p1+nosme-lutv2
diff --git a/llvm/test/MC/AArch64/FP8/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/FP8/directive-arch_extension-negative.s
new file mode 100644
index 00000000000000..9b39f6f109e0ba
--- /dev/null
+++ b/llvm/test/MC/AArch64/FP8/directive-arch_extension-negative.s
@@ -0,0 +1,68 @@
+// RUN: not llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s
+
+.arch_extension fp8
+.arch_extension nofp8
+bf1cvtl v0.8h, v0.8b
+// CHECK: error: instruction requires: fp8
+// CHECK-NEXT: bf1cvtl v0.8h, v0.8b
+
+.arch_extension faminmax
+.arch_extension nofaminmax
+famax v31.4h, v31.4h, v31.4h
+// CHECK: error: instruction requires: faminmax
+// CHECK-NEXT: famax v31.4h, v31.4h, v31.4h
+
+.arch_extension fp8fma
+.arch_extension nofp8fma
+fmlalb v0.8h, v0.16b, v0.16b
+// CHECK: error: instruction requires: fp8fma
+// CHECK-NEXT: fmlalb v0.8h, v0.16b, v0.16b
+
+.arch_extension ssve-fp8fma
+.arch_extension nossve-fp8fma
+fmlalb z23.h, z13.b, z0.b[7]
+// CHECK: error: instruction requires: ssve-fp8fma
+// CHECK-NEXT: fmlalb z23.h, z13.b, z0.b[7]
+
+.arch_extension fp8dot2
+.arch_extension nofp8dot2
+fdot v31.4h, v0.8b, v0.8b
+// CHECK: error: instruction requires: fp8dot2
+// CHECK-NEXT: fdot v31.4h, v0.8b, v0.8b
+
+.arch_extension fp8dot4
+.arch_extension nofp8dot4
+fdot v0.2s, v0.8b, v31.8b
+// CHECK: error: instruction requires: fp8dot4
+// CHECK-NEXT: fdot v0.2s, v0.8b, v31.8b
+
+.arch_extension sme-f16f16
+.arch_extension nosme-f16f16
+fsub za.h[w10, 5, vgx2], {z10.h, z11.h}
+// CHECK: error: instruction requires: sme-f16f16 or sme-f8f16
+// CHECK-NEXT: fsub za.h[w10, 5, vgx2], {z10.h, z11.h}
+
+.arch_extension sme-f8f32
+.arch_extension nosme-f8f32
+fdot za.s[w8, 0, vgx2], {z0.b-z1.b}, z0.b
+// CHECK: error: instruction requires: sme-f8f32
+// CHECK-NEXT: fdot za.s[w8, 0, vgx2], {z0.b-z1.b}, z0.b
+
+.arch_extension sme-f8f16
+.arch_extension nosme-f8f16
+fdot za.h[w8, 0, vgx2], { z0.b, z1.b }, z0.b
+// CHECK: error: instruction requires: sme-f8f16
+// CHECK-NEXT: fdot za.h[w8, 0, vgx2], { z0.b, z1.b }, z0.b
+
+.arch_extension lut
+.arch_extension nolut
+luti2 v30.8h, {v20.8h}, v31[7]
+// CHECK: error: instruction requires: lut
+// CHECK-NEXT: luti2 v30.8h, {v20.8h}, v31[7]
+
+.arch_extension sme2p1
+.arch_extension sme-lutv2
+.arch_extension nosme-lutv2
+luti4 {z0.b-z3.b}, zt0, {z0-z1}
+// CHECK: error: instruction requires: sme-lutv2
+// CHECK-NEXT: luti4 {z0.b-z3.b}, zt0, {z0-z1}
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/FP8/directive-arch_extension.s b/llvm/test/MC/AArch64/FP8/directive-arch_extension.s
new file mode 100644
index 00000000000000..cc56e84fcb868c
--- /dev/null
+++ b/llvm/test/MC/AArch64/FP8/directive-arch_extension.s
@@ -0,0 +1,50 @@
+// RUN: llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s
+
+.arch_extension fp8
+bf1cvtl v0.8h, v0.8b
+// CHECK: bf1cvtl v0.8h, v0.8b
+
+.arch_extension faminmax
+famax v31.4h, v31.4h, v31.4h
+// CHECK: famax v31.4h, v31.4h, v31.4h
+
+.arch_extension fp8fma
+fmlalb v0.8h, v0.16b, v0.16b
+// CHECK: fmlalb v0.8h, v0.16b, v0.16b
+
+.arch_extension ssve-fp8fma
+fmlalb z23.h, z13.b, z0.b[7]
+// CHECK: fmlalb z23.h, z13.b, z0.b[7]
+
+.arch_extension fp8dot2
+fdot v31.4h, v0.8b, v0.8b
+// CHECK: fdot v31.4h, v0.8b, v0.8b
+
+.arch_extension fp8dot4
+fdot v0.2s, v0.8b, v31.8b
+// CHECK: fdot v0.2s, v0.8b, v31.8b
+
+.arch_extension lut
+luti2 v30.8h, {v20.8h}, v31[7]
+// CHECK: luti2 v30.8h, { v20.8h }, v31[7]
+
+.arch_extension sve
+luti2 z0.h, {z0.h}, z0[0]
+// CHECK: luti2 z0.h, { z0.h }, z0[0]
+
+.arch_extension sme-f16f16
+fsub za.h[w10, 5, vgx2], {z10.h, z11.h}
+// CHECK: fsub za.h[w10, 5, vgx2], { z10.h, z11.h }
+
+.arch_extension sme-f8f32
+fdot za.s[w8, 0, vgx2], {z0.b-z1.b}, z0.b
+// CHECK: fdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b
+
+.arch_extension sme-f8f16
+fdot za.h[w8, 0, vgx2], { z0.b, z1.b }, z0.b
+// CHECK: fdot za.h[w8, 0, vgx2], { z0.b, z1.b }, z0.b
+
+.arch_extension sme2p1
+.arch_extension sme-lutv2
+luti4 {z0.b-z3.b}, zt0, {z0-z1}
+// CHECK: luti4 { z0.b - z3.b }, zt0, { z0, z1 }
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/FP8/directive-cpu-neagtive.s b/llvm/test/MC/AArch64/FP8/directive-cpu-neagtive.s
new file mode 100644
index 00000000000000..2cfe303d02bbd4
--- /dev/null
+++ b/llvm/test/MC/AArch64/FP8/directive-cpu-neagtive.s
@@ -0,0 +1,61 @@
+// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+
+.cpu generic+fp8+nofp8
+bf1cvtl v0.8h, v0.8b
+// CHECK: error: instruction requires: fp8
+// CHECK: bf1cvtl v0.8h, v0.8b
+
+.cpu generic+faminmax+nofaminmax
+famax v31.4h, v31.4h, v31.4h
+// CHECK: error: instruction requires: faminmax
+// CHECK: famax v31.4h, v31.4h, v31.4h
+
+.cpu generic+fp8fma+nofp8fma
+fmlalb v0.8h, v0.16b, v0.16b
+// CHECK: error: instruction requires: fp8fma
+// CHECK: fmlalb v0.8h, v0.16b, v0.16b
+
+.cpu generic+ssve-fp8fma+nossve-fp8fma
+fmlalb z23.h, z13.b, z0.b[7]
+// CHECK: error: instruction requires: ssve-fp8fma or (sve2 and fp8fma)
+// CHECK: fmlalb z23.h, z13.b, z0.b[7]
+
+.cpu generic+fp8dot2+nofp8dot2
+fdot v31.4h, v0.8b, v0.8b
+// CHECK: error: instruction requires: fp8dot2
+// CHECK: fdot v31.4h, v0.8b, v0.8b
+
+.cpu generic+fp8dot4+nofp8dot4
+fdot v0.2s, v0.8b, v31.8b
+// CHECK: error: instruction requires: fp8dot4
+// CHECK: fdot v0.2s, v0.8b, v31.8b
+
+.cpu generic+sme-f16f16+nosme-f16f16
+fsub za.h[w10, 5, vgx2], {z10.h, z11.h}
+// CHECK: error: instruction requires: sme-f16f16 or sme-f8f16
+// CHECK-NEXT: fsub za.h[w10, 5, vgx2], {z10.h, z11.h}
+
+.cpu generic+sme-f8f32+nosme-f8f32
+fdot za.s[w8, 0, vgx2], {z0.b-z1.b}, z0.b
+// CHECK: error: instruction requires: sme-f8f32
+// CHECK-NEXT: fdot za.s[w8, 0, vgx2], {z0.b-z1.b}, z0.b
+
+.cpu generic+sme-f8f16+nosme-f8f16
+fdot za.h[w8, 0, vgx2], {z0.b, z1.b}, z0.b
+// CHECK: error: instruction requires: sme-f8f16
+// CHECK-NEXT: fdot za.h[w8, 0, vgx2], {z0.b, z1.b}, z0.b
+
+.cpu generic+lut+nolut
+luti2 v30.8h, { v20.8h }, v31[7]
+// CHECK: error: instruction requires: lut
+// CHECK: luti2 v30.8h, { v20.8h }, v31[7]
+
+.cpu generic+sve2+lut+nosve2+nolut
+luti2 z0.h, { z0.h }, z0[0]
+// CHECK: error: instruction requires: lut sve2 or sme2
+// CHECK: luti2 z0.h, { z0.h }, z0[0]
+
+.cpu generic+sme-lutv2+nosme-lutv2
+luti4 { z0.b - z3.b }, zt0, { z0, z1 }
+// CHECK: error: instruction requires: sme-lutv2
+// CHECK: luti4 { z0.b - z3.b }, zt0, { z0, z1 }
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/FP8/directive-cpu.s b/llvm/test/MC/AArch64/FP8/directive-cpu.s
new file mode 100644
index 00000000000000..457cde2bc7ae3c
--- /dev/null
+++ b/llvm/test/MC/AArch64/FP8/directive-cpu.s
@@ -0,0 +1,49 @@
+// RUN: llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s
+
+.cpu generic+fp8
+bf1cvtl v0.8h, v0.8b
+// CHECK: bf1cvtl v0.8h, v0.8b
+
+.cpu generic+faminmax
+famax v31.4h, v31.4h, v31.4h
+// CHECK: famax v31.4h, v31.4h, v31.4h
+
+.cpu generic+fp8fma
+fmlalb v0.8h, v0.16b, v0.16b
+// CHECK: fmlalb v0.8h, v0.16b, v0.16b
+
+.cpu generic+ssve-fp8fma
+fmlalb z23.h, z13.b, z0.b[7]
+// CHECK: fmlalb z23.h, z13.b, z0.b[7]
+
+.cpu generic+fp8dot2
+fdot v31.4h, v0.8b, v0.8b
+// CHECK: fdot v31.4h, v0.8b, v0.8b
+
+.cpu generic+fp8dot4
+fdot v0.2s, v0.8b, v31.8b
+// CHECK: fdot v0.2s, v0.8b, v31.8b
+
+.cpu generic+sme-f16f16
+fsub za.h[w10, 5, vgx2], {z10.h, z11.h}
+// CHECK: fsub za.h[w10, 5, vgx2], { z10.h, z11.h }
+
+.cpu generic+sme-f8f32
+fdot za.s[w8, 0, vgx2], {z0.b-z1.b}, z0.b
+// CHECK: fdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b
+
+.cpu generic+sme-f8f16
+fdot za.h[w8, 0, vgx2], { z0.b, z1.b }, z0.b
+// CHECK: fdot za.h[w8, 0, vgx2], { z0.b, z1.b }, z0.b
+
+.cpu generic+lut
+luti2 v30.8h, {v20.8h}, v31[7]
+// CHECK: luti2 v30.8h, { v20.8h }, v31[7]
+
+.cpu generic+sve2+lut
+luti2 z0.h, {z0.h}, z0[0]
+// CHECK: luti2 z0.h, { z0.h }, z0[0]
+
+.cpu generic+sme2p1+sme-lutv2
+luti4 {z0.b-z3.b}, zt0, {z0-z1}
+// CHECK: luti4 { z0.b - z3.b }, zt0, { z0, z1 }
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SME/directive-arch-negative.s b/llvm/test/MC/AArch64/SME/directive-arch-negative.s
new file mode 100644
index 00000000000000..2edc2f0559b953
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME/directive-arch-negative.s
@@ -0,0 +1,16 @@
+// RUN: not llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s
+
+.arch armv9-a+sme+nosme
+zero {za}
+// CHECK: error: instruction requires: sme
+// CHECK-NEXT: zero {za}
+
+.arch armv9-a+sme-f64f64+nosme-f64f64
+fmopa za0.d, p0/m, p0/m, z0.d, z0.d
+// CHECK: error: instruction requires: sme-f64f64
+// CHECK-NEXT: fmopa za0.d, p0/m, p0/m, z0.d, z0.d
+
+.arch armv9-a+sme-i16i64+nosme-i16i64
+addha za0.d, p0/m, p0/m, z0.d
+// CHECK: error: instruction requires: sme-i16i64
+// CHECK-NEXT: addha za0.d, p0/m, p0/m, z0.d
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SME/directive-arch.s b/llvm/test/MC/AArch64/SME/directive-arch.s
new file mode 100644
index 00000000000000..202e71469f2953
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME/directive-arch.s
@@ -0,0 +1,15 @@
+// RUN: llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s
+
+.arch armv9-a+sme
+smstart
+// CHECK: smstart
+zero {za}
+// CHECK-NEXT: zero {za}
+
+.arch armv9-a+sme-f64f64
+fmopa za0.d, p0/m, p0/m, z0.d, z0.d
+// CHECK: fmopa za0.d, p0/m, p0/m, z0.d, z0.d
+
+.arch armv9-a+sme-i16i64
+addha za0.d, p0/m, p0/m, z0.d
+// CHECK: addha za0.d, p0/m, p0/m, z0.d
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SME/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/SME/directive-arch_extension-negative.s
new file mode 100644
index 00000000000000..feb8090ffd2854
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME/directive-arch_extension-negative.s
@@ -0,0 +1,19 @@
+// RUN: not llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s
+
+.arch_extension sme
+.arch_extension nosme
+zero {za}
+// CHECK: error: instruction requires: sme
+// CHECK-NEXT: zero {za}
+
+.arch_extension sme-f64f64
+.arch_extension nosme-f64f64
+fmopa za0.d, p0/m, p0/m, z0.d, z0.d
+// CHECK: error: instruction requires: sme-f64f64
+// CHECK-NEXT: fmopa za0.d, p0/m, p0/m, z0.d, z0.d
+
+.arch_extension sme-i16i64
+.arch_extension nosme-i16i64
+addha za0.d, p0/m, p0/m, z0.d
+// CHECK: error: instruction requires: sme-i16i64
+// CHECK-NEXT: addha za0.d, p0/m, p0/m, z0.d
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SME/directive-arch_extension.s b/llvm/test/MC/AArch64/SME/directive-arch_extension.s
new file mode 100644
index 00000000000000..aa5962b40b2b3e
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME/directive-arch_extension.s
@@ -0,0 +1,16 @@
+// RUN: llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s
+
+.arch_extension sme
+smstart
+// CHECK: smstart
+zero {za}
+// CHECK-NEXT: zero {za}
+
+.arch_extension sme-f64f64
+fmopa za0.d, p0/m, p0/m, z0.d, z0.d
+// CHECK: fmopa za0.d, p0/m, p0/m, z0.d, z0.d
+
+.arch_extension sme-i16i64
+addha za0.d, p0/m, p0/m, z0.d
+// CHECK: addha za0.d, p0/m, p0/m, z0.d
+
diff --git a/llvm/test/MC/AArch64/SME/directive-cpu-negative.s b/llvm/test/MC/AArch64/SME/directive-cpu-negative.s
new file mode 100644
index 00000000000000..ed26d1df8fbd41
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME/directive-cpu-negative.s
@@ -0,0 +1,16 @@
+// RUN: not llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s
+
+.cpu generic+sme+nosme
+zero {za}
+// CHECK: error: instruction requires: sme
+// CHECK-NEXT: zero {za}
+
+.cpu generic+sme-f64f64+nosme-f64f64
+fmopa za0.d, p0/m, p0/m, z0.d, z0.d
+// CHECK: error: instruction requires: sme-f64f64
+// CHECK-NEXT: fmopa za0.d, p0/m, p0/m, z0.d, z0.d
+
+.cpu generic+sme-i16i64+nosme-i16i64
+addha za0.d, p0/m, p0/m, z0.d
+// CHECK: error: instruction requires: sme-i16i64
+// CHECK-NEXT: addha za0.d, p0/m, p0/m, z0.d
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SME/directive-cpu.s b/llvm/test/MC/AArch64/SME/directive-cpu.s
new file mode 100644
index 00000000000000..5a71e0ff98a2cd
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME/directive-cpu.s
@@ -0,0 +1,15 @@
+// RUN: llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s
+
+.cpu generic+sme
+smstart
+// CHECK: smstart
+zero {za}
+// CHECK-NEXT: zero {za}
+
+.cpu generic+sme-f64f64
+fmopa za0.d, p0/m, p0/m, z0.d, z0.d
+// CHECK: fmopa za0.d, p0/m, p0/m, z0.d, z0.d
+
+.cpu generic+sme-i16i64
+addha za0.d, p0/m, p0/m, z0.d
+// CHECK: addha za0.d, p0/m, p0/m, z0.d
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SME/directives-negative.s b/llvm/test/MC/AArch64/SME/directives-negative.s
deleted file mode 100644
index 123c3a383d71ef..00000000000000
--- a/llvm/test/MC/AArch64/SME/directives-negative.s
+++ /dev/null
@@ -1,37 +0,0 @@
-// RUN: not llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s
-
-.arch_extension sme
-.arch_extension nosme
-zero {za}
-// CHECK: error: instruction requires: sme
-// CHECK-NEXT: zero {za}
-
-.arch_extension sme-f64f64
-.arch_extension nosme-f64f64
-fmopa za0.d, p0/m, p0/m, z0.d, z0.d
-// CHECK: error: instruction requires: sme-f64f64
-// CHECK-NEXT: fmopa za0.d, p0/m, p0/m, z0.d, z0.d
-
-.arch_extension sme-i16i64
-.arch_extension nosme-i16i64
-addha za0.d, p0/m, p0/m, z0.d
-// CHECK: error: instruction requires: sme-i16i64
-// CHECK-NEXT: addha za0.d, p0/m, p0/m, z0.d
-
-.arch armv9-a+sme
-.arch armv9-a+nosme
-zero {za}
-// CHECK: error: instruction requires: sme
-// CHECK-NEXT: zero {za}
-
-.arch armv9-a+sme-f64f64
-.arch armv9-a+nosme-f64f64
-fmopa za0.d, p0/m, p0/m, z0.d, z0.d
-// CHECK: error: instruction requires: sme-f64f64
-// CHECK-NEXT: fmopa za0.d, p0/m, p0/m, z0.d, z0.d
-
-.arch armv9-a+sme-i16i64
-.arch armv9-a+nosme-i16i64
-addha za0.d, p0/m, p0/m, z0.d
-// CHECK: error: instruction requires: sme-i16i64
-// CHECK-NEXT: addha za0.d, p0/m, p0/m, z0.d
diff --git a/llvm/test/MC/AArch64/SME/directives.s b/llvm/test/MC/AArch64/SME/directives.s
deleted file mode 100644
index ca3ba9c2f8e1ec..00000000000000
--- a/llvm/test/MC/AArch64/SME/directives.s
+++ /dev/null
@@ -1,35 +0,0 @@
-// RUN: llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s
-
-.arch_extension sme
-smstart
-// CHECK: smstart
-
-.arch_extension nosme
-
-.arch_extension sme-f64f64
-fmopa za0.d, p0/m, p0/m, z0.d, z0.d
-// CHECK: fmopa za0.d, p0/m, p0/m, z0.d, z0.d
-
-.arch_extension nosme-f64f64
-
-.arch_extension sme-i16i64
-addha za0.d, p0/m, p0/m, z0.d
-// CHECK: addha za0.d, p0/m, p0/m, z0.d
-
-.arch_extension nosme-i16i64
-
-.arch armv9-a+sme
-smstart
-// CHECK: smstart
-
-.arch armv9-a+nosme
-
-.arch armv9-a+sme-f64f64
-fmopa za0.d, p0/m, p0/m, z0.d, z0.d
-// CHECK: fmopa za0.d, p0/m, p0/m, z0.d, z0.d
-
-.arch armv9-a+nosme-f64f64
-
-.arch armv9-a+sme-i16i64
-addha za0.d, p0/m, p0/m, z0.d
-// CHECK: addha za0.d, p0/m, p0/m, z0.d
diff --git a/llvm/test/MC/AArch64/SME2/directive-arch-negative.s b/llvm/test/MC/AArch64/SME2/directive-arch-negative.s
new file mode 100644
index 00000000000000..b711aa593b3606
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/directive-arch-negative.s
@@ -0,0 +1,22 @@
+// RUN: not llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s
+
+// SME2 should require SME
+.arch armv9-a+sme2+nosme
+sqcvt z0.h, {z0.s, z1.s}
+// CHECK: error: instruction requires: sme2
+// CHECK-NEXT: sqcvt z0.h, {z0.s, z1.s}
+
+.arch armv9-a+sme2+nosme2
+sqcvt z0.h, {z0.s, z1.s}
+// CHECK: error: instruction requires: sme2
+// CHECK-NEXT: sqcvt z0.h, {z0.s, z1.s}
+
+.arch armv9-a+sme2+sve-b16b16+nosve-b16b16
+bfclamp {z0.h, z1.h}, z0.h, z0.h
+// CHECK: error: instruction requires: sve-b16b16
+// CHECK-NEXT: bfclamp {z0.h, z1.h}, z0.h, z0.h
+
+.arch armv9-a+sme-b16b16+nosme-b16b16
+bfadd za.h[w8, 3], {z20.h-z21.h}
+// CHECK: error: instruction requires: sme-b16b16
+// CHECK-NEXT: bfadd za.h[w8, 3], {z20.h-z21.h}
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SME2/directive-arch.s b/llvm/test/MC/AArch64/SME2/directive-arch.s
index cb787288000e8e..3df563fd811a15 100644
--- a/llvm/test/MC/AArch64/SME2/directive-arch.s
+++ b/llvm/test/MC/AArch64/SME2/directive-arch.s
@@ -1,9 +1,18 @@
// RUN: llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s
+// SME2 should imply SME
+.arch armv9-a+sme2
+zero {za}
+// CHECK: zero {za}
.arch armv9-a+sme2
-add za.s[w8, 7], {z20.s-z21.s}, z10.s
-// CHECK: add za.s[w8, 7, vgx2], { z20.s, z21.s }, z10.s
+sqcvt z0.h, {z0.s, z1.s}
+// CHECK: sqcvt z0.h, { z0.s, z1.s }
-.arch armv9-a+nosme2
+.arch armv9-a+sme2+sve-b16b16
+bfclamp {z0.h, z1.h}, z0.h, z0.h
+// CHECK: bfclamp { z0.h, z1.h }, z0.h, z0.h
+.arch armv9-a+sme-b16b16
+bfadd za.h[w8, 3], {z20.h-z21.h}
+// CHECK: bfadd za.h[w8, 3, vgx2], { z20.h, z21.h }
diff --git a/llvm/test/MC/AArch64/SME2/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/SME2/directive-arch_extension-negative.s
new file mode 100644
index 00000000000000..4c99a12d49d1c2
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/directive-arch_extension-negative.s
@@ -0,0 +1,27 @@
+// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+
+// SME2 should require SME
+.arch_extension sme2
+.arch_extension nosme
+sqcvt z0.h, {z0.s, z1.s}
+// CHECK: error: instruction requires: sme2
+// CHECK-NEXT: sqcvt z0.h, {z0.s, z1.s}
+
+.arch_extension sme2
+.arch_extension nosme2
+sqcvt z0.h, {z0.s, z1.s}
+// CHECK: error: instruction requires: sme2
+// CHECK-NEXT: sqcvt z0.h, {z0.s, z1.s}
+
+.arch_extension sme2
+.arch_extension sve-b16b16
+.arch_extension nosve-b16b16
+bfclamp { z0.h, z1.h }, z0.h, z0.h
+// CHECK: error: instruction requires: sve-b16b16
+// CHECK-NEXT: bfclamp { z0.h, z1.h }, z0.h, z0.h
+
+.arch_extension sme-b16b16
+.arch_extension nosme-b16b16
+bfadd za.h[w8, 3], {z20.h-z21.h}
+// CHECK: error: instruction requires: sme-b16b16
+// CHECK-NEXT: bfadd za.h[w8, 3], {z20.h-z21.h}
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SME2/directive-arch_extension.s b/llvm/test/MC/AArch64/SME2/directive-arch_extension.s
new file mode 100644
index 00000000000000..cfd0a0f3af7098
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/directive-arch_extension.s
@@ -0,0 +1,18 @@
+// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+
+// SME2 should imply SME
+.arch_extension sme2
+zero {za}
+// CHECK: zero {za}
+
+.arch_extension sme2
+sqcvt z0.h, {z0.s, z1.s}
+// CHECK: sqcvt z0.h, { z0.s, z1.s }
+
+.arch_extension sve-b16b16
+bfclamp { z0.h, z1.h }, z0.h, z0.h
+// CHECK: bfclamp { z0.h, z1.h }, z0.h, z0.h
+
+.arch_extension sme-b16b16
+bfadd za.h[w8, 3], {z20.h-z21.h}
+// CHECK: bfadd za.h[w8, 3, vgx2], { z20.h, z21.h }
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SME2/directive-cpu-negative.s b/llvm/test/MC/AArch64/SME2/directive-cpu-negative.s
new file mode 100644
index 00000000000000..b904461c50acb2
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/directive-cpu-negative.s
@@ -0,0 +1,22 @@
+// RUN: not llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s
+
+// SME2 should require SME
+.cpu generic+sme2+nosme
+sqcvt z0.h, { z0.s, z1.s }
+// CHECK: error: instruction requires: sme2
+// CHECK: sqcvt z0.h, { z0.s, z1.s }
+
+.cpu generic+sme2+nosme2
+sqcvt z0.h, { z0.s, z1.s }
+// CHECK: error: instruction requires: sme2
+// CHECK: sqcvt z0.h, { z0.s, z1.s }
+
+.cpu generic+sme2+sve-b16b16+nosve-b16b16
+bfclamp {z0.h, z1.h}, z0.h, z0.h
+// CHECK: error: instruction requires: sve-b16b16
+// CHECK: bfclamp {z0.h, z1.h}, z0.h, z0.h
+
+.cpu generic+sme-b16b16+nosme-b16b16
+bfadd za.h[w8, 0, vgx2], {z0.h, z1.h}
+// CHECK: error: instruction requires: sme-b16b16
+// CHECK: bfadd za.h[w8, 0, vgx2], {z0.h, z1.h}
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SME2/directive-cpu.s b/llvm/test/MC/AArch64/SME2/directive-cpu.s
new file mode 100644
index 00000000000000..0fd133b69722ed
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2/directive-cpu.s
@@ -0,0 +1,18 @@
+// RUN: llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s
+
+// SME2 should imply SME
+.cpu generic+sme2
+zero {za}
+// CHECK: zero {za}
+
+.cpu generic+sme2
+sqcvt z0.h, {z0.s, z1.s}
+// CHECK: sqcvt z0.h, { z0.s, z1.s }
+
+.cpu generic+sme2+sve-b16b16
+bfclamp {z0.h, z1.h}, z0.h, z0.h
+// CHECK: bfclamp { z0.h, z1.h }, z0.h, z0.h
+
+.cpu generic+sme-b16b16
+bfadd za.h[w8, 0, vgx2], {z0.h, z1.h}
+// CHECK: bfadd za.h[w8, 0, vgx2], { z0.h, z1.h }
diff --git a/llvm/test/MC/AArch64/SME2p1/directive-arch-negative.s b/llvm/test/MC/AArch64/SME2p1/directive-arch-negative.s
index 06bc5ec2339789..91f03e8aeb35cb 100644
--- a/llvm/test/MC/AArch64/SME2p1/directive-arch-negative.s
+++ b/llvm/test/MC/AArch64/SME2p1/directive-arch-negative.s
@@ -1,25 +1,17 @@
// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
-.arch armv9-a+sme2p1
-.arch armv9-a+nosme2p1
-sqcvt z0.h, {z0.s, z1.s}
-// CHECK: error: instruction requires: sme2
-// CHECK: sqcvt z0.h, {z0.s, z1.s}
+// SME2p1 should require SME2
+.arch armv9-a+sme2p1+nosme2
+movaz {z0.d, z1.d}, za.d[w8, 0]
+// CHECK: error: instruction requires: sme2p1
+// CHECK-NEXT: movaz {z0.d, z1.d}, za.d[w8, 0]
-.arch armv9-a+sme2+sve-b16b16
-.arch armv9-a+sme2+nosve-b16b16
-bfclamp { z0.h, z1.h }, z0.h, z0.h
-// CHECK: error: instruction requires: sve-b16b16
-// CHECK: bfclamp { z0.h, z1.h }, z0.h, z0.h
+.arch armv9-a+sme2p1+nosme2p1
+movaz {z0.d, z1.d}, za.d[w8, 0]
+// CHECK: error: instruction requires: sme2p1
+// CHECK-NEXT: movaz {z0.d, z1.d}, za.d[w8, 0]
-.arch armv9-a+sme-b16b16
-.arch armv9-a+nosme-b16b16
-bfadd za.h[w8, 3], {z20.h-z21.h}
-// CHECK: error: instruction requires: sme-b16b16
-// CHECK: bfadd za.h[w8, 3], {z20.h-z21.h}
-
-.arch armv9-a+sve-aes2+ssve-aes
-.arch armv9-a+nossve-aes
+.arch armv9-a+sve-aes2+ssve-aes+nossve-aes
aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
-// CHECK: error: instruction requires: sve2p1 or ssve-aes sve-aes2
-// CHECK: aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
\ No newline at end of file
+// CHECK: error: instruction requires: sve2p1 or ssve-aes
+// CHECK-NEXT: aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SME2p1/directive-arch.s b/llvm/test/MC/AArch64/SME2p1/directive-arch.s
index 51d259af30e813..86da646b75a24e 100644
--- a/llvm/test/MC/AArch64/SME2p1/directive-arch.s
+++ b/llvm/test/MC/AArch64/SME2p1/directive-arch.s
@@ -5,9 +5,9 @@
sqcvt z0.h, {z0.s, z1.s}
// CHECK: sqcvt z0.h, { z0.s, z1.s }
-.arch armv9-a+sme2+sve-b16b16
-bfclamp { z0.h, z1.h }, z0.h, z0.h
-// CHECK: bfclamp { z0.h, z1.h }, z0.h, z0.h
+.arch armv9-a+sme2p1
+movaz {z0.d, z1.d}, za.d[w8, 0, vgx2]
+// CHECK: movaz { z0.d, z1.d }, za.d[w8, 0, vgx2]
.arch armv9-a+sve-aes2+ssve-aes
aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
diff --git a/llvm/test/MC/AArch64/SME2p1/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/SME2p1/directive-arch_extension-negative.s
index 6e185a7ff8cc34..c61309b2cba055 100644
--- a/llvm/test/MC/AArch64/SME2p1/directive-arch_extension-negative.s
+++ b/llvm/test/MC/AArch64/SME2p1/directive-arch_extension-negative.s
@@ -1,27 +1,15 @@
// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+// SME2p1 should require SME2
.arch_extension sme2p1
.arch_extension nosme2
-sqcvt z0.h, { z0.s, z1.s }
-// CHECK: error: instruction requires: sme2
-// CHECK: sqcvt z0.h
-
-.arch_extension sme2
-.arch_extension sve-b16b16
-.arch_extension nosve-b16b16
-bfclamp { z0.h, z1.h }, z0.h, z0.h
-// CHECK: error: instruction requires: sve-b16b16
-// CHECK: bfclamp { z0.h, z1.h }, z0.h, z0.h
-
-.arch_extension sme-b16b16
-.arch_extension nosme-b16b16
-bfadd za.h[w8, 3], {z20.h-z21.h}
-// CHECK: error: instruction requires: sme-b16b16
-// CHECK: bfadd za.h[w8, 3], {z20.h-z21.h}
+movaz {z0.d, z1.d}, za.d[w8, 0]
+// CHECK: error: instruction requires: sme2p1
+// CHECK-NEXT: movaz {z0.d, z1.d}, za.d[w8, 0]
.arch_extension sve-aes2
.arch_extension ssve-aes
.arch_extension nossve-aes
aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
// CHECK: error: instruction requires: sve2p1 or ssve-aes
-// CHECK: aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
\ No newline at end of file
+// CHECK-NEXT: aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SME2p1/directive-arch_extension.s b/llvm/test/MC/AArch64/SME2p1/directive-arch_extension.s
index 3700325e6a5fe3..e8188f5881e76d 100644
--- a/llvm/test/MC/AArch64/SME2p1/directive-arch_extension.s
+++ b/llvm/test/MC/AArch64/SME2p1/directive-arch_extension.s
@@ -1,17 +1,12 @@
// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+// SME2p1 should imply SME2
.arch_extension sme2p1
-sqcvt z0.h, { z0.s, z1.s }
+sqcvt z0.h, {z0.s, z1.s}
// CHECK: sqcvt z0.h, { z0.s, z1.s }
-.arch_extension sme2
-.arch_extension sve-b16b16
-bfclamp { z0.h, z1.h }, z0.h, z0.h
-// CHECK: bfclamp { z0.h, z1.h }, z0.h, z0.h
-
-.arch_extension sme-b16b16
-bfadd za.h[w8, 3], {z20.h-z21.h}
-// CHECK: bfadd za.h[w8, 3, vgx2], { z20.h, z21.h }
+movaz {z0.d, z1.d}, za.d[w8, 0, vgx2]
+// CHECK: movaz { z0.d, z1.d }, za.d[w8, 0, vgx2]
.arch_extension sve-aes2
.arch_extension ssve-aes
diff --git a/llvm/test/MC/AArch64/SME2p1/directive-cpu-negative.s b/llvm/test/MC/AArch64/SME2p1/directive-cpu-negative.s
new file mode 100644
index 00000000000000..005752a4f3515b
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2p1/directive-cpu-negative.s
@@ -0,0 +1,17 @@
+// RUN: not llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s
+
+// SME2p1 should require SME2
+.cpu generic+sme2p1+nosme2
+movaz {z0.d, z1.d}, za.d[w8, 0]
+// CHECK: error: instruction requires: sme2p1
+// CHECK-NEXT: movaz {z0.d, z1.d}, za.d[w8, 0]
+
+.cpu generic+sme2p1+nosme2p1
+movaz {z0.d, z1.d}, za.d[w8, 0, vgx2]
+// CHECK: error: instruction requires: sme2p1
+// CHECK-NEXT: movaz {z0.d, z1.d}, za.d[w8, 0, vgx2]
+
+.cpu generic+sve-aes2+ssve-aes+nossve-aes
+aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
+// CHECK: error: instruction requires: sve2p1 or ssve-aes
+// CHECK-NEXT: aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SME2p1/directive-cpu.s b/llvm/test/MC/AArch64/SME2p1/directive-cpu.s
new file mode 100644
index 00000000000000..7aebbfe79f590c
--- /dev/null
+++ b/llvm/test/MC/AArch64/SME2p1/directive-cpu.s
@@ -0,0 +1,14 @@
+// RUN: llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s
+
+// SME2p1 should imply SME2
+.cpu generic+sme2p1
+sqcvt z0.h, {z0.s, z1.s}
+// CHECK: sqcvt z0.h, { z0.s, z1.s }
+
+.cpu generic+sme2p1
+movaz {z0.d, z1.d}, za.d[w8, 0, vgx2]
+// CHECK: movaz { z0.d, z1.d }, za.d[w8, 0, vgx2]
+
+.cpu generic+sve-aes2+ssve-aes
+aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
+// CHECK: aesdimc { z0.b - z3.b }, { z0.b - z3.b }, z0.q[0]
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SME2p2/directive-arch-negative.s b/llvm/test/MC/AArch64/SME2p2/directive-arch-negative.s
index 27169bac8133e7..eac05bba692fde 100644
--- a/llvm/test/MC/AArch64/SME2p2/directive-arch-negative.s
+++ b/llvm/test/MC/AArch64/SME2p2/directive-arch-negative.s
@@ -1,7 +1,12 @@
// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
-.arch armv9-a+sme2p2
-.arch armv9-a+nosme2p2
+// SME2p2 should require SME2p1
+.arch armv9-a+sme2p2+nosme2p1
+ftmopa za0.s, {z0.s-z1.s}, z0.s, z20[0]
+// CHECK: error: instruction requires: sme2p2
+// CHECK: ftmopa za0.s, {z0.s-z1.s}, z0.s, z20[0]
+
+.arch armv9-a+sme2p2+nosme2p2
ftmopa za0.s, {z0.s-z1.s}, z0.s, z20[0]
// CHECK: error: instruction requires: sme2p2
// CHECK: ftmopa za0.s, {z0.s-z1.s}, z0.s, z20[0]
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SME2p2/directive-arch.s b/llvm/test/MC/AArch64/SME2p2/directive-arch.s
index bb4e943a88478e..d0895cdd65c780 100644
--- a/llvm/test/MC/AArch64/SME2p2/directive-arch.s
+++ b/llvm/test/MC/AArch64/SME2p2/directive-arch.s
@@ -1,5 +1,10 @@
// RUN: llvm-mc -triple aarch64 -o - %s 2>&1 | FileCheck %s
+// SME2p2 should imply SME2p1
+.arch armv9-a+sme2p2
+movaz {z0.d, z1.d}, za.d[w8, 0, vgx2]
+// CHECK: movaz { z0.d, z1.d }, za.d[w8, 0, vgx2]
+
.arch armv9-a+sme2p2
ftmopa za0.s, {z0.s-z1.s}, z0.s, z20[0]
// CHECK: ftmopa za0.s, { z0.s, z1.s }, z0.s, z20[0]
diff --git a/llvm/test/MC/AArch64/SME2p2/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/SME2p2/directive-arch_extension-negative.s
index 68784db1c6272b..82657df0d31b60 100644
--- a/llvm/test/MC/AArch64/SME2p2/directive-arch_extension-negative.s
+++ b/llvm/test/MC/AArch64/SME2p2/directive-arch_extension-negative.s
@@ -1,5 +1,12 @@
// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+// SME2p2 should require SME2p1
+.arch_extension sme2p2
+.arch_extension nosme2p1
+ftmopa za0.s, {z0.s-z1.s}, z0.s, z20[0]
+// CHECK: error: instruction requires: sme2p2
+// CHECK: ftmopa za0.s, {z0.s-z1.s}, z0.s, z20[0]
+
.arch_extension sme2p2
.arch_extension nosme2p2
ftmopa za0.s, {z0.s-z1.s}, z0.s, z20[0]
diff --git a/llvm/test/MC/AArch64/SME2p2/directive-arch_extension.s b/llvm/test/MC/AArch64/SME2p2/directive-arch_extension.s
index 2e281e13f8ddb9..eaf84b18a020d0 100644
--- a/llvm/test/MC/AArch64/SME2p2/directive-arch_extension.s
+++ b/llvm/test/MC/AArch64/SME2p2/directive-arch_extension.s
@@ -1,5 +1,10 @@
// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+// SME2p2 should imply SME2p1
+.arch_extension sme2p2
+movaz {z0.d, z1.d}, za.d[w8, 0, vgx2]
+// CHECK: movaz { z0.d, z1.d }, za.d[w8, 0, vgx2]
+
.arch_extension sme2p2
ftmopa za0.s, {z0.s-z1.s}, z0.s, z20[0]
// CHECK: ftmopa za0.s, { z0.s, z1.s }, z0.s, z20[0]
diff --git a/llvm/test/MC/AArch64/SME2p2/directive-cpu-negative.s b/llvm/test/MC/AArch64/SME2p2/directive-cpu-negative.s
index 7cc829fbddd6ac..9d6a080fb8be09 100644
--- a/llvm/test/MC/AArch64/SME2p2/directive-cpu-negative.s
+++ b/llvm/test/MC/AArch64/SME2p2/directive-cpu-negative.s
@@ -1,7 +1,12 @@
// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
-.cpu generic+sme2p2
-.cpu generic+nosme2p2
+// SME2p2 should require SME2p1
+.cpu generic+sme2p2+nosme2p1
+ftmopa za0.s, {z0.s-z1.s}, z0.s, z20[0]
+// CHECK: error: instruction requires: sme2p2
+// CHECK: ftmopa za0.s, {z0.s-z1.s}, z0.s, z20[0]
+
+.cpu generic+sme2p2+nosme2p2
ftmopa za0.s, {z0.s-z1.s}, z0.s, z20[0]
// CHECK: error: instruction requires: sme2p2
// CHECK: ftmopa za0.s, {z0.s-z1.s}, z0.s, z20[0]
diff --git a/llvm/test/MC/AArch64/SME2p2/directive-cpu.s b/llvm/test/MC/AArch64/SME2p2/directive-cpu.s
index 152da398a90654..f77d6c0a7130d5 100644
--- a/llvm/test/MC/AArch64/SME2p2/directive-cpu.s
+++ b/llvm/test/MC/AArch64/SME2p2/directive-cpu.s
@@ -1,5 +1,10 @@
// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+// SME2p2 should imply SME2p1
+.cpu generic+sme2p2
+movaz {z0.d, z1.d}, za.d[w8, 0, vgx2]
+// CHECK: movaz { z0.d, z1.d }, za.d[w8, 0, vgx2]
+
.cpu generic+sme2p2
ftmopa za0.s, {z0.s-z1.s}, z0.s, z20[0]
// CHECK: ftmopa za0.s, { z0.s, z1.s }, z0.s, z20[0]
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s b/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
index 090d8af85825a3..cd989f97fa5f4e 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch-negative.s
@@ -1,15 +1,15 @@
// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
-.arch armv9-a+sve2
-.arch armv9-a+nosve2
+// SVE2 should require SVE
+.arch armv9-a+sve2+nosve
tbx z0.b, z1.b, z2.b
// CHECK: error: instruction requires: sve2 or sme
// CHECK-NEXT: tbx z0.b, z1.b, z2.b
-.arch armv9-a+sve-aes+nosve-aes
-aesd z23.b, z23.b, z13.b
-// CHECK: error: instruction requires: sve-aes
-// CHECK-NEXT: aesd z23.b, z23.b, z13.b
+.arch armv9-a+sve2+nosve2
+tbx z0.b, z1.b, z2.b
+// CHECK: error: instruction requires: sve2 or sme
+// CHECK-NEXT: tbx z0.b, z1.b, z2.b
// nosve2-aes should disable sve-aes but not sve2.
.arch armv9-a+sve2-aes+nosve2-aes
@@ -17,44 +17,37 @@ aesd z23.b, z23.b, z13.b
// CHECK: error: instruction requires: sve-aes
// CHECK-NEXT: aesd z23.b, z23.b, z13.b
-.arch armv9-a+sve2-sm4
-.arch armv9-a+nosve2-sm4
+.arch armv9-a+sve2-sm4+nosve2-sm4
sm4e z0.s, z0.s, z0.s
// CHECK: error: instruction requires: sve2-sm4
// CHECK-NEXT: sm4e z0.s, z0.s, z0.s
-.arch armv9-a+sve2-sha3
-.arch armv9-a+nosve2-sha3
+.arch armv9-a+sve2-sha3+nosve2-sha3
rax1 z0.d, z0.d, z0.d
// CHECK: error: instruction requires: sve2-sha3
// CHECK-NEXT: rax1 z0.d, z0.d, z0.d
-.arch armv9-a+sve2-bitperm
-.arch armv9-a+nosve2-bitperm
+.arch armv9-a+sve2-bitperm+nosve2-bitperm
bgrp z21.s, z10.s, z21.s
// CHECK: error: instruction requires: sve2-bitperm
// CHECK-NEXT: bgrp z21.s, z10.s, z21.s
-.arch armv9-a+f8f16mm
-.arch armv9-a+nof8f16mm
+.arch armv9-a+f8f16mm+nof8f16mm
fmmla z23.h, z13.b, z8.b
// CHECK: error: instruction requires: f8f16mm
// CHECK-NEXT: fmmla z23.h, z13.b, z8.b
-.arch armv9-a+f8f32mm
-.arch armv9-a+nof8f32mm
+.arch armv9-a+f8f32mm+nof8f32mm
fmmla z23.s, z13.b, z8.b
// CHECK: error: instruction requires: f8f32mm
// CHECK-NEXT: fmmla z23.s, z13.b, z8.b
-.arch armv9-a+sve-f16f32mm
-.arch armv9-a+nosve-f16f32mm
+.arch armv9-a+sve-f16f32mm+nosve-f16f32mm
fmmla z23.s, z13.h, z8.h
// CHECK: error: instruction requires: sve-f16f32mm
// CHECK-NEXT: fmmla z23.s, z13.h, z8.h
-.arch armv9-a+sve-bfscale
-.arch armv9-a+nosve-bfscale
+.arch armv9-a+sve-bfscale+nosve-bfscale
bfscale z0.h, p0/m, z0.h, z0.h
// CHECK: error: instruction requires: sve-bfscale
// CHECK-NEXT: bfscale z0.h, p0/m, z0.h, z0.h
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch.s b/llvm/test/MC/AArch64/SVE2/directive-arch.s
index 1319a8a186971c..8f6880200ea422 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch.s
@@ -1,5 +1,10 @@
// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+// SVE2 should imply SVE
+.arch armv9-a+sve2
+add z23.d, z13.d, z8.d
+// CHECK: add z23.d, z13.d, z8.d
+
.arch armv9-a+sve2
tbx z0.b, z1.b, z2.b
// CHECK: tbx z0.b, z1.b, z2.b
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
index fbe84d0c95a435..c8b466c715fe82 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch_extension-negative.s
@@ -1,5 +1,11 @@
// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+// SVE2 should require SVE
+.cpu generic+sve2+nosve
+tbx z0.b, z1.b, z2.b
+// CHECK: error: instruction requires: sve2 or sme
+// CHECK-NEXT: tbx z0.b, z1.b, z2.b
+
.arch_extension sve2
.arch_extension nosve2
tbx z0.b, z1.b, z2.b
diff --git a/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s b/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
index ce56127ca93b1c..559f2f8d22c3b0 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-arch_extension.s
@@ -1,5 +1,10 @@
// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+// SVE2 should imply SVE
+.arch_extension sve2
+add z23.d, z13.d, z8.d
+// CHECK: add z23.d, z13.d, z8.d
+
.arch_extension sve2
tbx z0.b, z1.b, z2.b
// CHECK: tbx z0.b, z1.b, z2.b
@@ -8,10 +13,6 @@ tbx z0.b, z1.b, z2.b
aesd z23.b, z23.b, z13.b
// CHECK: aesd z23.b, z23.b, z13.b
-.arch_extension sve2-aes
-aesd z23.b, z23.b, z13.b
-// CHECK: aesd z23.b, z23.b, z13.b
-
.arch_extension sve2-sm4
sm4e z0.s, z0.s, z0.s
// CHECK: sm4e z0.s, z0.s, z0.s
diff --git a/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s b/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
index a0c52cf29682a3..1ffd3c02b69b06 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-cpu-negative.s
@@ -1,7 +1,12 @@
// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
-.cpu generic+sve2
-.cpu generic+nosve2
+// SVE2 should require SVE
+.cpu generic+sve2+nosve
+tbx z0.b, z1.b, z2.b
+// CHECK: error: instruction requires: sve2 or sme
+// CHECK-NEXT: tbx z0.b, z1.b, z2.b
+
+.cpu generic+sve2+nosve2
tbx z0.b, z1.b, z2.b
// CHECK: error: instruction requires: sve2 or sme
// CHECK-NEXT: tbx z0.b, z1.b, z2.b
@@ -17,44 +22,37 @@ aesd z23.b, z23.b, z13.b
// CHECK: error: instruction requires: sve2 sve-aes
// CHECK-NEXT: aesd z23.b, z23.b, z13.b
-.cpu generic+sve2-sm4
-.cpu generic+nosve2-sm4
+.cpu generic+sve2-sm4+nosve2-sm4
sm4e z0.s, z0.s, z0.s
// CHECK: error: instruction requires: sve2-sm4
// CHECK-NEXT: sm4e z0.s, z0.s, z0.s
-.cpu generic+sve2-sha3
-.cpu generic+nosve2-sha3
+.cpu generic+sve2-sha3+nosve2-sha3
rax1 z0.d, z0.d, z0.d
// CHECK: error: instruction requires: sve2-sha3
// CHECK-NEXT: rax1 z0.d, z0.d, z0.d
-.cpu generic+sve2-bitperm
-.cpu generic+nosve2-bitperm
+.cpu generic+sve2-bitperm+nosve2-bitperm
bgrp z21.s, z10.s, z21.s
// CHECK: error: instruction requires: sve2-bitperm
// CHECK-NEXT: bgrp z21.s, z10.s, z21.s
-.cpu generic+sve2+f8f16mm
-.cpu generic+sve2+nof8f16mm
+.cpu generic+sve2+f8f16mm+nof8f16mm
fmmla z23.h, z13.b, z8.b
// CHECK: error: instruction requires: f8f16mm
// CHECK-NEXT: fmmla z23.h, z13.b, z8.b
-.cpu generic+sve2+f8f32mm
-.cpu generic+sve2+nof8f32mm
+.cpu generic+sve2+f8f32mm+nof8f32mm
fmmla z23.s, z13.b, z8.b
// CHECK: error: instruction requires: f8f32mm
// CHECK-NEXT: fmmla z23.s, z13.b, z8.b
-.cpu generic+sve-f16f32mm
-.cpu generic+nosve-f16f32mm
+.cpu generic+sve-f16f32mm+nosve-f16f32mm
fmmla z23.s, z13.h, z8.h
// CHECK: error: instruction requires: sve-f16f32mm
// CHECK-NEXT: fmmla z23.s, z13.h, z8.h
-.cpu generic+sve-bfscale
-.cpu generic+nosve-bfscale
+.cpu generic+sve-bfscale+nosve-bfscale
bfscale z0.h, p0/m, z0.h, z0.h
// CHECK: error: instruction requires: sve-bfscale
// CHECK-NEXT: bfscale z0.h, p0/m, z0.h, z0.h
diff --git a/llvm/test/MC/AArch64/SVE2/directive-cpu.s b/llvm/test/MC/AArch64/SVE2/directive-cpu.s
index c54a3a9f272c3d..402f30789dee4e 100644
--- a/llvm/test/MC/AArch64/SVE2/directive-cpu.s
+++ b/llvm/test/MC/AArch64/SVE2/directive-cpu.s
@@ -1,5 +1,10 @@
// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+// SVE2 should imply SVE
+.cpu generic+sve2
+add z23.d, z13.d, z8.d
+// CHECK: add z23.d, z13.d, z8.d
+
.cpu generic+sve2
tbx z0.b, z1.b, z2.b
// CHECK: tbx z0.b, z1.b, z2.b
diff --git a/llvm/test/MC/AArch64/SVE2p1/directive-arch-negative.s b/llvm/test/MC/AArch64/SVE2p1/directive-arch-negative.s
index e82c92df451dd3..49c03f90236429 100644
--- a/llvm/test/MC/AArch64/SVE2p1/directive-arch-negative.s
+++ b/llvm/test/MC/AArch64/SVE2p1/directive-arch-negative.s
@@ -1,19 +1,22 @@
// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
-.arch armv9-a+sve2p1
-.arch armv9-a+nosve2p1
+// SVE2p1 should require SVE2
+.arch armv9-a+sve2p1+nosve2
sclamp z0.s, z1.s, z2.s
// CHECK: error: instruction requires: sme or sve2p1
-// CHECK: sclamp z0.s, z1.s, z2.s
+// CHECK-NEXT: sclamp z0.s, z1.s, z2.s
-.arch armv9-a+sve2p1+sve-b16b16
-.arch armv9-a+sve2p1+nosve-b16b16
+.arch armv9-a+sve2p1+nosve2p1
+sclamp z0.s, z1.s, z2.s
+// CHECK: error: instruction requires: sme or sve2p1
+// CHECK-NEXT: sclamp z0.s, z1.s, z2.s
+
+.arch armv9-a+sve2p1+sve-b16b16+nosve-b16b16
bfadd z23.h, p3/m, z23.h, z13.h
// CHECK: error: instruction requires: sve-b16b16
-// CHECK: bfadd z23.h, p3/m, z23.h, z13.h
+// CHECK-NEXT: bfadd z23.h, p3/m, z23.h, z13.h
-.arch armv9-a+sve2p1+sve-aes2
-.arch armv9-a+nosve-aes2
+.arch armv9-a+sve2p1+sve-aes2+nosve-aes2
aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
-// CHECK: error: instruction requires: sve2p1 or ssve-aes sve-aes2
-// CHECK: aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
\ No newline at end of file
+// CHECK: error: instruction requires: sve-aes2
+// CHECK-NEXT: aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE2p1/directive-arch.s b/llvm/test/MC/AArch64/SVE2p1/directive-arch.s
index bf035d2accdbbf..066d2e2b78bd1c 100644
--- a/llvm/test/MC/AArch64/SVE2p1/directive-arch.s
+++ b/llvm/test/MC/AArch64/SVE2p1/directive-arch.s
@@ -1,5 +1,10 @@
// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+// SVE2p1 should imply SVE2
+.arch armv9-a+sve2p1
+tbx z0.b, z1.b, z2.b
+// CHECK: tbx z0.b, z1.b, z2.b
+
.arch armv9-a+sve2p1
sclamp z0.s, z1.s, z2.s
// CHECK: sclamp z0.s, z1.s, z2.s
diff --git a/llvm/test/MC/AArch64/SVE2p1/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/SVE2p1/directive-arch_extension-negative.s
index 4ab6373ee8a2ac..0957e98b9a3ba6 100644
--- a/llvm/test/MC/AArch64/SVE2p1/directive-arch_extension-negative.s
+++ b/llvm/test/MC/AArch64/SVE2p1/directive-arch_extension-negative.s
@@ -1,20 +1,27 @@
// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+// SVE2p1 should require SVE2
+.arch_extension sve2p1
+.arch_extension nosve2
+sclamp z0.s, z1.s, z2.s
+// CHECK: error: instruction requires: sme or sve2p1
+// CHECK-NEXT: sclamp z0.s, z1.s, z2.s
+
.arch_extension sve2p1
.arch_extension nosve2p1
sclamp z0.s, z1.s, z2.s
// CHECK: error: instruction requires: sme or sve2p1
-// CHECK: sclamp z0.s, z1.s, z2.s
+// CHECK-NEXT: sclamp z0.s, z1.s, z2.s
.arch_extension sve2p1
.arch_extension sve-b16b16
.arch_extension nosve-b16b16
bfadd z23.h, p3/m, z23.h, z13.h
// CHECK: error: instruction requires: sve-b16b16
-// CHECK: bfadd z23.h, p3/m, z23.h, z13.h
+// CHECK-NEXT: bfadd z23.h, p3/m, z23.h, z13.h
.arch_extension sve-aes2
.arch_extension nosve-aes2
aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
// CHECK: error: instruction requires: sve-aes2
-// CHECK: {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
\ No newline at end of file
+// CHECK-NEXT: aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE2p1/directive-arch_extension.s b/llvm/test/MC/AArch64/SVE2p1/directive-arch_extension.s
index d33e0812a0e0bf..8caec61b9d4618 100644
--- a/llvm/test/MC/AArch64/SVE2p1/directive-arch_extension.s
+++ b/llvm/test/MC/AArch64/SVE2p1/directive-arch_extension.s
@@ -1,5 +1,10 @@
// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+// SVE2p1 should imply SVE2
+.arch_extension sve2p1
+tbx z0.b, z1.b, z2.b
+// CHECK: tbx z0.b, z1.b, z2.b
+
.arch_extension sve2p1
sclamp z0.s, z1.s, z2.s
// CHECK: sclamp z0.s, z1.s, z2.s
diff --git a/llvm/test/MC/AArch64/SVE2p1/directive-cpu-negative.s b/llvm/test/MC/AArch64/SVE2p1/directive-cpu-negative.s
new file mode 100644
index 00000000000000..5790d3d95b8be0
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/directive-cpu-negative.s
@@ -0,0 +1,22 @@
+// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+
+// SVE2p1 should require SVE2
+.cpu generic+sve2p1+nosve2
+sclamp z0.s, z1.s, z2.s
+// CHECK: error: instruction requires: sme or sve2p1
+// CHECK-NEXT: sclamp z0.s, z1.s, z2.s
+
+.cpu generic+sve2p1+nosve2p1
+sclamp z0.s, z1.s, z2.s
+// CHECK: error: instruction requires: sme or sve2p1
+// CHECK-NEXT: sclamp z0.s, z1.s, z2.s
+
+.cpu generic+sve2p1+sve-b16b16+nosve-b16b16
+bfadd z23.h, p3/m, z23.h, z13.h
+// CHECK: error: instruction requires: sve-b16b16
+// CHECK-NEXT: bfadd z23.h, p3/m, z23.h, z13.h
+
+.cpu generic+sve2p1+sve-aes2+nosve-aes2
+aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
+// CHECK: error: instruction requires: sve-aes2
+// CHECK-NEXT: aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE2p1/directive-cpu.s b/llvm/test/MC/AArch64/SVE2p1/directive-cpu.s
new file mode 100644
index 00000000000000..7ea90b35bb3918
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/directive-cpu.s
@@ -0,0 +1,18 @@
+// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+
+// SVE2p1 should imply SVE2
+.cpu generic+sve2p1
+tbx z0.b, z1.b, z2.b
+// CHECK: tbx z0.b, z1.b, z2.b
+
+.cpu generic+sve2p1
+sclamp z0.s, z1.s, z2.s
+// CHECK: sclamp z0.s, z1.s, z2.s
+
+.cpu generic+sve2p1+sve-b16b16
+bfadd z23.h, p3/m, z23.h, z13.h
+// CHECK: bfadd z23.h, p3/m, z23.h, z13.h
+
+.cpu generic+sve2p1+sve-aes2
+aesdimc {z0.b-z3.b}, {z0.b-z3.b}, z0.q[0]
+// CHECK: aesdimc { z0.b - z3.b }, { z0.b - z3.b }, z0.q[0]
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE2p2/directive-arch-negative.s b/llvm/test/MC/AArch64/SVE2p2/directive-arch-negative.s
index 6d5837eddec2cd..558f5852ccd5d6 100644
--- a/llvm/test/MC/AArch64/SVE2p2/directive-arch-negative.s
+++ b/llvm/test/MC/AArch64/SVE2p2/directive-arch-negative.s
@@ -1,7 +1,12 @@
// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
-.arch armv9-a+sve2p2
-.arch armv9-a+nosve2p2
+// SVE2p2 should require SVE2p1
+.arch armv9-a+sve2p2+nosve2p1
+bfcvtnt z23.h, p3/z, z13.s
+// CHECK: error: instruction requires: sme2p2 or sve2p2
+// CHECK-NEXT: bfcvtnt z23.h, p3/z, z13.s
+
+.arch armv9-a+sve2p2+nosve2p2
bfcvtnt z23.h, p3/z, z13.s
// CHECK: error: instruction requires: sme2p2 or sve2p2
// CHECK-NEXT: bfcvtnt z23.h, p3/z, z13.s
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE2p2/directive-arch.s b/llvm/test/MC/AArch64/SVE2p2/directive-arch.s
index e7a5c6efd9d7e3..224807527f60a2 100644
--- a/llvm/test/MC/AArch64/SVE2p2/directive-arch.s
+++ b/llvm/test/MC/AArch64/SVE2p2/directive-arch.s
@@ -1,5 +1,10 @@
// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+// SVE2p2 should imply SVE2p1
+.arch armv9-a+sve2p1
+sclamp z0.s, z1.s, z2.s
+// CHECK: sclamp z0.s, z1.s, z2.s
+
.arch armv9-a+sve2p2
bfcvtnt z23.h, p3/z, z13.s
// CHECK: bfcvtnt z23.h, p3/z, z13.s
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE2p2/directive-arch_extension-negative.s b/llvm/test/MC/AArch64/SVE2p2/directive-arch_extension-negative.s
index 14b4cd722d04db..a792d33bb8371c 100644
--- a/llvm/test/MC/AArch64/SVE2p2/directive-arch_extension-negative.s
+++ b/llvm/test/MC/AArch64/SVE2p2/directive-arch_extension-negative.s
@@ -1,5 +1,12 @@
// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+// SVE2p2 should require SVE2p1
+.arch_extension sve2p2
+.arch_extension nosve2p1
+bfcvtnt z0.h, p0/z, z0.s
+// CHECK: error: instruction requires: sme2p2 or sve2p2
+// CHECK-NEXT: bfcvtnt z0.h, p0/z, z0.s
+
.arch_extension sve2p2
.arch_extension nosve2p2
bfcvtnt z0.h, p0/z, z0.s
diff --git a/llvm/test/MC/AArch64/SVE2p2/directive-arch_extension.s b/llvm/test/MC/AArch64/SVE2p2/directive-arch_extension.s
index d18ac8081b3e08..2d275a19d41aba 100644
--- a/llvm/test/MC/AArch64/SVE2p2/directive-arch_extension.s
+++ b/llvm/test/MC/AArch64/SVE2p2/directive-arch_extension.s
@@ -1,5 +1,10 @@
// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+// SVE2p2 should imply SVE2p1
+.arch_extension sve2p2
+sclamp z0.s, z1.s, z2.s
+// CHECK: sclamp z0.s, z1.s, z2.s
+
.arch_extension sve2p2
bfcvtnt z0.h, p0/z, z0.s
// CHECK: bfcvtnt z0.h, p0/z, z0.s
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE2p2/directive-cpu-negative.s b/llvm/test/MC/AArch64/SVE2p2/directive-cpu-negative.s
index fc172bbf756dbd..76ba33fb4f0022 100644
--- a/llvm/test/MC/AArch64/SVE2p2/directive-cpu-negative.s
+++ b/llvm/test/MC/AArch64/SVE2p2/directive-cpu-negative.s
@@ -1,7 +1,12 @@
// RUN: not llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
-.cpu generic+sve2p2
-.cpu generic+nosve2p2
+// SVE2p2 should require SVE2p1
+.cpu generic+sve2p2+nosve2p1
+fcvtnt z0.s, p0/z, z0.d
+// CHECK: error: instruction requires: sme2p2 or sve2p2
+// CHECK-NEXT: fcvtnt z0.s, p0/z, z0.d
+
+.cpu generic+sve2p2+nosve2p2
fcvtnt z0.s, p0/z, z0.d
// CHECK: error: instruction requires: sme2p2 or sve2p2
// CHECK-NEXT: fcvtnt z0.s, p0/z, z0.d
\ No newline at end of file
diff --git a/llvm/test/MC/AArch64/SVE2p2/directive-cpu.s b/llvm/test/MC/AArch64/SVE2p2/directive-cpu.s
index 7874fa10f393c5..27ac60d9a3c6b6 100644
--- a/llvm/test/MC/AArch64/SVE2p2/directive-cpu.s
+++ b/llvm/test/MC/AArch64/SVE2p2/directive-cpu.s
@@ -1,5 +1,10 @@
// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
+// SVE2p2 should implu SVE2p1
+.cpu generic+sve2p2
+sclamp z0.s, z1.s, z2.s
+// CHECK: sclamp z0.s, z1.s, z2.s
+
.cpu generic+sve2p2
fcvtnt z0.s, p0/z, z0.d
// CHECK: fcvtnt z0.s, p0/z, z0.d
\ No newline at end of file
>From dbe2b1f22e8e6031293af5e41480ff58aadab6d1 Mon Sep 17 00:00:00 2001
From: Spencer Abson <Spencer.Abson at arm.com>
Date: Thu, 14 Nov 2024 15:56:25 +0000
Subject: [PATCH 2/2] [NFC] fix typo
---
llvm/test/MC/AArch64/SVE2p2/directive-cpu.s | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/MC/AArch64/SVE2p2/directive-cpu.s b/llvm/test/MC/AArch64/SVE2p2/directive-cpu.s
index 27ac60d9a3c6b6..119cdc617defb4 100644
--- a/llvm/test/MC/AArch64/SVE2p2/directive-cpu.s
+++ b/llvm/test/MC/AArch64/SVE2p2/directive-cpu.s
@@ -1,6 +1,6 @@
// RUN: llvm-mc -triple aarch64 -filetype asm -o - %s 2>&1 | FileCheck %s
-// SVE2p2 should implu SVE2p1
+// SVE2p2 should imply SVE2p1
.cpu generic+sve2p2
sclamp z0.s, z1.s, z2.s
// CHECK: sclamp z0.s, z1.s, z2.s
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