[llvm] [InitUndef] handleSubReg should skip artificial subregs. (PR #116248)

[Sander de Smalen via llvm-commits]

https://github.com/sdesmalen-arm created https://github.com/llvm/llvm-project/pull/116248

When enabling subreg liveness tracking for AArch64, this pass fails because it tries to get the register class for the artificial subreg `sub_32_hi` of a 64-bit GPR. It tries to create an INIT_UNDEF instruction for the top 32-bits of the 64-bit GPR, which are not directly addressable, so getSubRegisterClass() returns a nullptr, crashing this pass.

It should instead just avoid trying to create the INIT_UNDEF instruction.

>From e70e3346641f4c018197e748733be90d3320c35c Mon Sep 17 00:00:00 2001
From: Sander de Smalen <sander.desmalen at arm.com>
Date: Wed, 30 Oct 2024 15:41:48 +0000
Subject: [PATCH] [InitUndef] handleSubReg should skip artificial subregs.

When enabling subreg liveness tracking for AArch64, this pass fails
because it tries to get the register class for the artificial subreg
`sub_32_hi` of a 64-bit GPR. It tries to create an INIT_UNDEF instruction
for the top 32-bits of the 64-bit GPR, which are not directly addressable,
so getSubRegisterClass() returns a nullptr, crashing this pass.

It should instead just avoid trying to create the INIT_UNDEF instruction.
---
 llvm/lib/CodeGen/InitUndef.cpp           | 9 +++++++++
 llvm/test/CodeGen/AArch64/init-undef.mir | 3 ++-
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/CodeGen/InitUndef.cpp b/llvm/lib/CodeGen/InitUndef.cpp
index d4ac131a32a959..7b00611b63b7bf 100644
--- a/llvm/lib/CodeGen/InitUndef.cpp
+++ b/llvm/lib/CodeGen/InitUndef.cpp
@@ -164,6 +164,15 @@ bool InitUndef::handleSubReg(MachineFunction &MF, MachineInstr &MI,
     TRI->getCoveringSubRegIndexes(*MRI, TargetRegClass, NeedDef,
                                   SubRegIndexNeedInsert);
 
+    // It's not possible to create the INIT_UNDEF when there is no register
+    // class associated for the subreg. This may happen for artificial subregs
+    // that are not directly addressable.
+    if (any_of(SubRegIndexNeedInsert,
+               [&TRI = TRI, &TargetRegClass](unsigned ind) -> bool {
+                 return !TRI->getSubRegisterClass(TargetRegClass, ind);
+               }))
+      continue;
+
     Register LatestReg = Reg;
     for (auto ind : SubRegIndexNeedInsert) {
       Changed = true;
diff --git a/llvm/test/CodeGen/AArch64/init-undef.mir b/llvm/test/CodeGen/AArch64/init-undef.mir
index 7935c09d7df5ec..c9d23006d35234 100644
--- a/llvm/test/CodeGen/AArch64/init-undef.mir
+++ b/llvm/test/CodeGen/AArch64/init-undef.mir
@@ -1,5 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple=aarch64-- -run-pass=init-undef -o - %s | FileCheck %s
+# RUN: llc -mtriple=aarch64-- -aarch64-enable-subreg-liveness-tracking=false -run-pass=init-undef -o - %s | FileCheck %s
+# RUN: llc -mtriple=aarch64-- -aarch64-enable-subreg-liveness-tracking=true -run-pass=init-undef -o - %s | FileCheck %s
 
 ---
 name:            test_stxp_undef