[llvm] AMDGPU: Update pattern matching from "x&(-1>>(32-y))" to "bfe x, 0, y" (PR #116115)

[Changpeng Fang via llvm-commits]

changpeng wrote:

[AMD Official Use Only - AMD Internal Distribution Only]

Right. So bfe x, 0, 32 is the same as bfe x, 0, 0 and the result is 0.  But x & (-1 >> 0) equals x.

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Subject: Re: [llvm/llvm-project] AMDGPU: Update pattern matching from "x&(-1>>(32-y))" to "bfe x, 0, y" (PR #116115)

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The description in the RDNA3 ISA says D0.u = ((S0.u >> S1.u[4 : 0].u) & 32'U((1 << S2.u[4 : 0].u) - 1))

This says that it only looks at bits 4:0 of S2, so 32 would be treated the same as 0.

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https://github.com/llvm/llvm-project/pull/116115