[llvm] [RISCV] Add mvendorid/marchid/mimpid to CPU definitions (PR #116202)

[Yingwei Zheng via llvm-commits]

================
@@ -435,7 +438,11 @@ def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
                                               TuneZExtHFusion,
                                               TuneZExtWFusion,
                                               TuneShiftedZExtWFusion,
-                                              TuneLDADDFusion]>;
+                                              TuneLDADDFusion]> {
+  let MVendorID = 0x61f;
+  let MArchID = 0x8000000000010000;
+  let MImpID = 0x111;
----------------
dtcxzyw wrote:

For spacemit-k1:
```
mvendorid       : 0x710
marchid         : 0x8000000058000001
mimpid          : 0x1000000049772200
```

https://github.com/llvm/llvm-project/pull/116202