[llvm] [RISCV] Add mvendorid/marchid/mimpid to CPU definitions (PR #116202)
Pengcheng Wang via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 14 02:28:23 PST 2024
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@@ -435,7 +438,11 @@ def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
TuneZExtHFusion,
TuneZExtWFusion,
TuneShiftedZExtWFusion,
- TuneLDADDFusion]>;
+ TuneLDADDFusion]> {
+ let MVendorID = 0x61f;
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wangpc-pp wrote:
This is from https://github.com/qemu/qemu/blob/master/target/riscv/cpu_vendorid.h.
https://github.com/llvm/llvm-project/pull/116202
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