[llvm] debfd7b - [msan] Remove unnecacary zero increment (#116185)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 14 00:59:05 PST 2024
Author: Vitaly Buka
Date: 2024-11-14T00:59:01-08:00
New Revision: debfd7b0b44d8eb0bfe9f69933251a67f752f0b5
URL: https://github.com/llvm/llvm-project/commit/debfd7b0b44d8eb0bfe9f69933251a67f752f0b5
DIFF: https://github.com/llvm/llvm-project/commit/debfd7b0b44d8eb0bfe9f69933251a67f752f0b5.diff
LOG: [msan] Remove unnecacary zero increment (#116185)
Added:
Modified:
llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
llvm/test/Instrumentation/MemorySanitizer/ARM32/vararg-arm32.ll
llvm/test/Instrumentation/MemorySanitizer/LoongArch/vararg-loongarch64.ll
llvm/test/Instrumentation/MemorySanitizer/LoongArch/vararg.ll
llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll
llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll
llvm/test/Instrumentation/MemorySanitizer/Mips32/vararg-mips.ll
llvm/test/Instrumentation/MemorySanitizer/Mips32/vararg-mipsel.ll
llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll
llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll
llvm/test/Instrumentation/MemorySanitizer/PowerPC32/kernel-ppcle.ll
llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppc.ll
llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppcle.ll
llvm/test/Instrumentation/MemorySanitizer/RISCV32/vararg-riscv32.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
index f7d4eadafc7df6..8c2fde8453a74a 100644
--- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
@@ -5685,8 +5685,7 @@ struct VarArgPowerPCHelper : public VarArgHelperBase {
"finalizeInstrumentation called twice");
IRBuilder<> IRB(MSV.FnPrologueEnd);
VAArgSize = IRB.CreateLoad(IRB.getInt64Ty(), MS.VAArgOverflowSizeTLS);
- Value *CopySize =
- IRB.CreateAdd(ConstantInt::get(MS.IntptrTy, 0), VAArgSize);
+ Value *CopySize = VAArgSize;
if (!VAStartInstrumentationList.empty()) {
// If there is a va_start in this function, make a backup copy of
@@ -5699,7 +5698,7 @@ struct VarArgPowerPCHelper : public VarArgHelperBase {
Value *SrcSize = IRB.CreateBinaryIntrinsic(
Intrinsic::umin, CopySize,
- ConstantInt::get(MS.IntptrTy, kParamTLSSize));
+ ConstantInt::get(IRB.getInt64Ty(), kParamTLSSize));
IRB.CreateMemCpy(VAArgTLSCopy, kShadowTLSAlignment, MS.VAArgTLS,
kShadowTLSAlignment, SrcSize);
}
@@ -6045,8 +6044,7 @@ struct VarArgGenericHelper : public VarArgHelperBase {
"finalizeInstrumentation called twice");
IRBuilder<> IRB(MSV.FnPrologueEnd);
VAArgSize = IRB.CreateLoad(IRB.getInt64Ty(), MS.VAArgOverflowSizeTLS);
- Value *CopySize =
- IRB.CreateAdd(ConstantInt::get(MS.IntptrTy, 0), VAArgSize);
+ Value *CopySize = VAArgSize;
if (!VAStartInstrumentationList.empty()) {
// If there is a va_start in this function, make a backup copy of
@@ -6058,7 +6056,7 @@ struct VarArgGenericHelper : public VarArgHelperBase {
Value *SrcSize = IRB.CreateBinaryIntrinsic(
Intrinsic::umin, CopySize,
- ConstantInt::get(MS.IntptrTy, kParamTLSSize));
+ ConstantInt::get(IRB.getInt64Ty(), kParamTLSSize));
IRB.CreateMemCpy(VAArgTLSCopy, kShadowTLSAlignment, MS.VAArgTLS,
kShadowTLSAlignment, SrcSize);
}
diff --git a/llvm/test/Instrumentation/MemorySanitizer/ARM32/vararg-arm32.ll b/llvm/test/Instrumentation/MemorySanitizer/ARM32/vararg-arm32.ll
index 149b7c9190cefb..3eccfb3170e242 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/ARM32/vararg-arm32.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/ARM32/vararg-arm32.ll
@@ -7,8 +7,7 @@ target triple = "mips64--linux"
define i32 @foo(i32 %guard, ...) {
; CHECK-LABEL: define i32 @foo(
; CHECK-SAME: i32 [[GUARD:%.*]], ...) {
-; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
+; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
; CHECK-NEXT: [[TMP3:%.*]] = alloca i8, i64 [[TMP2]], align 8
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP3]], i8 0, i64 [[TMP2]], i1 false)
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 800)
@@ -58,7 +57,6 @@ declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #1
define i32 @bar() {
; CHECK-LABEL: define i32 @bar() {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: store i32 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
@@ -87,7 +85,6 @@ declare i32 @foo2(i32 %g1, i32 %g2, ...)
define i32 @bar2() {
; CHECK-LABEL: define i32 @bar2() {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: store i32 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
@@ -113,7 +110,6 @@ define dso_local i64 @many_args() {
; CHECK-LABEL: define dso_local i64 @many_args() {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 0, [[TMP0]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i64 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: store i64 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
diff --git a/llvm/test/Instrumentation/MemorySanitizer/LoongArch/vararg-loongarch64.ll b/llvm/test/Instrumentation/MemorySanitizer/LoongArch/vararg-loongarch64.ll
index 8a4ab59588adb6..23df3fcd903c1e 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/LoongArch/vararg-loongarch64.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/LoongArch/vararg-loongarch64.ll
@@ -11,10 +11,9 @@ declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #1
define i32 @foo(i32 %guard, ...) {
; CHECK-LABEL: @foo
; CHECK: [[TMP1:%.*]] = load {{.*}} @__msan_va_arg_overflow_size_tls
-; CHECK: [[TMP2:%.*]] = add i64 0, [[TMP1]]
-; CHECK: [[TMP3:%.*]] = alloca {{.*}} [[TMP2]]
-; CHECK: call void @llvm.memset.p0.i64(ptr align 8 [[TMP3]], i8 0, i64 [[TMP2]], i1 false)
-; CHECK: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 800)
+; CHECK: [[TMP3:%.*]] = alloca {{.*}} [[TMP1]]
+; CHECK: call void @llvm.memset.p0.i64(ptr align 8 [[TMP3]], i8 0, i64 [[TMP1]], i1 false)
+; CHECK: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP1]], i64 800)
; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP3]], ptr align 8 @__msan_va_arg_tls, i64 [[TMP4]], i1 false)
;
%vl = alloca ptr, align 8
diff --git a/llvm/test/Instrumentation/MemorySanitizer/LoongArch/vararg.ll b/llvm/test/Instrumentation/MemorySanitizer/LoongArch/vararg.ll
index 1ed716e3de3fcc..a8671b48f139c6 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/LoongArch/vararg.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/LoongArch/vararg.ll
@@ -9,8 +9,7 @@ define void @VaStart(ptr %s, ...) {
; CHECK-LABEL: define void @VaStart(
; CHECK-SAME: ptr [[S:%.*]], ...) {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 0, [[TMP0]]
+; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
; CHECK-NEXT: [[TMP2:%.*]] = alloca i8, i64 [[TMP1]], align 8
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP2]], i8 0, i64 [[TMP1]], i1 false)
; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP1]], i64 800)
diff --git a/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll b/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll
index 8c23d954224264..64a76c5fd436a4 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64.ll
@@ -16,12 +16,11 @@ define i32 @foo(i32 %guard, ...) {
; CHECK-LABEL: @foo
; CHECK: [[A:%.*]] = load {{.*}} @__msan_va_arg_overflow_size_tls
-; CHECK: [[B:%.*]] = add i64 0, [[A]]
-; CHECK: [[C:%.*]] = alloca {{.*}} [[B]]
+; CHECK: [[C:%.*]] = alloca {{.*}} [[A]]
-; CHECK: call void @llvm.memset.p0.i64(ptr align 8 [[C]], i8 0, i64 [[B]], i1 false)
+; CHECK: call void @llvm.memset.p0.i64(ptr align 8 [[C]], i8 0, i64 [[A]], i1 false)
-; CHECK: [[D:%.*]] = call i64 @llvm.umin.i64(i64 [[B]], i64 800)
+; CHECK: [[D:%.*]] = call i64 @llvm.umin.i64(i64 [[A]], i64 800)
; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C]], ptr align 8 @__msan_va_arg_tls, i64 [[D]], i1 false)
declare void @llvm.lifetime.start.p0(i64, ptr nocapture) #1
diff --git a/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll b/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll
index 17f4b826be0bee..9f3127e9d89ed0 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/Mips/vararg-mips64el.ll
@@ -16,12 +16,11 @@ define i32 @foo(i32 %guard, ...) {
; CHECK-LABEL: @foo
; CHECK: [[A:%.*]] = load {{.*}} @__msan_va_arg_overflow_size_tls
-; CHECK: [[B:%.*]] = add i64 0, [[A]]
-; CHECK: [[C:%.*]] = alloca {{.*}} [[B]]
+; CHECK: [[C:%.*]] = alloca {{.*}} [[A]]
-; CHECK: call void @llvm.memset.p0.i64(ptr align 8 [[C]], i8 0, i64 [[B]], i1 false)
+; CHECK: call void @llvm.memset.p0.i64(ptr align 8 [[C]], i8 0, i64 [[A]], i1 false)
-; CHECK: [[D:%.*]] = call i64 @llvm.umin.i64(i64 [[B]], i64 800)
+; CHECK: [[D:%.*]] = call i64 @llvm.umin.i64(i64 [[A]], i64 800)
; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C]], ptr align 8 @__msan_va_arg_tls, i64 [[D]], i1 false)
declare void @llvm.lifetime.start.p0(i64, ptr nocapture) #1
diff --git a/llvm/test/Instrumentation/MemorySanitizer/Mips32/vararg-mips.ll b/llvm/test/Instrumentation/MemorySanitizer/Mips32/vararg-mips.ll
index 149b7c9190cefb..3eccfb3170e242 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/Mips32/vararg-mips.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/Mips32/vararg-mips.ll
@@ -7,8 +7,7 @@ target triple = "mips64--linux"
define i32 @foo(i32 %guard, ...) {
; CHECK-LABEL: define i32 @foo(
; CHECK-SAME: i32 [[GUARD:%.*]], ...) {
-; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
+; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
; CHECK-NEXT: [[TMP3:%.*]] = alloca i8, i64 [[TMP2]], align 8
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP3]], i8 0, i64 [[TMP2]], i1 false)
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 800)
@@ -58,7 +57,6 @@ declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #1
define i32 @bar() {
; CHECK-LABEL: define i32 @bar() {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: store i32 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
@@ -87,7 +85,6 @@ declare i32 @foo2(i32 %g1, i32 %g2, ...)
define i32 @bar2() {
; CHECK-LABEL: define i32 @bar2() {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: store i32 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
@@ -113,7 +110,6 @@ define dso_local i64 @many_args() {
; CHECK-LABEL: define dso_local i64 @many_args() {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 0, [[TMP0]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i64 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: store i64 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
diff --git a/llvm/test/Instrumentation/MemorySanitizer/Mips32/vararg-mipsel.ll b/llvm/test/Instrumentation/MemorySanitizer/Mips32/vararg-mipsel.ll
index c24309f504b01e..9dc4f70e9078f2 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/Mips32/vararg-mipsel.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/Mips32/vararg-mipsel.ll
@@ -7,8 +7,7 @@ target triple = "mips64el--linux"
define i32 @foo(i32 %guard, ...) {
; CHECK-LABEL: define i32 @foo(
; CHECK-SAME: i32 [[GUARD:%.*]], ...) {
-; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
+; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
; CHECK-NEXT: [[TMP3:%.*]] = alloca i8, i64 [[TMP2]], align 8
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP3]], i8 0, i64 [[TMP2]], i1 false)
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 800)
@@ -58,7 +57,6 @@ declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #1
define i32 @bar() {
; CHECK-LABEL: define i32 @bar() {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: store i32 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
@@ -86,7 +84,6 @@ declare i32 @foo2(i32 %g1, i32 %g2, ...)
define i32 @bar2() {
; CHECK-LABEL: define i32 @bar2() {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: store i32 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
@@ -112,7 +109,6 @@ define dso_local i64 @many_args() {
; CHECK-LABEL: define dso_local i64 @many_args() {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 0, [[TMP0]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i64 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: store i64 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
diff --git a/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll b/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll
index db09c5a4771868..45e8b2d16854a0 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64.ll
@@ -16,12 +16,11 @@ define i32 @foo(i32 %guard, ...) {
; CHECK-LABEL: @foo
; CHECK: [[A:%.*]] = load {{.*}} @__msan_va_arg_overflow_size_tls
-; CHECK: [[B:%.*]] = add i64 0, [[A]]
-; CHECK: [[C:%.*]] = alloca {{.*}} [[B]]
+; CHECK: [[C:%.*]] = alloca {{.*}} [[A]]
-; CHECK: call void @llvm.memset.p0.i64(ptr align 8 [[C]], i8 0, i64 [[B]], i1 false)
+; CHECK: call void @llvm.memset.p0.i64(ptr align 8 [[C]], i8 0, i64 [[A]], i1 false)
-; CHECK: [[D:%.*]] = call i64 @llvm.umin.i64(i64 [[B]], i64 800)
+; CHECK: [[D:%.*]] = call i64 @llvm.umin.i64(i64 [[A]], i64 800)
; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C]], ptr align 8 @__msan_va_arg_tls, i64 [[D]], i1 false)
declare void @llvm.lifetime.start.p0(i64, ptr nocapture) #1
diff --git a/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll b/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll
index 63e11dc7cadd09..d6b956c821e54e 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/PowerPC/vararg-ppc64le.ll
@@ -16,12 +16,11 @@ define i32 @foo(i32 %guard, ...) {
; CHECK-LABEL: @foo
; CHECK: [[A:%.*]] = load {{.*}} @__msan_va_arg_overflow_size_tls
-; CHECK: [[B:%.*]] = add i64 0, [[A]]
-; CHECK: [[C:%.*]] = alloca {{.*}} [[B]]
+; CHECK: [[C:%.*]] = alloca {{.*}} [[A]]
-; CHECK: call void @llvm.memset.p0.i64(ptr align 8 [[C]], i8 0, i64 [[B]], i1 false)
+; CHECK: call void @llvm.memset.p0.i64(ptr align 8 [[C]], i8 0, i64 [[A]], i1 false)
-; CHECK: [[D:%.*]] = call i64 @llvm.umin.i64(i64 [[B]], i64 800)
+; CHECK: [[D:%.*]] = call i64 @llvm.umin.i64(i64 [[A]], i64 800)
; CHECK: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[C]], ptr align 8 @__msan_va_arg_tls, i64 [[D]], i1 false)
declare void @llvm.lifetime.start.p0(i64, ptr nocapture) #1
diff --git a/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/kernel-ppcle.ll b/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/kernel-ppcle.ll
index 899cfca6dcaaa8..e7c78f12a17145 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/kernel-ppcle.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/kernel-ppcle.ll
@@ -23,7 +23,6 @@ define void @Store1(ptr %p, i8 %x) sanitize_memory {
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
-; CHECK-NEXT: [[TMP6:%.*]] = add i64 0, [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PARAM_SHADOW]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 8
; CHECK-NEXT: [[_MSARG1:%.*]] = inttoptr i64 [[TMP8]] to ptr
@@ -34,22 +33,22 @@ define void @Store1(ptr %p, i8 %x) sanitize_memory {
; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[_MSARG_O2]], align 4
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
-; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1:![0-9]+]]
-; CHECK: [[BB13]]:
+; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB12:.*]], label %[[BB13:.*]], !prof [[PROF1:![0-9]+]]
+; CHECK: [[BB12]]:
; CHECK-NEXT: call void @__msan_warning(i32 [[TMP4]]) #[[ATTR2:[0-9]+]]
-; CHECK-NEXT: br label %[[BB14]]
-; CHECK: [[BB14]]:
+; CHECK-NEXT: br label %[[BB13]]
+; CHECK: [[BB13]]:
; CHECK-NEXT: [[TMP15:%.*]] = call { ptr, ptr } @__msan_metadata_ptr_for_store_1(ptr [[P]])
; CHECK-NEXT: [[TMP16:%.*]] = extractvalue { ptr, ptr } [[TMP15]], 0
; CHECK-NEXT: [[TMP17:%.*]] = extractvalue { ptr, ptr } [[TMP15]], 1
; CHECK-NEXT: store i8 [[TMP9]], ptr [[TMP16]], align 1
; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i8 [[TMP9]], 0
-; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB18:.*]], label %[[BB20:.*]], !prof [[PROF1]]
-; CHECK: [[BB18]]:
+; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB17:.*]], label %[[BB19:.*]], !prof [[PROF1]]
+; CHECK: [[BB17]]:
; CHECK-NEXT: [[TMP19:%.*]] = call i32 @__msan_chain_origin(i32 [[TMP12]])
; CHECK-NEXT: store i32 [[TMP19]], ptr [[TMP17]], align 4
-; CHECK-NEXT: br label %[[BB20]]
-; CHECK: [[BB20]]:
+; CHECK-NEXT: br label %[[BB19]]
+; CHECK: [[BB19]]:
; CHECK-NEXT: store i8 [[X]], ptr [[P]], align 1
; CHECK-NEXT: ret void
;
@@ -78,7 +77,6 @@ define void @Store2(ptr %p, i16 %x) sanitize_memory {
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
-; CHECK-NEXT: [[TMP6:%.*]] = add i64 0, [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PARAM_SHADOW]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 8
; CHECK-NEXT: [[_MSARG1:%.*]] = inttoptr i64 [[TMP8]] to ptr
@@ -89,22 +87,22 @@ define void @Store2(ptr %p, i16 %x) sanitize_memory {
; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[_MSARG_O2]], align 4
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
-; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]
-; CHECK: [[BB13]]:
+; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB12:.*]], label %[[BB13:.*]], !prof [[PROF1]]
+; CHECK: [[BB12]]:
; CHECK-NEXT: call void @__msan_warning(i32 [[TMP4]]) #[[ATTR2]]
-; CHECK-NEXT: br label %[[BB14]]
-; CHECK: [[BB14]]:
+; CHECK-NEXT: br label %[[BB13]]
+; CHECK: [[BB13]]:
; CHECK-NEXT: [[TMP15:%.*]] = call { ptr, ptr } @__msan_metadata_ptr_for_store_2(ptr [[P]])
; CHECK-NEXT: [[TMP16:%.*]] = extractvalue { ptr, ptr } [[TMP15]], 0
; CHECK-NEXT: [[TMP17:%.*]] = extractvalue { ptr, ptr } [[TMP15]], 1
; CHECK-NEXT: store i16 [[TMP9]], ptr [[TMP16]], align 2
; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i16 [[TMP9]], 0
-; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB18:.*]], label %[[BB20:.*]], !prof [[PROF1]]
-; CHECK: [[BB18]]:
+; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB17:.*]], label %[[BB19:.*]], !prof [[PROF1]]
+; CHECK: [[BB17]]:
; CHECK-NEXT: [[TMP19:%.*]] = call i32 @__msan_chain_origin(i32 [[TMP12]])
; CHECK-NEXT: store i32 [[TMP19]], ptr [[TMP17]], align 4
-; CHECK-NEXT: br label %[[BB20]]
-; CHECK: [[BB20]]:
+; CHECK-NEXT: br label %[[BB19]]
+; CHECK: [[BB19]]:
; CHECK-NEXT: store i16 [[X]], ptr [[P]], align 2
; CHECK-NEXT: ret void
;
@@ -133,7 +131,6 @@ define void @Store4(ptr %p, i32 %x) sanitize_memory {
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
-; CHECK-NEXT: [[TMP6:%.*]] = add i64 0, [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PARAM_SHADOW]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 8
; CHECK-NEXT: [[_MSARG1:%.*]] = inttoptr i64 [[TMP8]] to ptr
@@ -144,22 +141,22 @@ define void @Store4(ptr %p, i32 %x) sanitize_memory {
; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[_MSARG_O2]], align 4
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
-; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]
-; CHECK: [[BB13]]:
+; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB12:.*]], label %[[BB13:.*]], !prof [[PROF1]]
+; CHECK: [[BB12]]:
; CHECK-NEXT: call void @__msan_warning(i32 [[TMP4]]) #[[ATTR2]]
-; CHECK-NEXT: br label %[[BB14]]
-; CHECK: [[BB14]]:
+; CHECK-NEXT: br label %[[BB13]]
+; CHECK: [[BB13]]:
; CHECK-NEXT: [[TMP15:%.*]] = call { ptr, ptr } @__msan_metadata_ptr_for_store_4(ptr [[P]])
; CHECK-NEXT: [[TMP16:%.*]] = extractvalue { ptr, ptr } [[TMP15]], 0
; CHECK-NEXT: [[TMP17:%.*]] = extractvalue { ptr, ptr } [[TMP15]], 1
; CHECK-NEXT: store i32 [[TMP9]], ptr [[TMP16]], align 4
; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i32 [[TMP9]], 0
-; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB18:.*]], label %[[BB20:.*]], !prof [[PROF1]]
-; CHECK: [[BB18]]:
+; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB17:.*]], label %[[BB19:.*]], !prof [[PROF1]]
+; CHECK: [[BB17]]:
; CHECK-NEXT: [[TMP19:%.*]] = call i32 @__msan_chain_origin(i32 [[TMP12]])
; CHECK-NEXT: store i32 [[TMP19]], ptr [[TMP17]], align 4
-; CHECK-NEXT: br label %[[BB20]]
-; CHECK: [[BB20]]:
+; CHECK-NEXT: br label %[[BB19]]
+; CHECK: [[BB19]]:
; CHECK-NEXT: store i32 [[X]], ptr [[P]], align 4
; CHECK-NEXT: ret void
;
@@ -188,7 +185,6 @@ define void @Store8(ptr %p, i64 %x) sanitize_memory {
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
-; CHECK-NEXT: [[TMP6:%.*]] = add i64 0, [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PARAM_SHADOW]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 8
; CHECK-NEXT: [[_MSARG1:%.*]] = inttoptr i64 [[TMP8]] to ptr
@@ -199,25 +195,25 @@ define void @Store8(ptr %p, i64 %x) sanitize_memory {
; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[_MSARG_O2]], align 4
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
-; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]
-; CHECK: [[BB13]]:
+; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB12:.*]], label %[[BB13:.*]], !prof [[PROF1]]
+; CHECK: [[BB12]]:
; CHECK-NEXT: call void @__msan_warning(i32 [[TMP4]]) #[[ATTR2]]
-; CHECK-NEXT: br label %[[BB14]]
-; CHECK: [[BB14]]:
+; CHECK-NEXT: br label %[[BB13]]
+; CHECK: [[BB13]]:
; CHECK-NEXT: [[TMP15:%.*]] = call { ptr, ptr } @__msan_metadata_ptr_for_store_8(ptr [[P]])
; CHECK-NEXT: [[TMP16:%.*]] = extractvalue { ptr, ptr } [[TMP15]], 0
; CHECK-NEXT: [[TMP17:%.*]] = extractvalue { ptr, ptr } [[TMP15]], 1
; CHECK-NEXT: store i64 [[TMP9]], ptr [[TMP16]], align 8
; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP9]], 0
-; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB18:.*]], label %[[BB23:.*]], !prof [[PROF1]]
-; CHECK: [[BB18]]:
+; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB17:.*]], label %[[BB22:.*]], !prof [[PROF1]]
+; CHECK: [[BB17]]:
; CHECK-NEXT: [[TMP19:%.*]] = call i32 @__msan_chain_origin(i32 [[TMP12]])
; CHECK-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
; CHECK-NEXT: [[TMP21:%.*]] = shl i64 [[TMP20]], 32
; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP20]], [[TMP21]]
; CHECK-NEXT: store i64 [[TMP22]], ptr [[TMP17]], align 8
-; CHECK-NEXT: br label %[[BB23]]
-; CHECK: [[BB23]]:
+; CHECK-NEXT: br label %[[BB22]]
+; CHECK: [[BB22]]:
; CHECK-NEXT: store i64 [[X]], ptr [[P]], align 8
; CHECK-NEXT: ret void
;
@@ -246,7 +242,6 @@ define void @Store16(ptr %p, i128 %x) sanitize_memory {
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
-; CHECK-NEXT: [[TMP6:%.*]] = add i64 0, [[TMP5]]
; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[PARAM_SHADOW]] to i64
; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 8
; CHECK-NEXT: [[_MSARG1:%.*]] = inttoptr i64 [[TMP8]] to ptr
@@ -257,18 +252,18 @@ define void @Store16(ptr %p, i128 %x) sanitize_memory {
; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[_MSARG_O2]], align 4
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
-; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB13:.*]], label %[[BB14:.*]], !prof [[PROF1]]
-; CHECK: [[BB13]]:
+; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB12:.*]], label %[[BB13:.*]], !prof [[PROF1]]
+; CHECK: [[BB12]]:
; CHECK-NEXT: call void @__msan_warning(i32 [[TMP4]]) #[[ATTR2]]
-; CHECK-NEXT: br label %[[BB14]]
-; CHECK: [[BB14]]:
+; CHECK-NEXT: br label %[[BB13]]
+; CHECK: [[BB13]]:
; CHECK-NEXT: [[TMP15:%.*]] = call { ptr, ptr } @__msan_metadata_ptr_for_store_n(ptr [[P]], i64 16)
; CHECK-NEXT: [[TMP16:%.*]] = extractvalue { ptr, ptr } [[TMP15]], 0
; CHECK-NEXT: [[TMP17:%.*]] = extractvalue { ptr, ptr } [[TMP15]], 1
; CHECK-NEXT: store i128 [[TMP9]], ptr [[TMP16]], align 8
; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP9]], 0
-; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB18:.*]], label %[[BB24:.*]], !prof [[PROF1]]
-; CHECK: [[BB18]]:
+; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB17:.*]], label %[[BB23:.*]], !prof [[PROF1]]
+; CHECK: [[BB17]]:
; CHECK-NEXT: [[TMP19:%.*]] = call i32 @__msan_chain_origin(i32 [[TMP12]])
; CHECK-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
; CHECK-NEXT: [[TMP21:%.*]] = shl i64 [[TMP20]], 32
@@ -276,8 +271,8 @@ define void @Store16(ptr %p, i128 %x) sanitize_memory {
; CHECK-NEXT: store i64 [[TMP22]], ptr [[TMP17]], align 8
; CHECK-NEXT: [[TMP23:%.*]] = getelementptr i64, ptr [[TMP17]], i32 1
; CHECK-NEXT: store i64 [[TMP22]], ptr [[TMP23]], align 8
-; CHECK-NEXT: br label %[[BB24]]
-; CHECK: [[BB24]]:
+; CHECK-NEXT: br label %[[BB23]]
+; CHECK: [[BB23]]:
; CHECK-NEXT: store i128 [[X]], ptr [[P]], align 8
; CHECK-NEXT: ret void
;
@@ -306,14 +301,13 @@ define i8 @Load1(ptr %p) sanitize_memory {
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
-; CHECK-NEXT: [[TMP6:%.*]] = add i64 0, [[TMP5]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
-; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]
-; CHECK: [[BB7]]:
+; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]
+; CHECK: [[BB6]]:
; CHECK-NEXT: call void @__msan_warning(i32 [[TMP4]]) #[[ATTR2]]
-; CHECK-NEXT: br label %[[BB8]]
-; CHECK: [[BB8]]:
+; CHECK-NEXT: br label %[[BB7]]
+; CHECK: [[BB7]]:
; CHECK-NEXT: [[TMP9:%.*]] = load i8, ptr [[P]], align 1
; CHECK-NEXT: [[TMP10:%.*]] = call { ptr, ptr } @__msan_metadata_ptr_for_load_1(ptr [[P]])
; CHECK-NEXT: [[TMP11:%.*]] = extractvalue { ptr, ptr } [[TMP10]], 0
@@ -349,14 +343,13 @@ define i16 @Load2(ptr %p) sanitize_memory {
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
-; CHECK-NEXT: [[TMP6:%.*]] = add i64 0, [[TMP5]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
-; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]
-; CHECK: [[BB7]]:
+; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]
+; CHECK: [[BB6]]:
; CHECK-NEXT: call void @__msan_warning(i32 [[TMP4]]) #[[ATTR2]]
-; CHECK-NEXT: br label %[[BB8]]
-; CHECK: [[BB8]]:
+; CHECK-NEXT: br label %[[BB7]]
+; CHECK: [[BB7]]:
; CHECK-NEXT: [[TMP9:%.*]] = load i16, ptr [[P]], align 2
; CHECK-NEXT: [[TMP10:%.*]] = call { ptr, ptr } @__msan_metadata_ptr_for_load_2(ptr [[P]])
; CHECK-NEXT: [[TMP11:%.*]] = extractvalue { ptr, ptr } [[TMP10]], 0
@@ -392,14 +385,13 @@ define i32 @Load4(ptr %p) sanitize_memory {
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
-; CHECK-NEXT: [[TMP6:%.*]] = add i64 0, [[TMP5]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
-; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]
-; CHECK: [[BB7]]:
+; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]
+; CHECK: [[BB6]]:
; CHECK-NEXT: call void @__msan_warning(i32 [[TMP4]]) #[[ATTR2]]
-; CHECK-NEXT: br label %[[BB8]]
-; CHECK: [[BB8]]:
+; CHECK-NEXT: br label %[[BB7]]
+; CHECK: [[BB7]]:
; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[P]], align 4
; CHECK-NEXT: [[TMP10:%.*]] = call { ptr, ptr } @__msan_metadata_ptr_for_load_4(ptr [[P]])
; CHECK-NEXT: [[TMP11:%.*]] = extractvalue { ptr, ptr } [[TMP10]], 0
@@ -435,14 +427,13 @@ define i64 @Load8(ptr %p) sanitize_memory {
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
-; CHECK-NEXT: [[TMP6:%.*]] = add i64 0, [[TMP5]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
-; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]
-; CHECK: [[BB7]]:
+; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]
+; CHECK: [[BB6]]:
; CHECK-NEXT: call void @__msan_warning(i32 [[TMP4]]) #[[ATTR2]]
-; CHECK-NEXT: br label %[[BB8]]
-; CHECK: [[BB8]]:
+; CHECK-NEXT: br label %[[BB7]]
+; CHECK: [[BB7]]:
; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr [[P]], align 8
; CHECK-NEXT: [[TMP10:%.*]] = call { ptr, ptr } @__msan_metadata_ptr_for_load_8(ptr [[P]])
; CHECK-NEXT: [[TMP11:%.*]] = extractvalue { ptr, ptr } [[TMP10]], 0
@@ -478,14 +469,13 @@ define i128 @Load16(ptr %p) sanitize_memory {
; CHECK-NEXT: [[_MSARG_O:%.*]] = inttoptr i64 [[TMP3]] to ptr
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[_MSARG_O]], align 4
; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[VA_ARG_OVERFLOW_SIZE]], align 8
-; CHECK-NEXT: [[TMP6:%.*]] = add i64 0, [[TMP5]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 0
-; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB7:.*]], label %[[BB8:.*]], !prof [[PROF1]]
-; CHECK: [[BB7]]:
+; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]
+; CHECK: [[BB6]]:
; CHECK-NEXT: call void @__msan_warning(i32 [[TMP4]]) #[[ATTR2]]
-; CHECK-NEXT: br label %[[BB8]]
-; CHECK: [[BB8]]:
+; CHECK-NEXT: br label %[[BB7]]
+; CHECK: [[BB7]]:
; CHECK-NEXT: [[TMP9:%.*]] = load i128, ptr [[P]], align 8
; CHECK-NEXT: [[TMP10:%.*]] = call { ptr, ptr } @__msan_metadata_ptr_for_load_n(ptr [[P]], i64 16)
; CHECK-NEXT: [[TMP11:%.*]] = extractvalue { ptr, ptr } [[TMP10]], 0
diff --git a/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppc.ll b/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppc.ll
index 359f634fa4cb38..50343106fc2ad2 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppc.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppc.ll
@@ -7,8 +7,7 @@ target triple = "powerpc64--linux"
define i32 @foo(i32 %guard, ...) {
; CHECK-LABEL: define i32 @foo(
; CHECK-SAME: i32 [[GUARD:%.*]], ...) {
-; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
+; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
; CHECK-NEXT: [[TMP3:%.*]] = alloca i8, i64 [[TMP2]], align 8
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP3]], i8 0, i64 [[TMP2]], i1 false)
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 800)
@@ -64,7 +63,6 @@ declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #1
define i32 @bar() {
; CHECK-LABEL: define i32 @bar() {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: store i32 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
@@ -92,7 +90,6 @@ define i32 @bar() {
define i32 @bar2() {
; CHECK-LABEL: define i32 @bar2() {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
@@ -116,7 +113,6 @@ define i32 @bar2() {
define i32 @bar4() {
; CHECK-LABEL: define i32 @bar4() {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: store [2 x i64] zeroinitializer, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
@@ -137,7 +133,6 @@ define i32 @bar4() {
define i32 @bar5() {
; CHECK-LABEL: define i32 @bar5() {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: store [2 x i128] zeroinitializer, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
@@ -159,7 +154,6 @@ define i32 @bar6(ptr %arg) {
; CHECK-LABEL: define i32 @bar6(
; CHECK-SAME: ptr [[ARG:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[ARG]] to i64
@@ -191,7 +185,6 @@ define i32 @bar7(ptr %arg) {
; CHECK-LABEL: define i32 @bar7(
; CHECK-SAME: ptr [[ARG:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[ARG]] to i64
@@ -225,7 +218,6 @@ define dso_local i64 @many_args() {
; CHECK-LABEL: define dso_local i64 @many_args() {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 0, [[TMP0]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i64 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: store i64 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
diff --git a/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppcle.ll b/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppcle.ll
index 0652d6c18d73f6..aabb3b859cdf55 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppcle.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/PowerPC32/vararg-ppcle.ll
@@ -7,8 +7,7 @@ target triple = "powerpc64le--linux"
define i32 @foo(i32 %guard, ...) {
; CHECK-LABEL: define i32 @foo(
; CHECK-SAME: i32 [[GUARD:%.*]], ...) {
-; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
+; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
; CHECK-NEXT: [[TMP3:%.*]] = alloca i8, i64 [[TMP2]], align 8
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP3]], i8 0, i64 [[TMP2]], i1 false)
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 800)
@@ -64,7 +63,6 @@ declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #1
define i32 @bar() {
; CHECK-LABEL: define i32 @bar() {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: store i32 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
@@ -91,7 +89,6 @@ define i32 @bar() {
define i32 @bar2() {
; CHECK-LABEL: define i32 @bar2() {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
@@ -115,7 +112,6 @@ define i32 @bar2() {
define i32 @bar4() {
; CHECK-LABEL: define i32 @bar4() {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: store [2 x i64] zeroinitializer, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
@@ -136,7 +132,6 @@ define i32 @bar4() {
define i32 @bar5() {
; CHECK-LABEL: define i32 @bar5() {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: store [2 x i128] zeroinitializer, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
@@ -158,7 +153,6 @@ define i32 @bar6(ptr %arg) {
; CHECK-LABEL: define i32 @bar6(
; CHECK-SAME: ptr [[ARG:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[ARG]] to i64
@@ -190,7 +184,6 @@ define i32 @bar7(ptr %arg) {
; CHECK-LABEL: define i32 @bar7(
; CHECK-SAME: ptr [[ARG:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[ARG]] to i64
@@ -223,7 +216,6 @@ define dso_local i64 @many_args() {
; CHECK-LABEL: define dso_local i64 @many_args() {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 0, [[TMP0]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i64 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: store i64 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
diff --git a/llvm/test/Instrumentation/MemorySanitizer/RISCV32/vararg-riscv32.ll b/llvm/test/Instrumentation/MemorySanitizer/RISCV32/vararg-riscv32.ll
index 149b7c9190cefb..3eccfb3170e242 100644
--- a/llvm/test/Instrumentation/MemorySanitizer/RISCV32/vararg-riscv32.ll
+++ b/llvm/test/Instrumentation/MemorySanitizer/RISCV32/vararg-riscv32.ll
@@ -7,8 +7,7 @@ target triple = "mips64--linux"
define i32 @foo(i32 %guard, ...) {
; CHECK-LABEL: define i32 @foo(
; CHECK-SAME: i32 [[GUARD:%.*]], ...) {
-; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
+; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
; CHECK-NEXT: [[TMP3:%.*]] = alloca i8, i64 [[TMP2]], align 8
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP3]], i8 0, i64 [[TMP2]], i1 false)
; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 800)
@@ -58,7 +57,6 @@ declare void @llvm.lifetime.end.p0(i64, ptr nocapture) #1
define i32 @bar() {
; CHECK-LABEL: define i32 @bar() {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: store i32 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
@@ -87,7 +85,6 @@ declare i32 @foo2(i32 %g1, i32 %g2, ...)
define i32 @bar2() {
; CHECK-LABEL: define i32 @bar2() {
; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP2:%.*]] = add i64 0, [[TMP1]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: store i32 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
@@ -113,7 +110,6 @@ define dso_local i64 @many_args() {
; CHECK-LABEL: define dso_local i64 @many_args() {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8
-; CHECK-NEXT: [[TMP1:%.*]] = add i64 0, [[TMP0]]
; CHECK-NEXT: call void @llvm.donothing()
; CHECK-NEXT: store i64 0, ptr @__msan_param_tls, align 8
; CHECK-NEXT: store i64 0, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8
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