[llvm] [RISCV] Implement tail call optimization in machine outliner (PR #115297)
Mark Goncharov via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 13 23:55:29 PST 2024
================
@@ -3054,6 +3089,13 @@ MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall(
Module &M, MachineBasicBlock &MBB, MachineBasicBlock::iterator &It,
MachineFunction &MF, outliner::Candidate &C) const {
+ if (C.CallConstructionID == MachineOutlinerTailCall) {
+ It = MBB.insert(It, BuildMI(MF, DebugLoc(), get(RISCV::PseudoTAIL))
----------------
mga-sc wrote:
Thanks for the comment, I did not consider the case of the influence of registers x6 and x7 before relaxation. Apparently, even llvm-test-suite didn't get such case.
I rewrote verification algorithm for tail call. If we modify X6/X7 (Specific register get from enabled extensions info) earlier than reads from X6/X7, than my optimization can be applied.
https://github.com/llvm/llvm-project/pull/115297
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