[llvm] [RISCV][MachineVerifier] Use RegUnit for register liveness checking (PR #115980)

[Piyou Chen via llvm-commits]

================
@@ -3035,6 +3035,16 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
 
             if (llvm::is_contained(TRI->subregs(MOP.getReg()), Reg))
               Bad = false;
+
+            if (any_of(TRI->subregs(MOP.getReg()),
----------------
BeMg wrote:

We would encounter problems if we were to drop the outer any_of with subregs().

Take this testcase as example:

https://github.com/llvm/llvm-project/blob/main/llvm/test/MachineVerifier/AMDGPU/verifier-implicit-virtreg-invalid-physreg-liveness.mir
```
# RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck -check-prefix=ERROR %s

# When the verifier was detecting the invalid liveness for vcc, it would assert when trying to iterate the subregisters of the implicit virtual register use.


# ERROR: *** Bad machine code: Using an undefined physical register ***
# ERROR: instruction: S_ENDPGM 0, implicit %0:vgpr_32, implicit $vcc
# ERROR: operand 2:   implicit $vcc

...

name: invalid_implicit_physreg_use_with_implicit_virtreg
tracksRegLiveness: true

body:             |
  bb.0:
    %0:vgpr_32 = IMPLICIT_DEF
    S_ENDPGM 0, implicit %0, implicit $vcc

...
```

The verification process will try to check if $vcc belongs to $vcc, which will always evaluate to true.



https://github.com/llvm/llvm-project/pull/115980