[llvm] [RISCV] Add an implementation of findRepresentativeClass to assign i32 to GPRRegClass for RV64. (PR #116165)

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git-clang-format --diff 5a2888ddbd7a601c8ad6bf7b5f13bf77318e4a4d 4928effc2ef653e0bdc54bb79f8015c696e21436 --extensions h,cpp -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVISelLowering.h
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View the diff from clang-format here.
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diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f191b4e9cb..2e157c7ce1 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -22007,7 +22007,9 @@ RISCVTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
   switch (VT.SimpleTy) {
   default:
     return TargetLowering::findRepresentativeClass(TRI, VT);
-  case MVT::i8: case MVT::i16: case MVT::i32:
+  case MVT::i8:
+  case MVT::i16:
+  case MVT::i32:
     RRC = &RISCV::GPRRegClass;
     break;
   }

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https://github.com/llvm/llvm-project/pull/116165