[llvm] [SDAG][ISel][TableGen] Do not skip through bitcasts when there are predicate calls (PR #116075)

[Yingwei Zheng via llvm-commits]

https://github.com/dtcxzyw updated https://github.com/llvm/llvm-project/pull/116075

>From 743a7d8a9dea7c1705758dc224908a6f99f34448 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Wed, 13 Nov 2024 23:35:59 +0800
Subject: [PATCH 1/3] [LoongArch] Add pre-commit tests. NFC.

---
 llvm/test/CodeGen/LoongArch/lsx/pr116008.ll | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)
 create mode 100644 llvm/test/CodeGen/LoongArch/lsx/pr116008.ll

diff --git a/llvm/test/CodeGen/LoongArch/lsx/pr116008.ll b/llvm/test/CodeGen/LoongArch/lsx/pr116008.ll
new file mode 100644
index 00000000000000..2087cff5c884d7
--- /dev/null
+++ b/llvm/test/CodeGen/LoongArch/lsx/pr116008.ll
@@ -0,0 +1,16 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+
+define <4 x i32> @xor_shl_splat_vec_one(i32 %x, <4 x i32> %y) nounwind {
+; CHECK-LABEL: xor_shl_splat_vec_one:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vrepli.w $vr1, 1
+; CHECK-NEXT:    vbitrev.w $vr0, $vr1, $vr0
+; CHECK-NEXT:    ret
+entry:
+  %ins = insertelement <4 x i32> poison, i32 %x, i64 0
+  %splat = shufflevector <4 x i32> %ins, <4 x i32> poison, <4 x i32> zeroinitializer
+  %shl = shl <4 x i32> %splat, %y
+  %xor = xor <4 x i32> %shl, splat (i32 1)
+  ret <4 x i32> %xor
+}

>From efae63a6538dd0db366d3b3695822ad22149480d Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Wed, 13 Nov 2024 23:52:36 +0800
Subject: [PATCH 2/3] [SDAG][ISel][TableGen] Do not skip through bitcasts when
 there are predicate calls

---
 llvm/test/CodeGen/LoongArch/lsx/pr116008.ll       | 5 +++--
 llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp | 2 +-
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/llvm/test/CodeGen/LoongArch/lsx/pr116008.ll b/llvm/test/CodeGen/LoongArch/lsx/pr116008.ll
index 2087cff5c884d7..ba8ffc34931893 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/pr116008.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/pr116008.ll
@@ -4,8 +4,9 @@
 define <4 x i32> @xor_shl_splat_vec_one(i32 %x, <4 x i32> %y) nounwind {
 ; CHECK-LABEL: xor_shl_splat_vec_one:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vrepli.w $vr1, 1
-; CHECK-NEXT:    vbitrev.w $vr0, $vr1, $vr0
+; CHECK-NEXT:    vreplgr2vr.w $vr1, $a0
+; CHECK-NEXT:    vsll.w $vr0, $vr1, $vr0
+; CHECK-NEXT:    vbitrevi.w $vr0, $vr0, 0
 ; CHECK-NEXT:    ret
 entry:
   %ins = insertelement <4 x i32> poison, i32 %x, i64 0
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index c8186d6e69523f..cfd125dac87f97 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -3055,7 +3055,7 @@ static bool SimplifyTree(TreePatternNodePtr &N) {
       N->getExtType(0).isValueTypeByHwMode(false) &&
       !N->getExtType(0).empty() &&
       N->getExtType(0) == N->getChild(0).getExtType(0) &&
-      N->getName().empty()) {
+      N->getName().empty() && N->getPredicateCalls().empty()) {
     N = N->getChildShared(0);
     SimplifyTree(N);
     return true;

>From 708be17c1e1683c9db13b75792ad4c7e90d2d871 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: Thu, 14 Nov 2024 10:58:15 +0800
Subject: [PATCH 3/3] [SDAG][ISel][TableGen] Report error for trivial
 bitconvert node with predicate calls

---
 llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td |  6 ++----
 llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp  | 10 +++++++++-
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
index 250896cbbe5f7a..1a267b3e42a30d 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
@@ -74,8 +74,7 @@ class VecCond<SDPatternOperator OpNode, ValueType TyNode,
   let usesCustomInserter = 1;
 }
 
-def vsplat_imm_eq_1 : PatFrags<(ops), [(build_vector),
-                                       (bitconvert (v4i32 (build_vector)))], [{
+def vsplat_imm_eq_1 : PatFrags<(ops), [(build_vector)], [{
   APInt Imm;
   EVT EltTy = N->getValueType(0).getVectorElementType();
 
@@ -116,8 +115,7 @@ def vsplati32_imm_eq_31 : PatFrags<(ops), [(build_vector)], [{
   return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&
          Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 31;
 }]>;
-def vsplati64_imm_eq_63 : PatFrags<(ops), [(build_vector),
-                                           (bitconvert (v4i32 (build_vector)))], [{
+def vsplati64_imm_eq_63 : PatFrags<(ops), [(build_vector)], [{
   APInt Imm;
   EVT EltTy = N->getValueType(0).getVectorElementType();
 
diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
index cfd125dac87f97..163a1a78a2ec40 100644
--- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp
@@ -3055,7 +3055,15 @@ static bool SimplifyTree(TreePatternNodePtr &N) {
       N->getExtType(0).isValueTypeByHwMode(false) &&
       !N->getExtType(0).empty() &&
       N->getExtType(0) == N->getChild(0).getExtType(0) &&
-      N->getName().empty() && N->getPredicateCalls().empty()) {
+      N->getName().empty()) {
+    if (!N->getPredicateCalls().empty()) {
+      std::string Str;
+      raw_string_ostream OS(Str);
+      OS << *N
+         << "\n trivial bitconvert node should not have predicate calls\n";
+      PrintFatalError(Str);
+      return false;
+    }
     N = N->getChildShared(0);
     SimplifyTree(N);
     return true;