[llvm] [RISCV][GISel] Add manual isel for s16 load/store for the GPR bank. (PR #116111)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 13 15:18:08 PST 2024
================
@@ -786,6 +803,54 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
return selectMergeValues(MI, MIB);
case TargetOpcode::G_UNMERGE_VALUES:
return selectUnmergeValues(MI, MIB);
+ case TargetOpcode::G_LOAD:
+ case TargetOpcode::G_STORE: {
+ GLoadStore &LdSt = cast<GLoadStore>(MI);
+ LLT PtrTy = MRI->getType(LdSt.getPointerReg());
+
+ if (PtrTy != LLT::pointer(0, STI.getXLen())) {
+ LLVM_DEBUG(dbgs() << "Load/Store pointer has type: " << PtrTy
+ << ", expected: " << LLT::pointer(0, STI.getXLen())
+ << '\n');
+ return false;
+ }
+
+#ifndef NDEBUG
+ const RegisterBank &PtrRB =
+ *RBI.getRegBank(LdSt.getPointerReg(), *MRI, TRI);
+ // Check that the pointer register is valid.
+ assert(PtrRB.getID() == RISCV::GPRBRegBankID &&
+ "Load/Store pointer operand isn't a GPR");
+#endif
+
+ unsigned MemSizeInBits = LdSt.getMemSizeInBits().getValue();
+
+ const Register ValReg = LdSt.getReg(0);
+ const RegisterBank &RB = *RBI.getRegBank(ValReg, *MRI, TRI);
+
+ const unsigned NewOpc =
+ selectLoadStoreOp(MI.getOpcode(), RB.getID(), MemSizeInBits);
+ if (NewOpc == MI.getOpcode())
+ return false;
+
+ // Check if we can fold anything into the addressing mode.
+ auto AddrModeFns = selectAddrRegImm(MI.getOperand(1));
+ if (!AddrModeFns)
+ return false;
+
+ // Folded something. Create a new instruction and return it.
+ auto NewInst = MIB.buildInstr(NewOpc, {}, {}, MI.getFlags());
+ if (isa<GStore>(MI))
+ NewInst.addUse(ValReg);
+ else
+ NewInst.addDef(ValReg);
+ NewInst.cloneMemRefs(MI);
+ for (auto &Fn : *AddrModeFns)
+ Fn(NewInst);
+ MI.eraseFromParent();
+
+ return constrainSelectedInstRegOperands(*NewInst, TII, TRI, RBI);
----------------
topperc wrote:
I think I've traced it back to `ForceArbitraryInstResultType`. Which just picks the first type in the set. Which is probably ordered by the MVT enum.
```
/// Given a pattern result with an unresolved type, see if we can find one
/// instruction with an unresolved result type. Force this result type to an
/// arbitrary element if it's possible types to converge results.
static bool ForceArbitraryInstResultType(TreePatternNode &N, TreePattern &TP) {
```
https://github.com/llvm/llvm-project/pull/116111
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