[llvm] AMDGPU: Disable pattern matching from x&(-1>>(32-y) to "bfe x, 0, y" (PR #116115)

[Changpeng Fang via llvm-commits]

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@@ -99,11 +99,21 @@ define i32 @bzhi32_b4_commutative(i32 %val, i32 %numlowbits) nounwind {
 ; ---------------------------------------------------------------------------- ;
 
 define i32 @bzhi32_c0(i32 %val, i32 %numlowbits) nounwind {
-; GCN-LABEL: bzhi32_c0:
-; GCN:       ; %bb.0:
-; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-NEXT:    v_bfe_u32 v0, v0, 0, v1
-; GCN-NEXT:    s_setpc_b64 s[30:31]
+; SI-LABEL: bzhi32_c0:
----------------
changpeng wrote:

  Frankly speaking, I have difficulty in understanding what is canonical here.  Is the following IR still canonical?
  And do you mean we can check MaxActiveBits to allow the pattern?  Thanks.
    
  %low5bits      = and i32 %numlowbits, 31
  %numhighbits = sub i32 32, %numlowbits
  %mask = lshr i32 -1, %numhighbits
  %masked = and i32 %mask, %val

https://github.com/llvm/llvm-project/pull/116115