[llvm] fd2e400 - [RISCV] Add XLenVT casts in isel patterns that output 2 GPR instructions.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2024-11-13T14:43:38-08:00
New Revision: fd2e4004cd01cd1cdf65cf643ca9c178c91741dc

URL: https://github.com/llvm/llvm-project/commit/fd2e4004cd01cd1cdf65cf643ca9c178c91741dc
DIFF: https://github.com/llvm/llvm-project/commit/fd2e4004cd01cd1cdf65cf643ca9c178c91741dc.diff

LOG: [RISCV] Add XLenVT casts in isel patterns that output 2 GPR instructions.

See #81192 for why we need to do this.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZb.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 39eff7dcead6e3..ccb851f9322d62 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -596,7 +596,7 @@ def : Pat<(and (or (shl GPR:$rs2, (XLenVT 8)),
           (PACKH GPR:$rs1, GPR:$rs2)>;
 def : Pat<(or (shl (zexti8 (XLenVT GPR:$rs2)), (XLenVT 24)),
               (shl (zexti8 (XLenVT GPR:$rs1)), (XLenVT 16))),
-          (SLLI (PACKH GPR:$rs1, GPR:$rs2), (XLenVT 16))>;
+          (SLLI (XLenVT (PACKH GPR:$rs1, GPR:$rs2)), (XLenVT 16))>;
 
 def : Pat<(binop_allhusers<or> (shl GPR:$rs2, (XLenVT 8)),
                                (zexti8 (XLenVT GPR:$rs1))),
@@ -612,7 +612,8 @@ def : Pat<(or (or
               (or
                   (shl (zexti8 (XLenVT GPR:$op0rs2)), (XLenVT 8)),
                   (zexti8 (XLenVT GPR:$op0rs1)))),
-          (PACK (PACKH GPR:$op0rs1, GPR:$op0rs2), (PACKH GPR:$op1rs1, GPR:$op1rs2))>;
+          (PACK (XLenVT (PACKH GPR:$op0rs1, GPR:$op0rs2)),
+                (XLenVT (PACKH GPR:$op1rs1, GPR:$op1rs2)))>;
 }
 
 let Predicates = [HasStdExtZbkb, IsRV64] in {