[llvm] 6684eb4 - [RISCV][GISel] Remove IR section from a couple MIR tests. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 13 13:01:33 PST 2024
Author: Craig Topper
Date: 2024-11-13T13:01:17-08:00
New Revision: 6684eb4d6c9ac2b1ec35cf7d0df1344bfe81ade1
URL: https://github.com/llvm/llvm-project/commit/6684eb4d6c9ac2b1ec35cf7d0df1344bfe81ade1
DIFF: https://github.com/llvm/llvm-project/commit/6684eb4d6c9ac2b1ec35cf7d0df1344bfe81ade1.diff
LOG: [RISCV][GISel] Remove IR section from a couple MIR tests. NFC
Added:
Modified:
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir
llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
index d49afb20974c34..36c604d4f5c529 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir
@@ -2,25 +2,6 @@
# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
# RUN: | FileCheck %s
---- |
- define void @load_i8(ptr %addr) { ret void }
- define void @load_i16(ptr %addr) { ret void }
- define void @load_i32(ptr %addr) { ret void }
- define void @zextload_i8(ptr %addr) { ret void }
- define void @zextload_i16(ptr %addr) { ret void }
- define void @sextload_i8(ptr %addr) { ret void }
- define void @sextload_i16(ptr %addr) { ret void }
- define void @load_p0(ptr %addr) { ret void }
- define void @load_fi_i32() {
- %ptr0 = alloca i32
- ret void
- }
- define void @load_fi_gep_i32() {
- %ptr0 = alloca [2 x i32]
- ret void
- }
- define void @load_gep_i32(ptr %addr) { ret void }
-...
---
name: load_i8
legalized: true
@@ -204,15 +185,15 @@ regBankSelected: true
tracksRegLiveness: true
stack:
- - { id: 0, name: ptr0, offset: 0, size: 4, alignment: 4 }
+ - { id: 0, offset: 0, size: 4, alignment: 4 }
body: |
bb.0:
; CHECK-LABEL: name: load_fi_i32
- ; CHECK: [[LW:%[0-9]+]]:gpr = LW %stack.0.ptr0, 0 :: (load (s32))
+ ; CHECK: [[LW:%[0-9]+]]:gpr = LW %stack.0, 0 :: (load (s32))
; CHECK-NEXT: $x10 = COPY [[LW]]
; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
+ %0:gprb(p0) = G_FRAME_INDEX %stack.0
%1:gprb(s32) = G_LOAD %0(p0) :: (load (s32))
$x10 = COPY %1(s32)
PseudoRET implicit $x10
@@ -225,15 +206,15 @@ regBankSelected: true
tracksRegLiveness: true
stack:
- - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 4 }
+ - { id: 0, offset: 0, size: 8, alignment: 4 }
body: |
bb.0:
; CHECK-LABEL: name: load_fi_gep_i32
- ; CHECK: [[LW:%[0-9]+]]:gpr = LW %stack.0.ptr0, 4 :: (load (s32))
+ ; CHECK: [[LW:%[0-9]+]]:gpr = LW %stack.0, 4 :: (load (s32))
; CHECK-NEXT: $x10 = COPY [[LW]]
; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
+ %0:gprb(p0) = G_FRAME_INDEX %stack.0
%1:gprb(s32) = G_CONSTANT i32 4
%2:gprb(p0) = G_PTR_ADD %0(p0), %1(s32)
%3:gprb(s32) = G_LOAD %2(p0) :: (load (s32))
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
index 8dc3bd1778e399..647e1e5287a80b 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv64.mir
@@ -2,31 +2,6 @@
# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
# RUN: | FileCheck %s
---- |
- define void @load_i8_i64(ptr %addr) { ret void }
- define void @load_i16_i64(ptr %addr) { ret void }
- define void @load_i32_i64(ptr %addr) { ret void }
- define void @load_i64_i64(ptr %addr) { ret void }
- define void @load_p0(ptr %addr) { ret void }
- define void @zextload_i8_i64(ptr %addr) { ret void }
- define void @zextload_i16_i64(ptr %addr) { ret void }
- define void @zextload_i32_i64(ptr %addr) { ret void }
- define void @sextload_i8_i64(ptr %addr) { ret void }
- define void @sextload_i16_i64(ptr %addr) { ret void }
- define void @sextload_i32_i64(ptr %addr) { ret void }
- define void @load_i8_i32(ptr %addr) { ret void }
- define void @load_i16_i32(ptr %addr) { ret void }
- define void @load_i32_i32(ptr %addr) { ret void }
- define void @load_fi_i64() {
- %ptr0 = alloca i64
- ret void
- }
- define void @load_fi_gep_i64_i64() {
- %ptr0 = alloca [2 x i64]
- ret void
- }
- define void @load_gep_i64_i64(ptr %addr) { ret void }
-...
---
name: load_i8_i64
legalized: true
@@ -342,15 +317,15 @@ regBankSelected: true
tracksRegLiveness: true
stack:
- - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
+ - { id: 0, offset: 0, size: 8, alignment: 8 }
body: |
bb.0:
; CHECK-LABEL: name: load_fi_i64
- ; CHECK: [[LD:%[0-9]+]]:gpr = LD %stack.0.ptr0, 0 :: (load (s64))
+ ; CHECK: [[LD:%[0-9]+]]:gpr = LD %stack.0, 0 :: (load (s64))
; CHECK-NEXT: $x10 = COPY [[LD]]
; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
+ %0:gprb(p0) = G_FRAME_INDEX %stack.0
%1:gprb(s64) = G_LOAD %0(p0) :: (load (s64))
$x10 = COPY %1(s64)
PseudoRET implicit $x10
@@ -363,15 +338,15 @@ regBankSelected: true
tracksRegLiveness: true
stack:
- - { id: 0, name: ptr0, offset: 0, size: 16, alignment: 8 }
+ - { id: 0, offset: 0, size: 16, alignment: 8 }
body: |
bb.0:
; CHECK-LABEL: name: load_fi_gep_i64_i64
- ; CHECK: [[LD:%[0-9]+]]:gpr = LD %stack.0.ptr0, 8 :: (load (s64))
+ ; CHECK: [[LD:%[0-9]+]]:gpr = LD %stack.0, 8 :: (load (s64))
; CHECK-NEXT: $x10 = COPY [[LD]]
; CHECK-NEXT: PseudoRET implicit $x10
- %0:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
+ %0:gprb(p0) = G_FRAME_INDEX %stack.0
%1:gprb(s64) = G_CONSTANT i64 8
%2:gprb(p0) = G_PTR_ADD %0(p0), %1(s64)
%3:gprb(s64) = G_LOAD %2(p0) :: (load (s64))
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir
index d320fb755da97a..e4111417ece672 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv32.mir
@@ -2,21 +2,6 @@
# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
# RUN: | FileCheck %s
#
---- |
- define void @store_i8(i8 %val, ptr %addr) { ret void }
- define void @store_i16(i16 %val, ptr %addr) { ret void }
- define void @store_i32(i32 %val, ptr %addr) { ret void }
- define void @store_p0(ptr %val, ptr %addr) { ret void }
- define void @store_fi_i32(ptr %val) {
- %ptr0 = alloca i32
- ret void
- }
- define void @store_fi_gep_i32(ptr %val) {
- %ptr0 = alloca [2 x i32]
- ret void
- }
- define void @store_gep_i32(i32 %val, ptr %addr) { ret void }
-...
---
name: store_i8
legalized: true
@@ -112,7 +97,7 @@ regBankSelected: true
tracksRegLiveness: true
stack:
- - { id: 0, name: ptr0, offset: 0, size: 4, alignment: 4 }
+ - { id: 0, offset: 0, size: 4, alignment: 4 }
body: |
bb.0:
@@ -122,10 +107,10 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: SW [[COPY]], %stack.0.ptr0, 0 :: (store (s32))
+ ; CHECK-NEXT: SW [[COPY]], %stack.0, 0 :: (store (s32))
; CHECK-NEXT: PseudoRET
%0:gprb(s32) = COPY $x10
- %1:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
+ %1:gprb(p0) = G_FRAME_INDEX %stack.0
G_STORE %0(s32), %1(p0) :: (store (s32))
PseudoRET
@@ -137,7 +122,7 @@ regBankSelected: true
tracksRegLiveness: true
stack:
- - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 4 }
+ - { id: 0, offset: 0, size: 8, alignment: 4 }
body: |
bb.0:
@@ -147,10 +132,10 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: SW [[COPY]], %stack.0.ptr0, 4 :: (store (s32))
+ ; CHECK-NEXT: SW [[COPY]], %stack.0, 4 :: (store (s32))
; CHECK-NEXT: PseudoRET
%0:gprb(s32) = COPY $x10
- %1:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
+ %1:gprb(p0) = G_FRAME_INDEX %stack.0
%2:gprb(s32) = G_CONSTANT i32 4
%3:gprb(p0) = G_PTR_ADD %1(p0), %2(s32)
G_STORE %0(s32), %3(p0) :: (store (s32))
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir
index 56d45016844b0b..385a330a97a175 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/store-rv64.mir
@@ -2,25 +2,6 @@
# RUN: llc -mtriple=riscv64 -run-pass=instruction-select %s -o - \
# RUN: | FileCheck %s
---- |
- define void @store_i8_i64(i8 %val, ptr %addr) { ret void }
- define void @store_i16_i64(i16 %val, ptr %addr) { ret void }
- define void @store_i32_i64(i32 %val, ptr %addr) { ret void }
- define void @store_i64_i64(i32 %val, ptr %addr) { ret void }
- define void @store_p0(ptr %val, ptr %addr) { ret void }
- define void @truncstore_i8_i32(i8 %val, ptr %addr) { ret void }
- define void @truncstore_i16_i32(i8 %val, ptr %addr) { ret void }
- define void @store_i32_i32(i8 %val, ptr %addr) { ret void }
- define void @store_fi_i64_i64(ptr %val) {
- %ptr0 = alloca i64
- ret void
- }
- define void @store_fi_gep_i64_i64(ptr %val) {
- %ptr0 = alloca [2 x i64]
- ret void
- }
- define void @store_gep_i64_i64(i32 %val, ptr %addr) { ret void }
-...
---
name: store_i8_i64
legalized: true
@@ -219,7 +200,7 @@ regBankSelected: true
tracksRegLiveness: true
stack:
- - { id: 0, name: ptr0, offset: 0, size: 8, alignment: 8 }
+ - { id: 0, offset: 0, size: 8, alignment: 8 }
body: |
bb.0:
@@ -229,10 +210,10 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: SD [[COPY]], %stack.0.ptr0, 0 :: (store (s64))
+ ; CHECK-NEXT: SD [[COPY]], %stack.0, 0 :: (store (s64))
; CHECK-NEXT: PseudoRET
%0:gprb(s64) = COPY $x10
- %1:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
+ %1:gprb(p0) = G_FRAME_INDEX %stack.0
G_STORE %0(s64), %1(p0) :: (store (s64))
PseudoRET
@@ -244,7 +225,7 @@ regBankSelected: true
tracksRegLiveness: true
stack:
- - { id: 0, name: ptr0, offset: 0, size: 16, alignment: 8 }
+ - { id: 0, offset: 0, size: 16, alignment: 8 }
body: |
bb.0:
@@ -254,10 +235,10 @@ body: |
; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
- ; CHECK-NEXT: SD [[COPY]], %stack.0.ptr0, 8 :: (store (s64))
+ ; CHECK-NEXT: SD [[COPY]], %stack.0, 8 :: (store (s64))
; CHECK-NEXT: PseudoRET
%0:gprb(s64) = COPY $x10
- %1:gprb(p0) = G_FRAME_INDEX %stack.0.ptr0
+ %1:gprb(p0) = G_FRAME_INDEX %stack.0
%2:gprb(s64) = G_CONSTANT i64 8
%3:gprb(p0) = G_PTR_ADD %1(p0), %2(s64)
G_STORE %0(s64), %3(p0) :: (store (s64))
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